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Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git]
/
manual
/
APPNOTE_011_Design_Investigation
/
example.v
1
module example(input clk, a, b, c,
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output reg [1:0] y);
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always @(posedge clk)
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if (c)
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y <= c ? a + b : 2'd0;
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endmodule