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Merge pull request #1894 from YosysHQ/mingw_fix
[yosys.git] / manual / APPNOTE_011_Design_Investigation / example.ys
1 read_verilog example.v
2 show -format dot -prefix example_00
3 proc
4 show -format dot -prefix example_01
5 opt
6 show -format dot -prefix example_02
7
8 cd example
9 select t:$add
10 show -format dot -prefix example_03
11