kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git] / manual / APPNOTE_011_Design_Investigation / foobaraddsub.v
1 module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
2 input [7:0] a, b, c, d;
3 output [7:0] fa, fs, ba, bs;
4 assign fa = a + (* foo *) b;
5 assign fs = a - (* foo *) b;
6 assign ba = c + (* bar *) d;
7 assign bs = c - (* bar *) d;
8 endmodule