manual/APPNOTE_011_Design_Investigation/memdemo.v

   1 module memdemo(clk, d, y);
   2
   3 input clk;
   4 input [3:0] d;
   5 output reg [3:0] y;
   6
   7 integer i;
   8 reg [1:0] s1, s2;
   9 reg [3:0] mem [0:3];
  10
  11 always @(posedge clk) begin
  12     for (i = 0; i < 4; i = i+1)
  13         mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
  14     { s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
  15     mem[s1] <= d;
  16     y <= mem[s2];
  17 end
  18
  19 endmodule