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kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git]
/
manual
/
APPNOTE_011_Design_Investigation
/
primetest.v
1
module primetest(p, a, b, ok);
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input [15:0] p, a, b;
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output ok = p != a*b || a == 1 || b == 1;
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endmodule