2 \chapter{Internal Cell Library
}
3 \label{chapter:celllib
}
5 Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
6 objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
9 This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
10 are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
11 cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
12 gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
13 from this category operate on single bit signals.
17 Most of the RTL cells closely resemble the operators available in HDLs such as
18 Verilog or VHDL. Therefore Verilog operators are used in the following sections
19 to define the behaviour of the RTL cells.
21 Note that all RTL cells have parameters indicating the size of inputs and outputs. When
22 passes modify RTL cells they must always keep the values of these parameters in sync with
23 the size of the signals connected to the inputs and outputs.
25 Simulation models for the RTL cells can be found in the file
{\tt techlibs/common/simlib.v
} in the Yosys
28 \subsection{Unary Operators
}
30 All unary RTL cells have one input port
\B{A
} and one output port
\B{Y
}. They also
31 have the following parameters:
34 \item \B{A
\_SIGNED} \\
35 Set to a non-zero value if the input
\B{A
} is signed and therefore should be sign-extended
39 The width of the input port
\B{A
}.
42 The width of the output port
\B{Y
}.
45 Table~
\ref{tab:CellLib_unary
} lists all cells for unary RTL operators.
50 Verilog & Cell Type \\
52 \lstinline[language=Verilog
]; Y = ~A ; &
{\tt \$not
} \\
53 \lstinline[language=Verilog
]; Y = +A ; &
{\tt \$pos
} \\
54 \lstinline[language=Verilog
]; Y = -A ; &
{\tt \$neg
} \\
56 \lstinline[language=Verilog
]; Y = &A ; &
{\tt \$reduce
\_and} \\
57 \lstinline[language=Verilog
]; Y = |A ; &
{\tt \$reduce
\_or} \\
58 \lstinline[language=Verilog
]; Y = ^A ; &
{\tt \$reduce
\_xor} \\
59 \lstinline[language=Verilog
]; Y = ~^A ; &
{\tt \$reduce
\_xnor} \\
61 \lstinline[language=Verilog
]; Y = |A ; &
{\tt \$reduce
\_bool} \\
62 \lstinline[language=Verilog
]; Y = !A ; &
{\tt \$logic
\_not}
64 \caption{Cell types for unary operators with their corresponding Verilog expressions.
}
65 \label{tab:CellLib_unary
}
68 For the unary cells that output a logical value (
{\tt \$reduce
\_and},
{\tt \$reduce
\_or},
69 {\tt \$reduce
\_xor},
{\tt \$reduce
\_xnor},
{\tt \$reduce
\_bool},
{\tt \$logic
\_not}),
70 when the
\B{Y
\_WIDTH} parameter is greater than
1, the output is zero-extended,
71 and only the least significant bit varies.
73 Note that
{\tt \$reduce
\_or} and
{\tt \$reduce
\_bool} actually represent the same
74 logic function. But the HDL frontends generate them in different situations. A
75 {\tt \$reduce
\_or} cell is generated when the prefix
{\tt |
} operator is being used. A
76 {\tt \$reduce
\_bool} cell is generated when a bit vector is used as a condition in
77 an
{\tt if
}-statement or
{\tt ?:
}-expression.
79 \subsection{Binary Operators
}
81 All binary RTL cells have two input ports
\B{A
} and
\B{B
} and one output port
\B{Y
}. They
82 also have the following parameters:
85 \item \B{A
\_SIGNED} \\
86 Set to a non-zero value if the input
\B{A
} is signed and therefore should be sign-extended
90 The width of the input port
\B{A
}.
92 \item \B{B
\_SIGNED} \\
93 Set to a non-zero value if the input
\B{B
} is signed and therefore should be sign-extended
97 The width of the input port
\B{B
}.
100 The width of the output port
\B{Y
}.
103 Table~
\ref{tab:CellLib_binary
} lists all cells for binary RTL operators.
107 \begin{tabular
}[t
]{ll
}
108 Verilog & Cell Type \\
110 \lstinline[language=Verilog
]; Y = A & B; &
{\tt \$and
} \\
111 \lstinline[language=Verilog
]; Y = A | B; &
{\tt \$or
} \\
112 \lstinline[language=Verilog
]; Y = A ^ B; &
{\tt \$xor
} \\
113 \lstinline[language=Verilog
]; Y = A ~^ B; &
{\tt \$xnor
} \\
115 \lstinline[language=Verilog
]; Y = A << B; &
{\tt \$shl
} \\
116 \lstinline[language=Verilog
]; Y = A >> B; &
{\tt \$shr
} \\
117 \lstinline[language=Verilog
]; Y = A <<< B; &
{\tt \$sshl
} \\
118 \lstinline[language=Verilog
]; Y = A >>> B; &
{\tt \$sshr
} \\
120 \lstinline[language=Verilog
]; Y = A && B; &
{\tt \$logic
\_and} \\
121 \lstinline[language=Verilog
]; Y = A || B; &
{\tt \$logic
\_or} \\
123 \lstinline[language=Verilog
]; Y = A === B; &
{\tt \$eqx
} \\
124 \lstinline[language=Verilog
]; Y = A !== B; &
{\tt \$nex
} \\
127 \begin{tabular
}[t
]{ll
}
128 Verilog & Cell Type \\
130 \lstinline[language=Verilog
]; Y = A < B; &
{\tt \$lt
} \\
131 \lstinline[language=Verilog
]; Y = A <= B; &
{\tt \$le
} \\
132 \lstinline[language=Verilog
]; Y = A == B; &
{\tt \$eq
} \\
133 \lstinline[language=Verilog
]; Y = A != B; &
{\tt \$ne
} \\
134 \lstinline[language=Verilog
]; Y = A >= B; &
{\tt \$ge
} \\
135 \lstinline[language=Verilog
]; Y = A > B; &
{\tt \$gt
} \\
137 \lstinline[language=Verilog
]; Y = A + B; &
{\tt \$add
} \\
138 \lstinline[language=Verilog
]; Y = A - B; &
{\tt \$sub
} \\
139 \lstinline[language=Verilog
]; Y = A * B; &
{\tt \$mul
} \\
140 \lstinline[language=Verilog
]; Y = A / B; &
{\tt \$div
} \\
141 \lstinline[language=Verilog
]; Y = A
% B; & {\tt \$mod} \\
142 \lstinline[language=Verilog
]; Y = A ** B; &
{\tt \$pow
} \\
144 \caption{Cell types for binary operators with their corresponding Verilog expressions.
}
145 \label{tab:CellLib_binary
}
148 The
{\tt \$shl
} and
{\tt \$shr
} cells implement logical shifts, whereas the
{\tt \$sshl
} and
149 {\tt \$sshr
} cells implement arithmetic shifts. The
{\tt \$shl
} and
{\tt \$sshl
} cells implement
150 the same operation. All four of these cells interpret the second operand as unsigned, and require
151 \B{B
\_SIGNED} to be zero.
153 Two additional shift operator cells are available that do not directly correspond to any operator
154 in Verilog,
{\tt \$shift
} and
{\tt \$shiftx
}. The
{\tt \$shift
} cell performs a right logical shift
155 if the second operand is positive (or unsigned), and a left logical shift if it is negative.
156 The
{\tt \$shiftx
} cell performs the same operation as the
{\tt \$shift
} cell, but the vacated bit
157 positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.
159 For the binary cells that output a logical value (
{\tt \$logic
\_and},
{\tt \$logic
\_or},
160 {\tt \$eqx
},
{\tt \$nex
},
{\tt \$lt
},
{\tt \$le
},
{\tt \$eq
},
{\tt \$ne
},
{\tt \$ge
},
161 {\tt \$gt
}), when the
\B{Y
\_WIDTH} parameter is greater than
1, the output is zero-extended,
162 and only the least significant bit varies.
164 \subsection{Multiplexers
}
166 Multiplexers are generated by the Verilog HDL frontend for
{\tt
167 ?:
}-expressions. Multiplexers are also generated by the
{\tt proc
} pass to map the decision trees
168 from RTLIL::Process objects to logic.
170 The simplest multiplexer cell type is
{\tt \$mux
}. Cells of this type have a
\B{WIDTH
} parameter
171 and data inputs
\B{A
} and
\B{B
} and a data output
\B{Y
}, all of the specified width. This cell also
172 has a single bit control input
\B{S
}. If
\B{S
} is
0 the value from the
\B{A
} input is sent to
173 the output, if it is
1 the value from the
\B{B
} input is sent to the output. So the
{\tt \$mux
}
174 cell implements the function
\lstinline[language=Verilog
]; Y = S ? B : A;.
176 The
{\tt \$pmux
} cell is used to multiplex between many inputs using a one-hot select signal. Cells
177 of this type have a
\B{WIDTH
} and a
\B{S
\_WIDTH} parameter and inputs
\B{A
},
\B{B
}, and
\B{S
} and
178 an output
\B{Y
}. The
\B{S
} input is
\B{S
\_WIDTH} bits wide. The
\B{A
} input and the output are both
179 \B{WIDTH
} bits wide and the
\B{B
} input is
\B{WIDTH
}*
\B{S
\_WIDTH} bits wide. When all bits of
180 \B{S
} are zero, the value from
\B{A
} input is sent to the output. If the $n$'th bit from
\B{S
} is
181 set, the value $n$'th
\B{WIDTH
} bits wide slice of the
\B{B
} input is sent to the output. When more
182 than one bit from
\B{S
} is set the output is undefined. Cells of this type are used to model
183 ``parallel cases'' (defined by using the
{\tt parallel
\_case} attribute or detected by
186 The
{\tt \$tribuf
} cell is used to implement tristate logic. Cells of this type have a
\B{WIDTH
}
187 parameter and inputs
\B{A
} and
\B{EN
} and an output
\B{Y
}. The
\B{A
} input and
\B{Y
} output are
188 \B{WIDTH
} bits wide, and the
\B{EN
} input is one bit wide. When
\B{EN
} is
0, the output
\B{Y
}
189 is not driven. When
\B{EN
} is
1, the value from
\B{A
} input is sent to the
\B{Y
} output. Therefore,
190 the
{\tt \$tribuf
} cell implements the function
\lstinline[language=Verilog
]; Y = EN ? A : 'bz;.
192 Behavioural code with cascaded
{\tt if-then-else
}- and
{\tt case
}-statements
193 usually results in trees of multiplexer cells. Many passes (from various
194 optimizations to FSM extraction) heavily depend on these multiplexer trees to
195 understand dependencies between signals. Therefore optimizations should not
196 break these multiplexer trees (e.g.~by replacing a multiplexer between a
197 calculated signal and a constant zero with an
{\tt \$and
} gate).
199 \subsection{Registers
}
201 D-type flip-flops are represented by
{\tt \$dff
} cells. These cells have a clock port
\B{CLK
},
202 an input port
\B{D
} and an output port
\B{Q
}. The following parameters are available for
{\tt \$dff
}
207 The width of input
\B{D
} and output
\B{Q
}.
209 \item \B{CLK
\_POLARITY} \\
210 Clock is active on the positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
211 edge if this parameter is
{\tt 1'b0
}.
214 D-type flip-flops with enable are represented by
{\tt \$dffe
} cells. As the
{\tt \$dff
}
215 cells they have
\B{CLK
},
\B{D
} and
\B{Q
} ports. In addition they also have a single-bit
\B{EN
}
216 input port for the enable pin and the following parameter:
219 \item \B{EN
\_POLARITY} \\
220 The enable input is active-high if this parameter has the value
{\tt 1'b1
} and active-low
221 if this parameter is
{\tt 1'b0
}.
224 D-type flip-flops with asynchronous reset are represented by
{\tt \$adff
} cells. As the
{\tt \$dff
}
225 cells they have
\B{CLK
},
\B{D
} and
\B{Q
} ports. In addition they also have a single-bit
\B{ARST
}
226 input port for the reset pin and the following additional two parameters:
229 \item \B{ARST
\_POLARITY} \\
230 The asynchronous reset is active-high if this parameter has the value
{\tt 1'b1
} and active-low
231 if this parameter is
{\tt 1'b0
}.
233 \item \B{ARST
\_VALUE} \\
234 The state of
\B{Q
} will be set to this value when the reset is active.
237 Note that the
{\tt \$adff
} cell can only be used when the reset value is constant.
240 Usually these cells are generated by the
{\tt proc
} pass using the information
241 in the designs RTLIL::Process objects.
244 D-type flip-flops with asynchronous set and reset are represented by
{\tt \$dffsr
} cells.
245 As the
{\tt \$dff
} cells they have
\B{CLK
},
\B{D
} and
\B{Q
} ports. In addition they also have
246 a single-bit
\B{SET
} input port for the set pin, a single-bit
\B{CLR
} input port for the reset pin,
247 and the following two parameters:
250 \item \B{SET
\_POLARITY} \\
251 The set input is active-high if this parameter has the value
{\tt 1'b1
} and active-low
252 if this parameter is
{\tt 1'b0
}.
254 \item \B{CLR
\_POLARITY} \\
255 The reset input is active-high if this parameter has the value
{\tt 1'b1
} and active-low
256 if this parameter is
{\tt 1'b0
}.
259 When both the set and reset inputs of a
{\tt \$dffsr
} cell are active, the reset input takes
263 Add information about
{\tt \$sr
} cells (set-reset flip-flops),
{\tt \$dlatch
} cells (d-type latches),
264 and
{\tt \$dlatchsr
} cells (d-type latches with set/reset).
267 \subsection{Memories
}
270 Memories are either represented using RTLIL::Memory objects,
{\tt \$memrd
},
{\tt \$memwr
}, and
{\tt \$meminit
}
271 cells, or by
{\tt \$mem
} cells alone.
273 In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
274 size in number of words, etc.) and for each port a
{\tt \$memrd
} (read port) or
{\tt \$memwr
} (write port)
275 cell is created. Having individual cells for read and write ports has the advantage that they can be
276 consolidated using resource sharing passes. In some cases this drastically reduces the number of required
277 ports on the memory cell. In this alternative, memory initialization data is represented by
{\tt \$meminit
} cells,
278 which allow delaying constant folding for initialization addresses and data until after the frontend finishes.
280 The
{\tt \$memrd
} cells have a clock input
\B{CLK
}, an enable input
\B{EN
}, an
281 address input
\B{ADDR
}, and a data output
\B{DATA
}. They also have the
282 following parameters:
286 The name of the RTLIL::Memory object that is associated with this read port.
289 The number of address bits (width of the
\B{ADDR
} input port).
292 The number of data bits (width of the
\B{DATA
} output port).
294 \item \B{CLK
\_ENABLE} \\
295 When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
296 the
\B{CLK
} input is not used.
298 \item \B{CLK
\_POLARITY} \\
299 Clock is active on the positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
300 edge if this parameter is
{\tt 1'b0
}.
302 \item \B{TRANSPARENT
} \\
303 If this parameter is set to
{\tt 1'b1
}, a read and write to the same address in the same cycle will
304 return the new value. Otherwise the old value is returned.
307 The
{\tt \$memwr
} cells have a clock input
\B{CLK
}, an enable input
\B{EN
} (one
308 enable bit for each data bit), an address input
\B{ADDR
} and a data input
309 \B{DATA
}. They also have the following parameters:
313 The name of the RTLIL::Memory object that is associated with this write port.
316 The number of address bits (width of the
\B{ADDR
} input port).
319 The number of data bits (width of the
\B{DATA
} output port).
321 \item \B{CLK
\_ENABLE} \\
322 When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
323 the
\B{CLK
} input is not used.
325 \item \B{CLK
\_POLARITY} \\
326 Clock is active on positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
327 edge if this parameter is
{\tt 1'b0
}.
329 \item \B{PRIORITY
} \\
330 The cell with the higher integer value in this parameter wins a write conflict.
333 The
{\tt \$meminit
} cells have an address input
\B{ADDR
} and a data input
\B{DATA
}, with the width
334 of the
\B{DATA
} port equal to
\B{WIDTH
} parameter times
\B{WORDS
} parameter. Both of the inputs
335 must resolve to a constant for synthesis to succeed.
339 The name of the RTLIL::Memory object that is associated with this initialization cell.
342 The number of address bits (width of the
\B{ADDR
} input port).
345 The number of data bits per memory location.
348 The number of consecutive memory locations initialized by this cell.
350 \item \B{PRIORITY
} \\
351 The cell with the higher integer value in this parameter wins an initialization conflict.
354 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
355 {\tt \$memrd
} and
{\tt \$memwr
} cells. The
{\tt memory
} pass (i.e.~its various sub-passes) migrates
356 {\tt \$dff
} cells into the
{\tt \$memrd
} and
{\tt \$memwr
} cells making them synchronous, then
357 converts them to a single
{\tt \$mem
} cell and (optionally) maps this cell type
358 to
{\tt \$dff
} cells for the individual words and multiplexer-based address decoders for the read and
359 write interfaces. When the last step is disabled or not possible, a
{\tt \$mem
} cell is left in the design.
361 The
{\tt \$mem
} cell provides the following parameters:
365 The name of the original RTLIL::Memory object that became this
{\tt \$mem
} cell.
368 The number of words in the memory.
371 The number of address bits.
374 The number of data bits per word.
377 The initial memory contents.
379 \item \B{RD
\_PORTS} \\
380 The number of read ports on this memory cell.
382 \item \B{RD
\_CLK\_ENABLE} \\
383 This parameter is
\B{RD
\_PORTS} bits wide, containing a clock enable bit for each read port.
385 \item \B{RD
\_CLK\_POLARITY} \\
386 This parameter is
\B{RD
\_PORTS} bits wide, containing a clock polarity bit for each read port.
388 \item \B{RD
\_TRANSPARENT} \\
389 This parameter is
\B{RD
\_PORTS} bits wide, containing a transparent bit for each read port.
391 \item \B{WR
\_PORTS} \\
392 The number of write ports on this memory cell.
394 \item \B{WR
\_CLK\_ENABLE} \\
395 This parameter is
\B{WR
\_PORTS} bits wide, containing a clock enable bit for each write port.
397 \item \B{WR
\_CLK\_POLARITY} \\
398 This parameter is
\B{WR
\_PORTS} bits wide, containing a clock polarity bit for each write port.
401 The
{\tt \$mem
} cell has the following ports:
405 This input is
\B{RD
\_PORTS} bits wide, containing all clock signals for the read ports.
408 This input is
\B{RD
\_PORTS} bits wide, containing all enable signals for the read ports.
410 \item \B{RD
\_ADDR} \\
411 This input is
\B{RD
\_PORTS}*
\B{ABITS
} bits wide, containing all address signals for the read ports.
413 \item \B{RD
\_DATA} \\
414 This input is
\B{RD
\_PORTS}*
\B{WIDTH
} bits wide, containing all data signals for the read ports.
417 This input is
\B{WR
\_PORTS} bits wide, containing all clock signals for the write ports.
420 This input is
\B{WR
\_PORTS}*
\B{WIDTH
} bits wide, containing all enable signals for the write ports.
422 \item \B{WR
\_ADDR} \\
423 This input is
\B{WR
\_PORTS}*
\B{ABITS
} bits wide, containing all address signals for the write ports.
425 \item \B{WR
\_DATA} \\
426 This input is
\B{WR
\_PORTS}*
\B{WIDTH
} bits wide, containing all data signals for the write ports.
429 The
{\tt memory
\_collect} pass can be used to convert discrete
{\tt \$memrd
},
{\tt \$memwr
}, and
{\tt \$meminit
} cells
430 belonging to the same memory to a single
{\tt \$mem
} cell, whereas the
{\tt memory
\_unpack} pass performs the inverse operation.
431 The
{\tt memory
\_dff} pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
432 The
{\tt memory
\_bram} pass can be used to recognize
{\tt \$mem
} cells that can be implemented with a block RAM resource on an FPGA.
433 The
{\tt memory
\_map} pass can be used to implement
{\tt \$mem
} cells as basic logic: word-wide DFFs and address decoders.
435 \subsection{Finite State Machines
}
438 Add a brief description of the
{\tt \$fsm
} cell type.
442 \label{sec:celllib_gates
}
444 For gate level logic networks, fixed function single bit cells are used that do
445 not provide any parameters.
447 Simulation models for these cells can be found in the file
{\tt techlibs/common/simcells.v
} in the Yosys
452 \begin{tabular
}[t
]{ll
}
453 Verilog & Cell Type \\
455 \lstinline[language=Verilog
]; Y = ~A; &
{\tt \$
\_NOT\_} \\
456 \lstinline[language=Verilog
]; Y = A & B; &
{\tt \$
\_AND\_} \\
457 \lstinline[language=Verilog
]; Y = ~(A & B); &
{\tt \$
\_NAND\_} \\
458 \lstinline[language=Verilog
]; Y = A & ~B; &
{\tt \$
\_ANDNOT\_} \\
459 \lstinline[language=Verilog
]; Y = A | B; &
{\tt \$
\_OR\_} \\
460 \lstinline[language=Verilog
]; Y = ~(A | B); &
{\tt \$
\_NOR\_} \\
461 \lstinline[language=Verilog
]; Y = A | ~B; &
{\tt \$
\_ORNOT\_} \\
462 \lstinline[language=Verilog
]; Y = A ^ B; &
{\tt \$
\_XOR\_} \\
463 \lstinline[language=Verilog
]; Y = ~(A ^ B); &
{\tt \$
\_XNOR\_} \\
464 \lstinline[language=Verilog
]; Y = S ? B : A; &
{\tt \$
\_MUX\_} \\
465 \lstinline[language=Verilog
]; Y = EN ? A : 'bz; &
{\tt \$
\_TBUF\_} \\
467 \lstinline[language=Verilog
]; always @(negedge C) Q <= D; &
{\tt \$
\_DFF\_N\_} \\
468 \lstinline[language=Verilog
]; always @(posedge C) Q <= D; &
{\tt \$
\_DFF\_P\_} \\
471 \begin{tabular
}[t
]{llll
}
472 $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
474 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_NN0\_} \\
475 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_NN1\_} \\
476 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_NP0\_} \\
477 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_NP1\_} \\
478 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_PN0\_} \\
479 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_PN1\_} \\
480 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_PP0\_} \\
481 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_PP1\_} \\
483 % FIXME: the layout of this is broken and I have no idea how to fix it
485 \begin{tabular
}[t
]{lll
}
486 $ClkEdge$ & $EnLvl$ & Cell Type \\
488 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFE\_NN\_} \\
489 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFE\_NP\_} \\
490 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFE\_PN\_} \\
491 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFE\_PP\_} \\
493 % FIXME: the layout of this is broken too
495 \begin{tabular
}[t
]{llll
}
496 $ClkEdge$ & $SetLvl$ & $RstLvl$ & Cell Type \\
498 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFSR\_NNN\_} \\
499 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFSR\_NNP\_} \\
500 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFSR\_NPN\_} \\
501 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFSR\_NPP\_} \\
502 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFSR\_PNN\_} \\
503 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFSR\_PNP\_} \\
504 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFFSR\_PPN\_} \\
505 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFFSR\_PPP\_} \\
507 \caption{Cell types for gate level logic networks
}
508 \label{tab:CellLib_gates
}
511 Table~
\ref{tab:CellLib_gates
} lists all cell types used for gate level logic. The cell types
512 {\tt \$
\_NOT\_},
{\tt \$
\_AND\_},
{\tt \$
\_NAND\_},
{\tt \$
\_ANDNOT\_},
{\tt \$
\_OR\_},
{\tt \$
\_NOR\_},
513 {\tt \$
\_ORNOT\_},
{\tt \$
\_XOR\_},
{\tt \$
\_XNOR\_} and
{\tt \$
\_MUX\_} are used to model combinatorial logic.
514 The cell type
{\tt \$
\_TBUF\_} is used to model tristate logic.
516 The cell types
{\tt \$
\_DFF\_N\_} and
{\tt \$
\_DFF\_P\_} represent d-type flip-flops.
518 The cell types
{\tt \$
\_DFFE\_NN\_},
{\tt \$
\_DFFE\_NP\_},
{\tt \$
\_DFFE\_PN\_} and
{\tt \$
\_DFFE\_PP\_}
519 implement d-type flip-flops with enable. The values in the table for these cell types relate to the
520 following Verilog code template.
522 \begin{lstlisting
}[mathescape,language=Verilog
]
523 always @($ClkEdge$ C)
528 The cell types
{\tt \$
\_DFF\_NN0\_},
{\tt \$
\_DFF\_NN1\_},
{\tt \$
\_DFF\_NP0\_},
{\tt \$
\_DFF\_NP1\_},
529 {\tt \$
\_DFF\_PN0\_},
{\tt \$
\_DFF\_PN1\_},
{\tt \$
\_DFF\_PP0\_} and
{\tt \$
\_DFF\_PP1\_} implement
530 d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the
531 following Verilog code template, where
\lstinline[mathescape,language=Verilog
];$RstEdge$; is
\lstinline[language=Verilog
];posedge;
532 if
\lstinline[mathescape,language=Verilog
];$RstLvl$; if
\lstinline[language=Verilog
];
1;, and
\lstinline[language=Verilog
];negedge;
535 \begin{lstlisting
}[mathescape,language=Verilog
]
536 always @($ClkEdge$ C, $RstEdge$ R)
543 The cell types
{\tt \$
\_DFFSR\_NNN\_},
{\tt \$
\_DFFSR\_NNP\_},
{\tt \$
\_DFFSR\_NPN\_},
{\tt \$
\_DFFSR\_NPP\_},
544 {\tt \$
\_DFFSR\_PNN\_},
{\tt \$
\_DFFSR\_PNP\_},
{\tt \$
\_DFFSR\_PPN\_} and
{\tt \$
\_DFFSR\_PPP\_} implement
545 d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the
546 following Verilog code template, where
\lstinline[mathescape,language=Verilog
];$RstEdge$; is
\lstinline[language=Verilog
];posedge;
547 if
\lstinline[mathescape,language=Verilog
];$RstLvl$; if
\lstinline[language=Verilog
];
1;,
\lstinline[language=Verilog
];negedge;
548 otherwise, and
\lstinline[mathescape,language=Verilog
];$SetEdge$; is
\lstinline[language=Verilog
];posedge;
549 if
\lstinline[mathescape,language=Verilog
];$SetLvl$; if
\lstinline[language=Verilog
];
1;,
\lstinline[language=Verilog
];negedge;
552 \begin{lstlisting
}[mathescape,language=Verilog
]
553 always @($ClkEdge$ C, $RstEdge$ R, $SetEdge$ S)
556 else if (S == $SetLvl$)
562 In most cases gate level logic networks are created from RTL networks using the
{\tt techmap
} pass. The flip-flop cells
563 from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the
{\tt dfflibmap
}
564 pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC
\citeweblink{ABC
}
565 using the
{\tt abc
} pass.
568 Add information about
{\tt \$assert
},
{\tt \$assume
},
{\tt \$live
},
{\tt \$fair
},
{\tt \$cover
},
{\tt \$equiv
},
569 {\tt \$initstate
},
{\tt \$anyconst
},
{\tt \$anyseq
},
{\tt \$allconst
},
{\tt \$allseq
} cells.
573 Add information about
{\tt \$specify2
},
{\tt \$specify3
}, and
{\tt \$specrule
} cells.
577 Add information about
{\tt \$slice
} and
{\tt \$concat
} cells.
581 Add information about
{\tt \$lut
} and
{\tt \$sop
} cells.
585 Add information about
{\tt \$alu
},
{\tt \$macc
},
{\tt \$fa
}, and
{\tt \$lcu
} cells.
589 Add information about
{\tt \$ff
} and
{\tt \$
\_FF\_} cells.
593 Add information about
{\tt \$
\_DLATCH\_?
\_}, and
{\tt \$
\_DLATCHSR\_???
\_} cells.
597 Add information about
{\tt \$
\_AOI3\_},
{\tt \$
\_OAI3\_},
{\tt \$
\_AOI4\_},
{\tt \$
\_OAI4\_}, and
{\tt \$
\_NMUX\_} cells.