2 \chapter{Internal Cell Library
}
3 \label{chapter:celllib
}
5 Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
6 objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
9 This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
10 are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
11 cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
12 gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
13 from this category operate on single bit signals.
17 Most of the RTL cells closely resemble the operators available in HDLs such as
18 Verilog or VHDL. Therefore Verilog operators are used in the following sections
19 to define the behaviour of the RTL cells.
21 Note that all RTL cells have parameters indicating the size of inputs and outputs. When
22 passes modify RTL cells they must always keep the values of these parameters in sync with
23 the size of the signals connected to the inputs and outputs.
25 Simulation models for the RTL cells can be found in the file
{\tt techlibs/common/simlib.v
} in the Yosys
28 \subsection{Unary Operators
}
30 All unary RTL cells have one input port
\B{A
} and one output port
\B{Y
}. They also
31 have the following parameters:
34 \item \B{A
\_SIGNED} \\
35 Set to a non-zero value if the input
\B{A
} is signed and therefore should be sign-extended
39 The width of the input port
\B{A
}.
42 The width of the output port
\B{Y
}.
45 Table~
\ref{tab:CellLib_unary
} lists all cells for unary RTL operators.
50 Verilog & Cell Type \\
52 \lstinline[language=Verilog
]; Y = ~A ; &
{\tt \$not
} \\
53 \lstinline[language=Verilog
]; Y = +A ; &
{\tt \$pos
} \\
54 \lstinline[language=Verilog
]; Y = -A ; &
{\tt \$neg
} \\
56 \lstinline[language=Verilog
]; Y = &A ; &
{\tt \$reduce
\_and} \\
57 \lstinline[language=Verilog
]; Y = |A ; &
{\tt \$reduce
\_or} \\
58 \lstinline[language=Verilog
]; Y = ^A ; &
{\tt \$reduce
\_xor} \\
59 \lstinline[language=Verilog
]; Y = ~^A ; &
{\tt \$reduce
\_xnor} \\
61 \lstinline[language=Verilog
]; Y = |A ; &
{\tt \$reduce
\_bool} \\
62 \lstinline[language=Verilog
]; Y = !A ; &
{\tt \$logic
\_not}
64 \caption{Cell types for unary operators with their corresponding Verilog expressions.
}
65 \label{tab:CellLib_unary
}
68 Note that
{\tt \$reduce
\_or} and
{\tt \$reduce
\_bool} actually represent the same
69 logic function. But the HDL frontends generate them in different situations. A
70 {\tt \$reduce
\_or} cell is generated when the prefix
{\tt |
} operator is being used. A
71 {\tt \$reduce
\_bool} cell is generated when a bit vector is used as a condition in
72 an
{\tt if
}-statement or
{\tt ?:
}-expression.
74 \subsection{Binary Operators
}
76 All binary RTL cells have two input ports
\B{A
} and
\B{B
} and one output port
\B{Y
}. They
77 also have the following parameters:
80 \item \B{A
\_SIGNED} \\
81 Set to a non-zero value if the input
\B{A
} is signed and therefore should be sign-extended
85 The width of the input port
\B{A
}.
87 \item \B{B
\_SIGNED} \\
88 Set to a non-zero value if the input
\B{B
} is signed and therefore should be sign-extended
92 The width of the input port
\B{B
}.
95 The width of the output port
\B{Y
}.
98 Table~
\ref{tab:CellLib_binary
} lists all cells for binary RTL operators.
100 \subsection{Multiplexers
}
102 Multiplexers are generated by the Verilog HDL frontend for
{\tt
103 ?:
}-expressions. Multiplexers are also generated by the
{\tt proc
} pass to map the decision trees
104 from RTLIL::Process objects to logic.
106 The simplest multiplexer cell type is
{\tt \$mux
}. Cells of this type have a
\B{WIDTH
} parameter
107 and data inputs
\B{A
} and
\B{B
} and a data output
\B{Y
}, all of the specified width. This cell also
108 has a single bit control input
\B{S
}. If
\B{S
} is
0 the value from the
\B{A
} input is sent to
109 the output, if it is
1 the value from the
\B{B
} input is sent to the output. So the
{\tt \$mux
}
110 cell implements the function
\lstinline[language=Verilog
]; Y = S ? B : A;.
112 The
{\tt \$pmux
} cell is used to multiplex between many inputs using a one-hot select signal. Cells
113 of this type have a
\B{WIDTH
} and a
\B{S
\_WIDTH} parameter and inputs
\B{A
},
\B{B
}, and
\B{S
} and
114 an output
\B{Y
}. The
\B{S
} input is
\B{S
\_WIDTH} bits wide. The
\B{A
} input and the output are both
115 \B{WIDTH
} bits wide and the
\B{B
} input is
\B{WIDTH
}*
\B{S
\_WIDTH} bits wide. When all bits of
116 \B{S
} are zero, the value from
\B{A
} input is sent to the output. If the $n$'th bit from
\B{S
} is
117 set, the value $n$'th
\B{WIDTH
} bits wide slice of the
\B{B
} input is sent to the output. When more
118 than one bit from
\B{S
} is set the output is undefined. Cells of this type are used to model
119 ``parallel cases'' (defined by using the
{\tt parallel
\_case} attribute or detected by
122 The
{\tt \$tribuf
} cell is used to implement tristate logic. Cells of this type have a
\B{WIDTH
}
123 parameter and inputs
\B{A
} and
\B{EN
} and an output
\B{Y
}. The
\B{A
} input and
\B{Y
} output are
124 \B{WIDTH
} bits wide, and the
\B{EN
} input is one bit wide. When
\B{EN
} is
0, the output
\B{Y
}
125 is not driven. When
\B{EN
} is
1, the value from
\B{A
} input is sent to the
\B{Y
} output. Therefore,
126 the
{\tt \$tribuf
} cell implements the function
\lstinline[language=Verilog
]; Y = EN ? A : 'bz;.
128 Behavioural code with cascaded
{\tt if-then-else
}- and
{\tt case
}-statements
129 usually results in trees of multiplexer cells. Many passes (from various
130 optimizations to FSM extraction) heavily depend on these multiplexer trees to
131 understand dependencies between signals. Therefore optimizations should not
132 break these multiplexer trees (e.g.~by replacing a multiplexer between a
133 calculated signal and a constant zero with an
{\tt \$and
} gate).
137 \begin{tabular
}[t
]{ll
}
138 Verilog & Cell Type \\
140 \lstinline[language=Verilog
]; Y = A & B; &
{\tt \$and
} \\
141 \lstinline[language=Verilog
]; Y = A | B; &
{\tt \$or
} \\
142 \lstinline[language=Verilog
]; Y = A ^ B; &
{\tt \$xor
} \\
143 \lstinline[language=Verilog
]; Y = A ~^ B; &
{\tt \$xnor
} \\
145 \lstinline[language=Verilog
]; Y = A << B; &
{\tt \$shl
} \\
146 \lstinline[language=Verilog
]; Y = A >> B; &
{\tt \$shr
} \\
147 \lstinline[language=Verilog
]; Y = A <<< B; &
{\tt \$sshl
} \\
148 \lstinline[language=Verilog
]; Y = A >>> B; &
{\tt \$sshr
} \\
150 \lstinline[language=Verilog
]; Y = A && B; &
{\tt \$logic
\_and} \\
151 \lstinline[language=Verilog
]; Y = A || B; &
{\tt \$logic
\_or} \\
153 \lstinline[language=Verilog
]; Y = A === B; &
{\tt \$eqx
} \\
154 \lstinline[language=Verilog
]; Y = A !== B; &
{\tt \$nex
} \\
157 \begin{tabular
}[t
]{ll
}
158 Verilog & Cell Type \\
160 \lstinline[language=Verilog
]; Y = A < B; &
{\tt \$lt
} \\
161 \lstinline[language=Verilog
]; Y = A <= B; &
{\tt \$le
} \\
162 \lstinline[language=Verilog
]; Y = A == B; &
{\tt \$eq
} \\
163 \lstinline[language=Verilog
]; Y = A != B; &
{\tt \$ne
} \\
164 \lstinline[language=Verilog
]; Y = A >= B; &
{\tt \$ge
} \\
165 \lstinline[language=Verilog
]; Y = A > B; &
{\tt \$gt
} \\
167 \lstinline[language=Verilog
]; Y = A + B; &
{\tt \$add
} \\
168 \lstinline[language=Verilog
]; Y = A - B; &
{\tt \$sub
} \\
169 \lstinline[language=Verilog
]; Y = A * B; &
{\tt \$mul
} \\
170 \lstinline[language=Verilog
]; Y = A / B; &
{\tt \$div
} \\
171 \lstinline[language=Verilog
]; Y = A
% B; & {\tt \$mod} \\
172 \lstinline[language=Verilog
]; Y = A ** B; &
{\tt \$pow
} \\
174 \caption{Cell types for binary operators with their corresponding Verilog expressions.
}
175 \label{tab:CellLib_binary
}
178 \subsection{Registers
}
180 D-Type Flip-Flops are represented by
{\tt \$dff
} cells. These cells have a clock port
\B{CLK
},
181 an input port
\B{D
} and an output port
\B{Q
}. The following parameters are available for \$dff
186 The width of input
\B{D
} and output
\B{Q
}.
188 \item \B{CLK
\_POLARITY} \\
189 Clock is active on the positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
190 edge if this parameter is
{\tt 1'b0
}.
193 D-Type Flip-Flops with asynchronous resets are represented by
{\tt \$adff
} cells. As the
{\tt \$dff
}
194 cells they have
\B{CLK
},
\B{D
} and
\B{Q
} ports. In addition they also have a single-bit
\B{ARST
}
195 input port for the reset pin and the following additional two parameters:
198 \item \B{ARST
\_POLARITY} \\
199 The asynchronous reset is high-active if this parameter has the value
{\tt 1'b1
} and low-active
200 if this parameter is
{\tt 1'b0
}.
202 \item \B{ARST
\_VALUE} \\
203 The state of
\B{Q
} will be set to this value when the reset is active.
206 Note that the
{\tt \$adff
} cell can only be used when the reset value is constant.
209 Usually these cells are generated by the
{\tt proc
} pass using the information
210 in the designs RTLIL::Process objects.
214 Add information about
{\tt \$sr
} cells (set-reset flip-flops) and d-type latches.
217 \subsection{Memories
}
220 Memories are either represented using RTLIL::Memory objects,
{\tt \$memrd
},
{\tt \$memwr
}, and
{\tt \$meminit
}
221 cells, or by
{\tt \$mem
} cells alone.
223 In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
224 size in number of words, etc.) and for each port a
{\tt \$memrd
} (read port) or
{\tt \$memwr
} (write port)
225 cell is created. Having individual cells for read and write ports has the advantage that they can be
226 consolidated using resource sharing passes. In some cases this drastically reduces the number of required
227 ports on the memory cell. In this alternative, memory initialization data is represented by
{\tt \$meminit
} cells,
228 which allow delaying constant folding for initialization addresses and data until after the frontend finishes.
230 The
{\tt \$memrd
} cells have a clock input
\B{CLK
}, an enable input
\B{EN
}, an
231 address input
\B{ADDR
}, and a data output
\B{DATA
}. They also have the
232 following parameters:
236 The name of the RTLIL::Memory object that is associated with this read port.
239 The number of address bits (width of the
\B{ADDR
} input port).
242 The number of data bits (width of the
\B{DATA
} output port).
244 \item \B{CLK
\_ENABLE} \\
245 When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
246 the
\B{CLK
} input is not used.
248 \item \B{CLK
\_POLARITY} \\
249 Clock is active on the positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
250 edge if this parameter is
{\tt 1'b0
}.
252 \item \B{TRANSPARENT
} \\
253 If this parameter is set to
{\tt 1'b1
}, a read and write to the same address in the same cycle will
254 return the new value. Otherwise the old value is returned.
257 The
{\tt \$memwr
} cells have a clock input
\B{CLK
}, an enable input
\B{EN
} (one
258 enable bit for each data bit), an address input
\B{ADDR
} and a data input
259 \B{DATA
}. They also have the following parameters:
263 The name of the RTLIL::Memory object that is associated with this write port.
266 The number of address bits (width of the
\B{ADDR
} input port).
269 The number of data bits (width of the
\B{DATA
} output port).
271 \item \B{CLK
\_ENABLE} \\
272 When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
273 the
\B{CLK
} input is not used.
275 \item \B{CLK
\_POLARITY} \\
276 Clock is active on positive edge if this parameter has the value
{\tt 1'b1
} and on the negative
277 edge if this parameter is
{\tt 1'b0
}.
279 \item \B{PRIORITY
} \\
280 The cell with the higher integer value in this parameter wins a write conflict.
283 The
{\tt \$meminit
} cells have an address input
\B{ADDR
} and a data input
\B{DATA
}, with the width
284 of the
\B{DATA
} port equal to
\B{WIDTH
} parameter times
\B{WORDS
} parameter. Both of the inputs
285 must resolve to a constant for synthesis to succeed.
289 The name of the RTLIL::Memory object that is associated with this initialization cell.
292 The number of address bits (width of the
\B{ADDR
} input port).
295 The number of data bits per memory location.
298 The number of consecutive memory locations initialized by this cell.
300 \item \B{PRIORITY
} \\
301 The cell with the higher integer value in this parameter wins an initialization conflict.
304 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
305 {\tt \$memrd
} and
{\tt \$memwr
} cells. The
{\tt memory
} pass (i.e.~its various sub-passes) migrates
306 {\tt \$dff
} cells into the
{\tt \$memrd
} and
{\tt \$memwr
} cells making them synchronous, then
307 converts them to a single
{\tt \$mem
} cell and (optionally) maps this cell type
308 to
{\tt \$dff
} cells for the individual words and multiplexer-based address decoders for the read and
309 write interfaces. When the last step is disabled or not possible, a
{\tt \$mem
} cell is left in the design.
311 The
{\tt \$mem
} cell provides the following parameters:
315 The name of the original RTLIL::Memory object that became this
{\tt \$mem
} cell.
318 The number of words in the memory.
321 The number of address bits.
324 The number of data bits per word.
327 The initial memory contents.
329 \item \B{RD
\_PORTS} \\
330 The number of read ports on this memory cell.
332 \item \B{RD
\_CLK\_ENABLE} \\
333 This parameter is
\B{RD
\_PORTS} bits wide, containing a clock enable bit for each read port.
335 \item \B{RD
\_CLK\_POLARITY} \\
336 This parameter is
\B{RD
\_PORTS} bits wide, containing a clock polarity bit for each read port.
338 \item \B{RD
\_TRANSPARENT} \\
339 This parameter is
\B{RD
\_PORTS} bits wide, containing a transparent bit for each read port.
341 \item \B{WR
\_PORTS} \\
342 The number of write ports on this memory cell.
344 \item \B{WR
\_CLK\_ENABLE} \\
345 This parameter is
\B{WR
\_PORTS} bits wide, containing a clock enable bit for each write port.
347 \item \B{WR
\_CLK\_POLARITY} \\
348 This parameter is
\B{WR
\_PORTS} bits wide, containing a clock polarity bit for each write port.
351 The
{\tt \$mem
} cell has the following ports:
355 This input is
\B{RD
\_PORTS} bits wide, containing all clock signals for the read ports.
358 This input is
\B{RD
\_PORTS} bits wide, containing all enable signals for the read ports.
360 \item \B{RD
\_ADDR} \\
361 This input is
\B{RD
\_PORTS}*
\B{ABITS
} bits wide, containing all address signals for the read ports.
363 \item \B{RD
\_DATA} \\
364 This input is
\B{RD
\_PORTS}*
\B{WIDTH
} bits wide, containing all data signals for the read ports.
367 This input is
\B{WR
\_PORTS} bits wide, containing all clock signals for the write ports.
370 This input is
\B{WR
\_PORTS}*
\B{WIDTH
} bits wide, containing all enable signals for the write ports.
372 \item \B{WR
\_ADDR} \\
373 This input is
\B{WR
\_PORTS}*
\B{ABITS
} bits wide, containing all address signals for the write ports.
375 \item \B{WR
\_DATA} \\
376 This input is
\B{WR
\_PORTS}*
\B{WIDTH
} bits wide, containing all data signals for the write ports.
379 The
{\tt memory
\_collect} pass can be used to convert discrete
{\tt \$memrd
},
{\tt \$memwr
}, and
{\tt \$meminit
} cells
380 belonging to the same memory to a single
{\tt \$mem
} cell, whereas the
{\tt memory
\_unpack} pass performs the inverse operation.
381 The
{\tt memory
\_dff} pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
382 The
{\tt memory
\_bram} pass can be used to recognize
{\tt \$mem
} cells that can be implemented with a block RAM resource on an FPGA.
383 The
{\tt memory
\_map} pass can be used to implement
{\tt \$mem
} cells as basic logic: word-wide DFFs and address decoders.
385 \subsection{Finite State Machines
}
388 Add a brief description of the
{\tt \$fsm
} cell type.
392 \label{sec:celllib_gates
}
394 For gate level logic networks, fixed function single bit cells are used that do
395 not provide any parameters.
397 Simulation models for these cells can be found in the file
{\tt techlibs/common/simcells.v
} in the Yosys
402 \begin{tabular
}[t
]{ll
}
403 Verilog & Cell Type \\
405 \lstinline[language=Verilog
]; Y = ~A; &
{\tt \$
\_NOT\_} \\
406 \lstinline[language=Verilog
]; Y = A & B; &
{\tt \$
\_AND\_} \\
407 \lstinline[language=Verilog
]; Y = ~(A & B); &
{\tt \$
\_NAND\_} \\
408 \lstinline[language=Verilog
]; Y = A & ~B; &
{\tt \$
\_ANDNOT\_} \\
409 \lstinline[language=Verilog
]; Y = A | B; &
{\tt \$
\_OR\_} \\
410 \lstinline[language=Verilog
]; Y = ~(A | B); &
{\tt \$
\_NOR\_} \\
411 \lstinline[language=Verilog
]; Y = A | ~B; &
{\tt \$
\_ORNOT\_} \\
412 \lstinline[language=Verilog
]; Y = A ^ B; &
{\tt \$
\_XOR\_} \\
413 \lstinline[language=Verilog
]; Y = ~(A ^ B); &
{\tt \$
\_XNOR\_} \\
414 \lstinline[language=Verilog
]; Y = S ? B : A; &
{\tt \$
\_MUX\_} \\
415 \lstinline[language=Verilog
]; Y = EN ? A : 'bz; &
{\tt \$
\_TBUF\_} \\
417 \lstinline[language=Verilog
]; always @(negedge C) Q <= D; &
{\tt \$
\_DFF\_N\_} \\
418 \lstinline[language=Verilog
]; always @(posedge C) Q <= D; &
{\tt \$
\_DFF\_P\_} \\
421 \begin{tabular
}[t
]{llll
}
422 $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
424 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_NN0\_} \\
425 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_NN1\_} \\
426 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_NP0\_} \\
427 \lstinline[language=Verilog
];negedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_NP1\_} \\
428 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_PN0\_} \\
429 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
0; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_PN1\_} \\
430 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
0; &
{\tt \$
\_DFF\_PP0\_} \\
431 \lstinline[language=Verilog
];posedge; &
\lstinline[language=Verilog
];
1; &
\lstinline[language=Verilog
];
1; &
{\tt \$
\_DFF\_PP1\_} \\
433 \caption{Cell types for gate level logic networks
}
434 \label{tab:CellLib_gates
}
437 Table~
\ref{tab:CellLib_gates
} lists all cell types used for gate level logic. The cell types
438 {\tt \$
\_NOT\_},
{\tt \$
\_AND\_},
{\tt \$
\_NAND\_},
{\tt \$
\_ANDNOT\_},
{\tt \$
\_OR\_},
{\tt \$
\_NOR\_},
439 {\tt \$
\_ORNOT\_},
{\tt \$
\_XOR\_},
{\tt \$
\_XNOR\_} and
{\tt \$
\_MUX\_} are used to model combinatorial logic.
440 The cell type
{\tt \$
\_TBUF\_} is used to model tristate logic.
441 The cell types
{\tt \$
\_DFF\_N\_} and
{\tt \$
\_DFF\_P\_} represent d-type flip-flops.
443 The cell types
{\tt \$
\_DFF\_NN0\_},
{\tt \$
\_DFF\_NN1\_},
{\tt \$
\_DFF\_NP0\_},
{\tt \$
\_DFF\_NP1\_},
444 {\tt \$
\_DFF\_PN0\_},
{\tt \$
\_DFF\_PN1\_},
{\tt \$
\_DFF\_PP0\_} and
{\tt \$
\_DFF\_PP1\_} implement
445 d-type flip-flops with asynchronous resets. The values in the table for these cell types relate to the
446 following Verilog code template, where
\lstinline[mathescape,language=Verilog
];$RstEdge$; is
\lstinline[language=Verilog
];posedge;
447 if
\lstinline[mathescape,language=Verilog
];$RstLvl$; if
\lstinline[language=Verilog
];
1;, and
\lstinline[language=Verilog
];negedge;
450 \begin{lstlisting
}[mathescape,language=Verilog
]
451 always @($ClkEdge$ C, $RstEdge$ R)
458 In most cases gate level logic networks are created from RTL networks using the
{\tt techmap
} pass. The flip-flop cells
459 from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the
{\tt dfflibmap
}
460 pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC
\citeweblink{ABC
}
461 using the
{\tt abc
} pass.
464 Add information about
{\tt \$assert
},
{\tt \$assume
},
{\tt \$live
},
{\tt \$fair
},
{\tt \$cover
},
{\tt \$equiv
},
465 {\tt \$initstate
},
{\tt \$anyconst
},
{\tt \$anyseq
},
{\tt \$allconst
},
{\tt \$allseq
} cells.
469 Add information about
{\tt \$specify2
},
{\tt \$specify3
}, and
{\tt \$specrule
} cells.
473 Add information about
{\tt \$slice
} and
{\tt \$concat
} cells.
477 Add information about
{\tt \$lut
} and
{\tt \$sop
} cells.
481 Add information about
{\tt \$alu
},
{\tt \$macc
},
{\tt \$fa
}, and
{\tt \$lcu
} cells.
485 Add information about
{\tt \$ff
} and
{\tt \$
\_FF\_} cells.
489 Add information about
{\tt \$dffe
},
{\tt \$dffsr
},
{\tt \$dlatch
}, and
{\tt \$dlatchsr
} cells.
493 Add information about
{\tt \$
\_DFFE\_??
\_},
{\tt \$
\_DFFSR\_???
\_},
{\tt \$
\_DLATCH\_?
\_}, and
{\tt \$
\_DLATCHSR\_???
\_} cells.
497 Add information about
{\tt \$
\_AOI3\_},
{\tt \$
\_OAI3\_},
{\tt \$
\_AOI4\_},
{\tt \$
\_OAI4\_}, and
{\tt \$
\_NMUX\_} cells.