manual/CHAPTER_CellLib.tex

   1
   2 \chapter{Internal Cell Library}
   3 \label{chapter:celllib}
   4
   5 Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
   6 objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
   7 design internally.
   8
   9 This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
  10 are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
  11 cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
  12 gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
  13 from this category operate on single bit signals.
  14
  15 \section{RTL Cells}
  16
  17 Most of the RTL cells closely resemble the operators available in HDLs such as
  18 Verilog or VHDL. Therefore Verilog operators are used in the following sections
  19 to define the behaviour of the RTL cells.
  20
  21 Note that all RTL cells have parameters indicating the size of inputs and outputs. When
  22 passes modify RTL cells they must always keep the values of these parameters in sync with
  23 the size of the signals connected to the inputs and outputs.
  24
  25 Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys
  26 source tree.
  27
  28 \subsection{Unary Operators}
  29
  30 All unary RTL cells have one input port \B{A} and one output port \B{Y}. They also
  31 have the following parameters:
  32
  33 \begin{itemize}
  34 \item \B{A\_SIGNED} \\
  35 Set to a non-zero value if the input \B{A} is signed and therefore should be sign-extended
  36 when needed.
  37
  38 \item \B{A\_WIDTH} \\
  39 The width of the input port \B{A}.
  40
  41 \item \B{Y\_WIDTH} \\
  42 The width of the output port \B{Y}.
  43 \end{itemize}
  44
  45 Table~\ref{tab:CellLib_unary} lists all cells for unary RTL operators.
  46
  47 \begin{table}[t!]
  48 \hfil
  49 \begin{tabular}{ll}
  50 Verilog & Cell Type \\
  51 \hline
  52 \lstinline[language=Verilog]; Y =  ~A ; & {\tt \$not} \\
  53 \lstinline[language=Verilog]; Y =  +A ; & {\tt \$pos} \\
  54 \lstinline[language=Verilog]; Y =  -A ; & {\tt \$neg} \\
  55 \hline
  56 \lstinline[language=Verilog]; Y =  &A ; & {\tt \$reduce\_and} \\
  57 \lstinline[language=Verilog]; Y =  |A ; & {\tt \$reduce\_or} \\
  58 \lstinline[language=Verilog]; Y =  ^A ; & {\tt \$reduce\_xor} \\
  59 \lstinline[language=Verilog]; Y = ~^A ; & {\tt \$reduce\_xnor} \\
  60 \hline
  61 \lstinline[language=Verilog]; Y =  |A ; & {\tt \$reduce\_bool} \\
  62 \lstinline[language=Verilog]; Y =  !A ; & {\tt \$logic\_not}
  63 \end{tabular}
  64 \caption{Cell types for unary operators with their corresponding Verilog expressions.}
  65 \label{tab:CellLib_unary}
  66 \end{table}
  67
  68 For the unary cells that output a logical value ({\tt \$reduce\_and}, {\tt \$reduce\_or},
  69 {\tt \$reduce\_xor}, {\tt \$reduce\_xnor}, {\tt \$reduce\_bool}, {\tt \$logic\_not}),
  70 when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
  71 and only the least significant bit varies.
  72
  73 Note that {\tt \$reduce\_or} and {\tt \$reduce\_bool} actually represent the same
  74 logic function. But the HDL frontends generate them in different situations. A
  75 {\tt \$reduce\_or} cell is generated when the prefix {\tt |} operator is being used. A
  76 {\tt \$reduce\_bool} cell is generated when a bit vector is used as a condition in
  77 an {\tt if}-statement or {\tt ?:}-expression.
  78
  79 \subsection{Binary Operators}
  80
  81 All binary RTL cells have two input ports \B{A} and \B{B} and one output port \B{Y}. They
  82 also have the following parameters:
  83
  84 \begin{itemize}
  85 \item \B{A\_SIGNED} \\
  86 Set to a non-zero value if the input \B{A} is signed and therefore should be sign-extended
  87 when needed.
  88
  89 \item \B{A\_WIDTH} \\
  90 The width of the input port \B{A}.
  91
  92 \item \B{B\_SIGNED} \\
  93 Set to a non-zero value if the input \B{B} is signed and therefore should be sign-extended
  94 when needed.
  95
  96 \item \B{B\_WIDTH} \\
  97 The width of the input port \B{B}.
  98
  99 \item \B{Y\_WIDTH} \\
 100 The width of the output port \B{Y}.
 101 \end{itemize}
 102
 103 Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
 104
 105 \begin{table}[t!]
 106 \hfil
 107 \begin{tabular}[t]{ll}
 108 Verilog & Cell Type \\
 109 \hline
 110 \lstinline[language=Verilog]; Y = A  & B; & {\tt \$and} \\
 111 \lstinline[language=Verilog]; Y = A  | B; & {\tt \$or} \\
 112 \lstinline[language=Verilog]; Y = A  ^ B; & {\tt \$xor} \\
 113 \lstinline[language=Verilog]; Y = A ~^ B; & {\tt \$xnor} \\
 114 \hline
 115 \lstinline[language=Verilog]; Y = A << B; & {\tt \$shl} \\
 116 \lstinline[language=Verilog]; Y = A >> B; & {\tt \$shr} \\
 117 \lstinline[language=Verilog]; Y = A <<< B; & {\tt \$sshl} \\
 118 \lstinline[language=Verilog]; Y = A >>> B; & {\tt \$sshr} \\
 119 \hline
 120 \lstinline[language=Verilog]; Y = A && B; & {\tt \$logic\_and} \\
 121 \lstinline[language=Verilog]; Y = A || B; & {\tt \$logic\_or} \\
 122 \hline
 123 \lstinline[language=Verilog]; Y = A === B; & {\tt \$eqx} \\
 124 \lstinline[language=Verilog]; Y = A !== B; & {\tt \$nex} \\
 125 \end{tabular}
 126 \hfil
 127 \begin{tabular}[t]{ll}
 128 Verilog & Cell Type \\
 129 \hline
 130 \lstinline[language=Verilog]; Y = A <  B; & {\tt \$lt} \\
 131 \lstinline[language=Verilog]; Y = A <= B; & {\tt \$le} \\
 132 \lstinline[language=Verilog]; Y = A == B; & {\tt \$eq} \\
 133 \lstinline[language=Verilog]; Y = A != B; & {\tt \$ne} \\
 134 \lstinline[language=Verilog]; Y = A >= B; & {\tt \$ge} \\
 135 \lstinline[language=Verilog]; Y = A >  B; & {\tt \$gt} \\
 136 \hline
 137 \lstinline[language=Verilog]; Y = A  + B; & {\tt \$add} \\
 138 \lstinline[language=Verilog]; Y = A  - B; & {\tt \$sub} \\
 139 \lstinline[language=Verilog]; Y = A  * B; & {\tt \$mul} \\
 140 \lstinline[language=Verilog]; Y = A  / B; & {\tt \$div} \\
 141 \lstinline[language=Verilog]; Y = A  % B; & {\tt \$mod} \\
 142 \multicolumn{1}{c}{\tt [N/A]} & {\tt \$divfloor} \\
 143 \multicolumn{1}{c}{\tt [N/A]} & {\tt \$modfoor} \\
 144 \lstinline[language=Verilog]; Y = A ** B; & {\tt \$pow} \\
 145 \end{tabular}
 146 \caption{Cell types for binary operators with their corresponding Verilog expressions.}
 147 \label{tab:CellLib_binary}
 148 \end{table}
 149
 150 The {\tt \$shl} and {\tt \$shr} cells implement logical shifts, whereas the {\tt \$sshl} and
 151 {\tt \$sshr} cells implement arithmetic shifts. The {\tt \$shl} and {\tt \$sshl} cells implement
 152 the same operation. All four of these cells interpret the second operand as unsigned, and require
 153 \B{B\_SIGNED} to be zero.
 154
 155 Two additional shift operator cells are available that do not directly correspond to any operator
 156 in Verilog, {\tt \$shift} and {\tt \$shiftx}. The {\tt \$shift} cell performs a right logical shift
 157 if the second operand is positive (or unsigned), and a left logical shift if it is negative.
 158 The {\tt \$shiftx} cell performs the same operation as the {\tt \$shift} cell, but the vacated bit
 159 positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.
 160
 161 For the binary cells that output a logical value ({\tt \$logic\_and}, {\tt \$logic\_or},
 162 {\tt \$eqx}, {\tt \$nex}, {\tt \$lt}, {\tt \$le}, {\tt \$eq}, {\tt \$ne}, {\tt \$ge},
 163 {\tt \$gt}), when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
 164 and only the least significant bit varies.
 165
 166 Division and modulo cells are available in two rounding modes. The original {\tt \$div} and {\tt \$mod}
 167 cells are based on truncating division, and correspond to the semantics of the verilog {\tt /} and
 168 {\tt \%} operators. The {\tt \$divfloor} and {\tt \$modfloor} cells represent flooring division and
 169 flooring modulo, the latter of which is also known as ``remainder'' in several languages. See
 170 table~\ref{tab:CellLib_divmod} for a side-by-side comparison between the different semantics.
 171
 172 \begin{table}[h]
 173 \hfil
 174 \begin{tabular}{lr|rr|rr}
 175 \multirow{2}{*}{Division} & \multirow{2}{*}{Result} & \multicolumn{2}{c|}{Truncating} & \multicolumn{2}{c}{Flooring} \\
 176                &            & {\tt \$div} & {\tt \$mod} & {\tt \$divfloor} & {\tt \$modfloor} \\
 177 \hline
 178 {\tt -10 / 3}  & {\tt -3.3} & {\tt -3}    & {\tt -1}    & {\tt -4}         & {\tt 2} \\
 179 {\tt 10 / -3}  & {\tt -3.3} & {\tt -3}    & {\tt 1}     & {\tt -4}         & {\tt -2} \\
 180 {\tt -10 / -3} & {\tt 3.3}  & {\tt 3}     & {\tt -1}    & {\tt 3}          & {\tt -1} \\
 181 {\tt 10 / 3}   & {\tt 3.3}  & {\tt 3}     & {\tt 1}     & {\tt 3}          & {\tt 1} \\
 182 \end{tabular}
 183 \caption{Comparison between different rounding modes for division and modulo cells.}
 184 \label{tab:CellLib_divmod}
 185 \end{table}
 186
 187 \subsection{Multiplexers}
 188
 189 Multiplexers are generated by the Verilog HDL frontend for {\tt
 190 ?:}-expressions. Multiplexers are also generated by the {\tt proc} pass to map the decision trees
 191 from RTLIL::Process objects to logic.
 192
 193 The simplest multiplexer cell type is {\tt \$mux}. Cells of this type have a \B{WIDTH} parameter
 194 and data inputs \B{A} and \B{B} and a data output \B{Y}, all of the specified width. This cell also
 195 has a single bit control input \B{S}. If \B{S} is 0 the value from the \B{A} input is sent to
 196 the output, if it is 1 the value from the \B{B} input is sent to the output. So the {\tt \$mux}
 197 cell implements the function \lstinline[language=Verilog]; Y = S ? B : A;.
 198
 199 The {\tt \$pmux} cell is used to multiplex between many inputs using a one-hot select signal. Cells
 200 of this type have a \B{WIDTH} and a \B{S\_WIDTH} parameter and inputs \B{A}, \B{B}, and \B{S} and
 201 an output \B{Y}. The \B{S} input is \B{S\_WIDTH} bits wide. The \B{A} input and the output are both
 202 \B{WIDTH} bits wide and the \B{B} input is \B{WIDTH}*\B{S\_WIDTH} bits wide. When all bits of
 203 \B{S} are zero, the value from \B{A} input is sent to the output. If the $n$'th bit from \B{S} is
 204 set, the value $n$'th \B{WIDTH} bits wide slice of the \B{B} input is sent to the output. When more
 205 than one bit from \B{S} is set the output is undefined. Cells of this type are used to model
 206 ``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by
 207 an optimization).
 208
 209 The {\tt \$tribuf} cell is used to implement tristate logic. Cells of this type have a \B{WIDTH}
 210 parameter and inputs \B{A} and \B{EN} and an output \B{Y}. The \B{A} input and \B{Y} output are
 211 \B{WIDTH} bits wide, and the \B{EN} input is one bit wide. When \B{EN} is 0, the output \B{Y}
 212 is not driven. When \B{EN} is 1, the value from \B{A} input is sent to the \B{Y} output. Therefore,
 213 the {\tt \$tribuf} cell implements the function \lstinline[language=Verilog]; Y = EN ? A : 'bz;.
 214
 215 Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements
 216 usually results in trees of multiplexer cells. Many passes (from various
 217 optimizations to FSM extraction) heavily depend on these multiplexer trees to
 218 understand dependencies between signals. Therefore optimizations should not
 219 break these multiplexer trees (e.g.~by replacing a multiplexer between a
 220 calculated signal and a constant zero with an {\tt \$and} gate).
 221
 222 \subsection{Registers}
 223
 224 SR-type latches are represented by {\tt \$sr} cells.  These cells have input ports
 225 \B{SET} and \B{CLR} and an output port \B{Q}.  They have the following parameters:
 226
 227 \begin{itemize}
 228 \item \B{WIDTH} \\
 229 The width of inputs \B{SET} and \B{CLR} and output \B{Q}.
 230
 231 \item \B{SET\_POLARITY} \\
 232 The set input bits are active-high if this parameter has the value {\tt 1'b1} and active-low
 233 if this parameter is {\tt 1'b0}.
 234
 235 \item \B{CLR\_POLARITY} \\
 236 The reset input bits are active-high if this parameter has the value {\tt 1'b1} and active-low
 237 if this parameter is {\tt 1'b0}.
 238 \end{itemize}
 239
 240 Both set and reset inputs have separate bits for every output bit.
 241 When both the set and reset inputs of an {\tt \$sr} cell are active for a given bit
 242 index, the reset input takes precedence.
 243
 244 D-type flip-flops are represented by {\tt \$dff} cells. These cells have a clock port \B{CLK},
 245 an input port \B{D} and an output port \B{Q}. The following parameters are available for {\tt \$dff}
 246 cells:
 247
 248 \begin{itemize}
 249 \item \B{WIDTH} \\
 250 The width of input \B{D} and output \B{Q}.
 251
 252 \item \B{CLK\_POLARITY} \\
 253 Clock is active on the positive edge if this parameter has the value {\tt 1'b1} and on the negative
 254 edge if this parameter is {\tt 1'b0}.
 255 \end{itemize}
 256
 257 D-type flip-flops with asynchronous reset are represented by {\tt \$adff} cells. As the {\tt \$dff}
 258 cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{ARST}
 259 input port for the reset pin and the following additional two parameters:
 260
 261 \begin{itemize}
 262 \item \B{ARST\_POLARITY} \\
 263 The asynchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
 264 if this parameter is {\tt 1'b0}.
 265
 266 \item \B{ARST\_VALUE} \\
 267 The state of \B{Q} will be set to this value when the reset is active.
 268 \end{itemize}
 269
 270 \begin{sloppypar}
 271 Usually these cells are generated by the {\tt proc} pass using the information
 272 in the designs RTLIL::Process objects.
 273 \end{sloppypar}
 274
 275 D-type flip-flops with synchronous reset are represented by {\tt \$sdff} cells. As the {\tt \$dff}
 276 cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{SRST}
 277 input port for the reset pin and the following additional two parameters:
 278
 279 \begin{itemize}
 280 \item \B{SRST\_POLARITY} \\
 281 The synchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
 282 if this parameter is {\tt 1'b0}.
 283
 284 \item \B{SRST\_VALUE} \\
 285 The state of \B{Q} will be set to this value when the reset is active.
 286 \end{itemize}
 287
 288 Note that the {\tt \$adff} and {\tt \$sdff} cells can only be used when the reset value is constant.
 289
 290 D-type flip-flops with asynchronous set and reset are represented by {\tt \$dffsr} cells.
 291 As the {\tt \$dff} cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have
 292 multi-bit \B{SET} and \B{CLR} input ports and the corresponding polarity parameters, like
 293 {\tt \$sr} cells.
 294
 295 D-type flip-flops with enable are represented by {\tt \$dffe}, {\tt \$adffe}, {\tt \$dffsre},
 296 {\tt \$sdffe}, and {\tt \$sdffce} cells, which are enhanced variants of {\tt \$dff}, {\tt \$adff}, {\tt \$dffsr},
 297 {\tt \$sdff} (with reset over enable) and {\tt \$sdff} (with enable over reset)
 298 cells, respectively.  They have the same ports and parameters as their base cell.
 299 In addition they also have a single-bit \B{EN} input port for the enable pin and the following parameter:
 300
 301 \begin{itemize}
 302 \item \B{EN\_POLARITY} \\
 303 The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
 304 if this parameter is {\tt 1'b0}.
 305 \end{itemize}
 306
 307 D-type latches are represented by {\tt \$dlatch} cells.  These cells have an enable port \B{EN},
 308 an input port \B{D}, and an output port \B{Q}.  The following parameters are available for {\tt \$dlatch} cells:
 309
 310 \begin{itemize}
 311 \item \B{WIDTH} \\
 312 The width of input \B{D} and output \B{Q}.
 313
 314 \item \B{EN\_POLARITY} \\
 315 The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
 316 if this parameter is {\tt 1'b0}.
 317 \end{itemize}
 318
 319 The latch is transparent when the \B{EN} input is active.
 320
 321 D-type latches with reset are represented by {\tt \$adlatch} cells.  In addition to {\tt \$dlatch}
 322 ports and parameters, they also have a single-bit \B{ARST} input port for the reset pin and the following additional parameters:
 323
 324 \begin{itemize}
 325 \item \B{ARST\_POLARITY} \\
 326 The asynchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
 327 if this parameter is {\tt 1'b0}.
 328
 329 \item \B{ARST\_VALUE} \\
 330 The state of \B{Q} will be set to this value when the reset is active.
 331 \end{itemize}
 332
 333 D-type latches with set and reset are represented by {\tt \$dlatchsr} cells.
 334 In addition to {\tt \$dlatch} ports and parameters, they also have multi-bit
 335 \B{SET} and \B{CLR} input ports and the corresponding polarity parameters, like
 336 {\tt \$sr} cells.
 337
 338 \subsection{Memories}
 339 \label{sec:memcells}
 340
 341 Memories are either represented using RTLIL::Memory objects, {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit}
 342 cells, or by {\tt \$mem} cells alone.
 343
 344 In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
 345 size in number of words, etc.) and for each port a {\tt \$memrd} (read port) or {\tt \$memwr} (write port)
 346 cell is created. Having individual cells for read and write ports has the advantage that they can be
 347 consolidated using resource sharing passes. In some cases this drastically reduces the number of required
 348 ports on the memory cell. In this alternative, memory initialization data is represented by {\tt \$meminit} cells,
 349 which allow delaying constant folding for initialization addresses and data until after the frontend finishes.
 350
 351 The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an
 352 address input \B{ADDR}, and a data output \B{DATA}. They also have the
 353 following parameters:
 354
 355 \begin{itemize}
 356 \item \B{MEMID} \\
 357 The name of the RTLIL::Memory object that is associated with this read port.
 358
 359 \item \B{ABITS} \\
 360 The number of address bits (width of the \B{ADDR} input port).
 361
 362 \item \B{WIDTH} \\
 363 The number of data bits (width of the \B{DATA} output port).
 364
 365 \item \B{CLK\_ENABLE} \\
 366 When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
 367 the \B{CLK} input is not used.
 368
 369 \item \B{CLK\_POLARITY} \\
 370 Clock is active on the positive edge if this parameter has the value {\tt 1'b1} and on the negative
 371 edge if this parameter is {\tt 1'b0}.
 372
 373 \item \B{TRANSPARENT} \\
 374 If this parameter is set to {\tt 1'b1}, a read and write to the same address in the same cycle will
 375 return the new value. Otherwise the old value is returned.
 376 \end{itemize}
 377
 378 The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
 379 enable bit for each data bit), an address input \B{ADDR} and a data input
 380 \B{DATA}. They also have the following parameters:
 381
 382 \begin{itemize}
 383 \item \B{MEMID} \\
 384 The name of the RTLIL::Memory object that is associated with this write port.
 385
 386 \item \B{ABITS} \\
 387 The number of address bits (width of the \B{ADDR} input port).
 388
 389 \item \B{WIDTH} \\
 390 The number of data bits (width of the \B{DATA} output port).
 391
 392 \item \B{CLK\_ENABLE} \\
 393 When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
 394 the \B{CLK} input is not used.
 395
 396 \item \B{CLK\_POLARITY} \\
 397 Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative
 398 edge if this parameter is {\tt 1'b0}.
 399
 400 \item \B{PRIORITY} \\
 401 The cell with the higher integer value in this parameter wins a write conflict.
 402 \end{itemize}
 403
 404 The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}, with the width
 405 of the \B{DATA} port equal to \B{WIDTH} parameter times \B{WORDS} parameter. Both of the inputs
 406 must resolve to a constant for synthesis to succeed.
 407
 408 \begin{itemize}
 409 \item \B{MEMID} \\
 410 The name of the RTLIL::Memory object that is associated with this initialization cell.
 411
 412 \item \B{ABITS} \\
 413 The number of address bits (width of the \B{ADDR} input port).
 414
 415 \item \B{WIDTH} \\
 416 The number of data bits per memory location.
 417
 418 \item \B{WORDS} \\
 419 The number of consecutive memory locations initialized by this cell.
 420
 421 \item \B{PRIORITY} \\
 422 The cell with the higher integer value in this parameter wins an initialization conflict.
 423 \end{itemize}
 424
 425 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
 426 {\tt \$memrd} and {\tt \$memwr} cells. The {\tt memory} pass (i.e.~its various sub-passes) migrates
 427 {\tt \$dff} cells into the {\tt \$memrd} and {\tt \$memwr} cells making them synchronous, then
 428 converts them to a single {\tt \$mem} cell and (optionally) maps this cell type
 429 to {\tt \$dff} cells for the individual words and multiplexer-based address decoders for the read and
 430 write interfaces. When the last step is disabled or not possible, a {\tt \$mem} cell is left in the design.
 431
 432 The {\tt \$mem} cell provides the following parameters:
 433
 434 \begin{itemize}
 435 \item \B{MEMID} \\
 436 The name of the original RTLIL::Memory object that became this {\tt \$mem} cell.
 437
 438 \item \B{SIZE} \\
 439 The number of words in the memory.
 440
 441 \item \B{ABITS} \\
 442 The number of address bits.
 443
 444 \item \B{WIDTH} \\
 445 The number of data bits per word.
 446
 447 \item \B{INIT} \\
 448 The initial memory contents.
 449
 450 \item \B{RD\_PORTS} \\
 451 The number of read ports on this memory cell.
 452
 453 \item \B{RD\_CLK\_ENABLE} \\
 454 This parameter is \B{RD\_PORTS} bits wide, containing a clock enable bit for each read port.
 455
 456 \item \B{RD\_CLK\_POLARITY} \\
 457 This parameter is \B{RD\_PORTS} bits wide, containing a clock polarity bit for each read port.
 458
 459 \item \B{RD\_TRANSPARENT} \\
 460 This parameter is \B{RD\_PORTS} bits wide, containing a transparent bit for each read port.
 461
 462 \item \B{WR\_PORTS} \\
 463 The number of write ports on this memory cell.
 464
 465 \item \B{WR\_CLK\_ENABLE} \\
 466 This parameter is \B{WR\_PORTS} bits wide, containing a clock enable bit for each write port.
 467
 468 \item \B{WR\_CLK\_POLARITY} \\
 469 This parameter is \B{WR\_PORTS} bits wide, containing a clock polarity bit for each write port.
 470 \end{itemize}
 471
 472 The {\tt \$mem} cell has the following ports:
 473
 474 \begin{itemize}
 475 \item \B{RD\_CLK} \\
 476 This input is \B{RD\_PORTS} bits wide, containing all clock signals for the read ports.
 477
 478 \item \B{RD\_EN} \\
 479 This input is \B{RD\_PORTS} bits wide, containing all enable signals for the read ports.
 480
 481 \item \B{RD\_ADDR} \\
 482 This input is \B{RD\_PORTS}*\B{ABITS} bits wide, containing all address signals for the read ports.
 483
 484 \item \B{RD\_DATA} \\
 485 This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for the read ports.
 486
 487 \item \B{WR\_CLK} \\
 488 This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
 489
 490 \item \B{WR\_EN} \\
 491 This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
 492
 493 \item \B{WR\_ADDR} \\
 494 This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.
 495
 496 \item \B{WR\_DATA} \\
 497 This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all data signals for the write ports.
 498 \end{itemize}
 499
 500 The {\tt memory\_collect} pass can be used to convert discrete {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit} cells
 501 belonging to the same memory to a single {\tt \$mem} cell, whereas the {\tt memory\_unpack} pass performs the inverse operation.
 502 The {\tt memory\_dff} pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
 503 The {\tt memory\_bram} pass can be used to recognize {\tt \$mem} cells that can be implemented with a block RAM resource on an FPGA.
 504 The {\tt memory\_map} pass can be used to implement {\tt \$mem} cells as basic logic: word-wide DFFs and address decoders.
 505
 506 \subsection{Finite State Machines}
 507
 508 \begin{fixme}
 509 Add a brief description of the {\tt \$fsm} cell type.
 510 \end{fixme}
 511
 512 \subsection{Specify rules}
 513
 514 \begin{fixme}
 515 Add information about {\tt \$specify2}, {\tt \$specify3}, and {\tt \$specrule} cells.
 516 \end{fixme}
 517
 518 \subsection{Formal verification cells}
 519
 520 \begin{fixme}
 521 Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv},
 522 {\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells.
 523 \end{fixme}
 524
 525 \begin{fixme}
 526 Add information about {\tt \$ff} and {\tt \$\_FF\_} cells.
 527 \end{fixme}
 528
 529 \section{Gates}
 530 \label{sec:celllib_gates}
 531
 532 For gate level logic networks, fixed function single bit cells are used that do
 533 not provide any parameters.
 534
 535 Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
 536 source tree.
 537
 538 \begin{table}[t]
 539 \hfil
 540 \begin{tabular}[t]{ll}
 541 Verilog & Cell Type \\
 542 \hline
 543 \lstinline[language=Verilog]; Y = A;     & {\tt \$\_BUF\_} \\
 544 \lstinline[language=Verilog]; Y = ~A;    & {\tt \$\_NOT\_} \\
 545 \lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
 546 \lstinline[language=Verilog]; Y = ~(A & B); & {\tt \$\_NAND\_} \\
 547 \lstinline[language=Verilog]; Y = A & ~B; & {\tt \$\_ANDNOT\_} \\
 548 \lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\
 549 \lstinline[language=Verilog]; Y = ~(A | B); & {\tt \$\_NOR\_} \\
 550 \lstinline[language=Verilog]; Y = A | ~B; & {\tt \$\_ORNOT\_} \\
 551 \lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
 552 \lstinline[language=Verilog]; Y = ~(A ^ B); & {\tt \$\_XNOR\_} \\
 553 \lstinline[language=Verilog]; Y = ~((A & B) | C); & {\tt \$\_AOI3\_} \\
 554 \lstinline[language=Verilog]; Y = ~((A | B) & C); & {\tt \$\_OAI3\_} \\
 555 \lstinline[language=Verilog]; Y = ~((A & B) | (C & D)); & {\tt \$\_AOI4\_} \\
 556 \lstinline[language=Verilog]; Y = ~((A | B) & (C | D)); & {\tt \$\_OAI4\_} \\
 557 \lstinline[language=Verilog]; Y = S ? B : A; & {\tt \$\_MUX\_} \\
 558 \lstinline[language=Verilog]; Y = ~(S ? B : A); & {\tt \$\_NMUX\_} \\
 559 (see below) & {\tt \$\_MUX4\_} \\
 560 (see below) & {\tt \$\_MUX8\_} \\
 561 (see below) & {\tt \$\_MUX16\_} \\
 562 \lstinline[language=Verilog]; Y = EN ? A : 1'bz; & {\tt \$\_TBUF\_} \\
 563 \hline
 564 \lstinline[language=Verilog]; always @(negedge C) Q <= D; & {\tt \$\_DFF\_N\_} \\
 565 \lstinline[language=Verilog]; always @(posedge C) Q <= D; & {\tt \$\_DFF\_P\_} \\
 566 \lstinline[language=Verilog]; always @* if (!E) Q <= D; & {\tt \$\_DLATCH\_N\_} \\
 567 \lstinline[language=Verilog]; always @* if (E)  Q <= D; & {\tt \$\_DLATCH\_P\_} \\
 568 \end{tabular}
 569 \caption{Cell types for gate level logic networks (main list)}
 570 \label{tab:CellLib_gates}
 571 \end{table}
 572
 573 \begin{table}[t]
 574 \hfil
 575 \begin{tabular}[t]{llll}
 576 $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
 577 \hline
 578 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NN0\_}, {\tt \$\_SDFF\_NN0\_} \\
 579 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NN1\_}, {\tt \$\_SDFF\_NN1\_} \\
 580 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NP0\_}, {\tt \$\_SDFF\_NP0\_} \\
 581 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NP1\_}, {\tt \$\_SDFF\_NP1\_} \\
 582 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PN0\_}, {\tt \$\_SDFF\_PN0\_} \\
 583 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PN1\_}, {\tt \$\_SDFF\_PN1\_} \\
 584 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PP0\_}, {\tt \$\_SDFF\_PP0\_} \\
 585 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PP1\_}, {\tt \$\_SDFF\_PP1\_} \\
 586 \end{tabular}
 587 \caption{Cell types for gate level logic networks (FFs with reset)}
 588 \label{tab:CellLib_gates_adff}
 589 \end{table}
 590
 591 \begin{table}[t]
 592 \hfil
 593 \begin{tabular}[t]{lll}
 594 $ClkEdge$ & $EnLvl$ & Cell Type \\
 595 \hline
 596 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN\_} \\
 597 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP\_} \\
 598 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN\_} \\
 599 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP\_} \\
 600 \end{tabular}
 601 \caption{Cell types for gate level logic networks (FFs with enable)}
 602 \label{tab:CellLib_gates_dffe}
 603 \end{table}
 604
 605 \begin{table}[t]
 606 \begin{tabular}[t]{lllll}
 607 $ClkEdge$ & $RstLvl$ & $RstVal$ & $EnLvl$ & Cell Type \\
 608 \hline
 609 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN0N\_}, {\tt \$\_SDFFE\_NN0N\_}, {\tt \$\_SDFFCE\_NN0N\_} \\
 610 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NN0P\_}, {\tt \$\_SDFFE\_NN0P\_}, {\tt \$\_SDFFCE\_NN0P\_} \\
 611 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN1N\_}, {\tt \$\_SDFFE\_NN1N\_}, {\tt \$\_SDFFCE\_NN1N\_} \\
 612 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NN1P\_}, {\tt \$\_SDFFE\_NN1P\_}, {\tt \$\_SDFFCE\_NN1P\_} \\
 613 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NP0N\_}, {\tt \$\_SDFFE\_NP0N\_}, {\tt \$\_SDFFCE\_NP0N\_} \\
 614 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP0P\_}, {\tt \$\_SDFFE\_NP0P\_}, {\tt \$\_SDFFCE\_NP0P\_} \\
 615 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NP1N\_}, {\tt \$\_SDFFE\_NP1N\_}, {\tt \$\_SDFFCE\_NP1N\_} \\
 616 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP1P\_}, {\tt \$\_SDFFE\_NP1P\_}, {\tt \$\_SDFFCE\_NP1P\_} \\
 617 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN0N\_}, {\tt \$\_SDFFE\_PN0N\_}, {\tt \$\_SDFFCE\_PN0N\_} \\
 618 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PN0P\_}, {\tt \$\_SDFFE\_PN0P\_}, {\tt \$\_SDFFCE\_PN0P\_} \\
 619 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN1N\_}, {\tt \$\_SDFFE\_PN1N\_}, {\tt \$\_SDFFCE\_PN1N\_} \\
 620 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PN1P\_}, {\tt \$\_SDFFE\_PN1P\_}, {\tt \$\_SDFFCE\_PN1P\_} \\
 621 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PP0N\_}, {\tt \$\_SDFFE\_PP0N\_}, {\tt \$\_SDFFCE\_PP0N\_} \\
 622 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP0P\_}, {\tt \$\_SDFFE\_PP0P\_}, {\tt \$\_SDFFCE\_PP0P\_} \\
 623 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PP1N\_}, {\tt \$\_SDFFE\_PP1N\_}, {\tt \$\_SDFFCE\_PP1N\_} \\
 624 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP1P\_}, {\tt \$\_SDFFE\_PP1P\_}, {\tt \$\_SDFFCE\_PP1P\_} \\
 625 \end{tabular}
 626 \caption{Cell types for gate level logic networks (FFs with reset and enable)}
 627 \label{tab:CellLib_gates_adffe}
 628 \end{table}
 629
 630 \begin{table}[t]
 631 \hfil
 632 \begin{tabular}[t]{llll}
 633 $ClkEdge$ & $SetLvl$ & $RstLvl$ & Cell Type \\
 634 \hline
 635 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_NNN\_} \\
 636 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_NNP\_} \\
 637 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_NPN\_} \\
 638 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_NPP\_} \\
 639 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_PNN\_} \\
 640 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_PNP\_} \\
 641 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_PPN\_} \\
 642 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_PPP\_} \\
 643 \end{tabular}
 644 \caption{Cell types for gate level logic networks (FFs with set and reset)}
 645 \label{tab:CellLib_gates_dffsr}
 646 \end{table}
 647
 648 \begin{table}[t]
 649 \hfil
 650 \begin{tabular}[t]{lllll}
 651 $ClkEdge$ & $SetLvl$ & $RstLvl$ & $EnLvl$ & Cell Type \\
 652 \hline
 653 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NNNN\_} \\
 654 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NNNP\_} \\
 655 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NNPN\_} \\
 656 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NNPP\_} \\
 657 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NPNN\_} \\
 658 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NPNP\_} \\
 659 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NPPN\_} \\
 660 \lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NPPP\_} \\
 661 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PNNN\_} \\
 662 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PNNP\_} \\
 663 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PNPN\_} \\
 664 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PNPP\_} \\
 665 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PPNN\_} \\
 666 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PPNP\_} \\
 667 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PPPN\_} \\
 668 \lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PPPP\_} \\
 669 \end{tabular}
 670 \caption{Cell types for gate level logic networks (FFs with set and reset and enable)}
 671 \label{tab:CellLib_gates_dffsre}
 672 \end{table}
 673
 674 \begin{table}[t]
 675 \hfil
 676 \begin{tabular}[t]{llll}
 677 $EnLvl$ & $RstLvl$ & $RstVal$ & Cell Type \\
 678 \hline
 679 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_NN0\_} \\
 680 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_NN1\_} \\
 681 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_NP0\_} \\
 682 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_NP1\_} \\
 683 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_PN0\_} \\
 684 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_PN1\_} \\
 685 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_PP0\_} \\
 686 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_PP1\_} \\
 687 \end{tabular}
 688 \caption{Cell types for gate level logic networks (latches with reset)}
 689 \label{tab:CellLib_gates_adlatch}
 690 \end{table}
 691
 692 \begin{table}[t]
 693 \hfil
 694 \begin{tabular}[t]{llll}
 695 $EnLvl$ & $SetLvl$ & $RstLvl$ & Cell Type \\
 696 \hline
 697 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_NNN\_} \\
 698 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_NNP\_} \\
 699 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_NPN\_} \\
 700 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_NPP\_} \\
 701 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_PNN\_} \\
 702 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_PNP\_} \\
 703 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_PPN\_} \\
 704 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_PPP\_} \\
 705 \end{tabular}
 706 \caption{Cell types for gate level logic networks (latches with set and reset)}
 707 \label{tab:CellLib_gates_dlatchsr}
 708 \end{table}
 709
 710 \begin{table}[t]
 711 \hfil
 712 \begin{tabular}[t]{llll}
 713 $SetLvl$ & $RstLvl$ & Cell Type \\
 714 \hline
 715 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_SR\_NN\_} \\
 716 \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_SR\_NP\_} \\
 717 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_SR\_PN\_} \\
 718 \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_SR\_PP\_} \\
 719 \end{tabular}
 720 \caption{Cell types for gate level logic networks (SR latches)}
 721 \label{tab:CellLib_gates_sr}
 722 \end{table}
 723
 724 Tables~\ref{tab:CellLib_gates}, \ref{tab:CellLib_gates_dffe}, \ref{tab:CellLib_gates_adff}, \ref{tab:CellLib_gates_adffe}, \ref{tab:CellLib_gates_dffsr}, \ref{tab:CellLib_gates_dffsre}, \ref{tab:CellLib_gates_adlatch}, \ref{tab:CellLib_gates_dlatchsr} and \ref{tab:CellLib_gates_sr} list all cell types used for gate level logic. The cell types
 725 {\tt \$\_BUF\_}, {\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_NAND\_}, {\tt \$\_ANDNOT\_},
 726 {\tt \$\_OR\_}, {\tt \$\_NOR\_}, {\tt \$\_ORNOT\_}, {\tt \$\_XOR\_}, {\tt \$\_XNOR\_},
 727 {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, {\tt \$\_OAI4\_},
 728 {\tt \$\_MUX\_}, {\tt \$\_MUX4\_}, {\tt \$\_MUX8\_}, {\tt \$\_MUX16\_} and {\tt \$\_NMUX\_} are used to model combinatorial logic.
 729 The cell type {\tt \$\_TBUF\_} is used to model tristate logic.
 730
 731 The {\tt \$\_MUX4\_}, {\tt \$\_MUX8\_} and {\tt \$\_MUX16\_} cells are used to model wide muxes, and correspond to the following Verilog code:
 732
 733 \begin{lstlisting}[language=Verilog]
 734 // $_MUX4_
 735 assign Y = T ? (S ? D : C) :
 736                (S ? B : A);
 737 // $_MUX8_
 738 assign Y = U ? T ? (S ? H : G) :
 739                    (S ? F : E) :
 740                T ? (S ? D : C) :
 741                    (S ? B : A);
 742 // $_MUX16_
 743 assign Y = V ? U ? T ? (S ? P : O) :
 744                        (S ? N : M) :
 745                    T ? (S ? L : K) :
 746                        (S ? J : I) :
 747                U ? T ? (S ? H : G) :
 748                        (S ? F : E) :
 749                    T ? (S ? D : C) :
 750                        (S ? B : A);
 751 \end{lstlisting}
 752
 753 The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_} represent d-type flip-flops.
 754
 755 The cell types {\tt \$\_DFFE\_[NP][NP]\_}
 756 implement d-type flip-flops with enable. The values in the table for these cell types relate to the
 757 following Verilog code template.
 758
 759 \begin{lstlisting}[mathescape,language=Verilog]
 760         always @($ClkEdge$ C)
 761                 if (EN == $EnLvl$)
 762                         Q <= D;
 763 \end{lstlisting}
 764
 765 The cell types {\tt \$\_DFF\_[NP][NP][01]\_} implement
 766 d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the
 767 following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
 768 if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
 769 otherwise.
 770
 771 \begin{lstlisting}[mathescape,language=Verilog]
 772         always @($ClkEdge$ C, $RstEdge$ R)
 773                 if (R == $RstLvl$)
 774                         Q <= $RstVal$;
 775                 else
 776                         Q <= D;
 777 \end{lstlisting}
 778
 779 The cell types {\tt \$\_SDFF\_[NP][NP][01]\_} implement
 780 d-type flip-flops with synchronous reset. The values in the table for these cell types relate to the
 781 following Verilog code template:
 782
 783 \begin{lstlisting}[mathescape,language=Verilog]
 784         always @($ClkEdge$ C)
 785                 if (R == $RstLvl$)
 786                         Q <= $RstVal$;
 787                 else
 788                         Q <= D;
 789 \end{lstlisting}
 790
 791 The cell types {\tt \$\_DFFE\_[NP][NP][01][NP]\_} implement
 792 d-type flip-flops with asynchronous reset and enable.  The values in the table for these cell types relate to the
 793 following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
 794 if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
 795 otherwise.
 796
 797 \begin{lstlisting}[mathescape,language=Verilog]
 798         always @($ClkEdge$ C, $RstEdge$ R)
 799                 if (R == $RstLvl$)
 800                         Q <= $RstVal$;
 801                 else if (EN == $EnLvl$)
 802                         Q <= D;
 803 \end{lstlisting}
 804
 805 The cell types {\tt \$\_SDFFE\_[NP][NP][01][NP]\_} implement d-type flip-flops
 806 with synchronous reset and enable, with reset having priority over enable.
 807 The values in the table for these cell types relate to the
 808 following Verilog code template:
 809
 810 \begin{lstlisting}[mathescape,language=Verilog]
 811         always @($ClkEdge$ C)
 812                 if (R == $RstLvl$)
 813                         Q <= $RstVal$;
 814                 else if (EN == $EnLvl$)
 815                         Q <= D;
 816 \end{lstlisting}
 817
 818 The cell types {\tt \$\_SDFFCE\_[NP][NP][01][NP]\_} implement d-type flip-flops
 819 with synchronous reset and enable, with enable having priority over reset.
 820 The values in the table for these cell types relate to the
 821 following Verilog code template:
 822
 823 \begin{lstlisting}[mathescape,language=Verilog]
 824         always @($ClkEdge$ C)
 825                 if (EN == $EnLvl$)
 826                         if (R == $RstLvl$)
 827                                 Q <= $RstVal$;
 828                         else
 829                                 Q <= D;
 830 \end{lstlisting}
 831
 832 The cell types {\tt \$\_DFFSR\_[NP][NP][NP]\_} implement
 833 d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the
 834 following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
 835 if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
 836 otherwise, and \lstinline[mathescape,language=Verilog];$SetEdge$; is \lstinline[language=Verilog];posedge;
 837 if \lstinline[mathescape,language=Verilog];$SetLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
 838 otherwise.
 839
 840 \begin{lstlisting}[mathescape,language=Verilog]
 841         always @($ClkEdge$ C, $RstEdge$ R, $SetEdge$ S)
 842                 if (R == $RstLvl$)
 843                         Q <= 0;
 844                 else if (S == $SetLvl$)
 845                         Q <= 1;
 846                 else
 847                         Q <= D;
 848 \end{lstlisting}
 849
 850 The cell types {\tt \$\_DFFSRE\_[NP][NP][NP][NP]\_} implement
 851 d-type flip-flops with asynchronous set and reset and enable. The values in the table for these cell types relate to the
 852 following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
 853 if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
 854 otherwise, and \lstinline[mathescape,language=Verilog];$SetEdge$; is \lstinline[language=Verilog];posedge;
 855 if \lstinline[mathescape,language=Verilog];$SetLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
 856 otherwise.
 857
 858 \begin{lstlisting}[mathescape,language=Verilog]
 859         always @($ClkEdge$ C, $RstEdge$ R, $SetEdge$ S)
 860                 if (R == $RstLvl$)
 861                         Q <= 0;
 862                 else if (S == $SetLvl$)
 863                         Q <= 1;
 864                 else if (E == $EnLvl$)
 865                         Q <= D;
 866 \end{lstlisting}
 867
 868 The cell types {\tt \$\_DLATCH\_N\_} and {\tt \$\_DLATCH\_P\_} represent d-type latches.
 869
 870 The cell types {\tt \$\_DLATCH\_[NP][NP][01]\_} implement
 871 d-type latches with reset. The values in the table for these cell types relate to the
 872 following Verilog code template:
 873
 874 \begin{lstlisting}[mathescape,language=Verilog]
 875         always @*
 876                 if (R == $RstLvl$)
 877                         Q <= $RstVal$;
 878                 else if (E == $EnLvl$)
 879                         Q <= D;
 880 \end{lstlisting}
 881
 882 The cell types {\tt \$\_DLATCHSR\_[NP][NP][NP]\_} implement
 883 d-type latches with set and reset. The values in the table for these cell types relate to the
 884 following Verilog code template:
 885
 886 \begin{lstlisting}[mathescape,language=Verilog]
 887         always @*
 888                 if (R == $RstLvl$)
 889                         Q <= 0;
 890                 else if (S == $SetLvl$)
 891                         Q <= 1;
 892                 else if (E == $EnLvl$)
 893                         Q <= D;
 894 \end{lstlisting}
 895
 896 The cell types {\tt \$\_SR\_[NP][NP]\_} implement
 897 sr-type latches. The values in the table for these cell types relate to the
 898 following Verilog code template:
 899
 900 \begin{lstlisting}[mathescape,language=Verilog]
 901         always @*
 902                 if (R == $RstLvl$)
 903                         Q <= 0;
 904                 else if (S == $SetLvl$)
 905                         Q <= 1;
 906 \end{lstlisting}
 907
 908 In most cases gate level logic networks are created from RTL networks using the {\tt techmap} pass. The flip-flop cells
 909 from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the {\tt dfflibmap}
 910 pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
 911 using the {\tt abc} pass.
 912
 913 \begin{fixme}
 914 Add information about {\tt \$slice} and {\tt \$concat} cells.
 915 \end{fixme}
 916
 917 \begin{fixme}
 918 Add information about {\tt \$lut} and {\tt \$sop} cells.
 919 \end{fixme}
 920
 921 \begin{fixme}
 922 Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
 923 \end{fixme}