manual/CHAPTER_Intro.tex

   1
   2 \chapter{Introduction}
   3 \label{chapter:intro}
   4
   5 This document presents the Free and Open Source (FOSS) Verilog HDL synthesis tool ``Yosys''.
   6 Its design and implementation as well as its performance on real-world designs
   7 is discussed in this document.
   8
   9 \section{History of Yosys}
  10
  11 A Hardware Description Language (HDL) is a computer language used to describe
  12 circuits. A HDL synthesis tool is a computer program that takes a formal
  13 description of a circuit written in an HDL as input and generates a netlist
  14 that implements the given circuit as output.
  15
  16 Currently the most widely used and supported HDLs for digital circuits are
  17 Verilog \cite{Verilog2005}\cite{VerilogSynth} and
  18 VHDL\footnote{VHDL is an acronym for ``VHSIC hardware description language''
  19 and VHSIC is an acronym for ``Very-High-Speed Integrated
  20 Circuits''.} \cite{VHDL}\cite{VHDLSynth}.
  21 Both HDLs are used for test and verification purposes as well as logic
  22 synthesis, resulting in a set of synthesizable and a set of non-synthesizable
  23 language features. In this document we only look at the synthesizable subset
  24 of the language features.
  25
  26 In recent work on heterogeneous coarse-grain reconfigurable
  27 logic \cite{intersynth} the need for a custom application-specific HDL synthesis
  28 tool emerged. It was soon realised that a synthesis tool that understood Verilog
  29 or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
  30 existing Verilog or VHDL front end, the work for writing the necessary
  31 additional features and integrating them in an existing tool can be estimated to be
  32 about the same as writing a new tool with support for a minimalistic custom HDL.
  33
  34 The proposed custom HDL synthesis tool should be licensed under a Free
  35 and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
  36 synthesis tool would have been needed as basis to build upon. The main advantages
  37 of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
  38 to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
  39 such a tool would have to provide a feature-complete implementation of the
  40 synthesizable HDL subset.
  41
  42 Basic RTL synthesis is a well understood field \cite{LogicSynthesis}. Lexing,
  43 parsing and processing of computer languages \cite{Dragonbook} is a thoroughly
  44 researched field. All the information required to write such tools has been openly
  45 available for a long time, and it is therefore likely that a FOSS HDL synthesis tool
  46 with a feature-complete Verilog or VHDL front end must exist which can be used as a basis for a custom RTL synthesis tool.
  47
  48 Due to the author's preference for Verilog over VHDL it was decided early
  49 on to go for Verilog instead of VHDL\footnote{A quick investigation into FOSS
  50 VHDL tools yielded similar grim results for FOSS VHDL synthesis tools.}.
  51 So the existing FOSS Verilog synthesis tools were evaluated (see
  52 App.~\ref{chapter:sota}).  The results of this evaluation are utterly
  53 devastating. Therefore a completely new Verilog synthesis tool was implemented
  54 and is recommended as basis for custom synthesis tools. This is the tool that
  55 is discussed in this document.
  56
  57 \section{Structure of this Document}
  58
  59 The structure of this document is as follows:
  60
  61 Chapter~\ref{chapter:intro} is this introduction.
  62
  63 Chapter~\ref{chapter:basics} covers a short introduction to the world of HDL
  64 synthesis. Basic principles and the terminology are outlined in this chapter.
  65
  66 Chapter~\ref{chapter:approach} gives the quickest possible outline to how the
  67 problem of implementing a HDL synthesis tool is approached in the case of
  68 Yosys.
  69
  70 Chapter~\ref{chapter:overview} contains a more detailed overview of the
  71 implementation of Yosys. This chapter covers the data structures used in
  72 Yosys to represent a design in detail and is therefore recommended reading
  73 for everyone who is interested in understanding the Yosys internals.
  74
  75 Chapter~\ref{chapter:celllib} covers the internal cell library used by Yosys.
  76 This is especially important knowledge for anyone who wants to understand the
  77 intermediate netlists used internally by Yosys.
  78
  79 Chapter~ \ref{chapter:prog} gives a tour to the internal APIs of Yosys. This
  80 is recommended reading for everyone who actually wants to read or write
  81 Yosys source code. The chapter concludes with an example loadable module
  82 for Yosys.
  83
  84 Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
  85 cover three important pieces of the synthesis pipeline: The Verilog frontend,
  86 the optimization passes and the technology mapping to the target architecture,
  87 respectively.
  88
  89 Chapter~\ref{chapter:eval} covers the evaluation of the performance
  90 (correctness and quality) of Yosys on real-world input data.
  91 The chapter concludes the main part of this document with conclusions and
  92 outlook to future work.
  93
  94 Various appendices, including a command reference manual
  95 (App.~\ref{commandref}) and an evaluation of pre-existing FOSS Verilog
  96 synthesis tools (App.~\ref{chapter:sota}) complete this document.
  97
  98