manual/CHAPTER_Prog/test.v

   1 module uut(in1, in2, in3, out1, out2);
   2
   3 input [8:0] in1, in2, in3;
   4 output [8:0] out1, out2;
   5
   6 assign out1 = in1 + in2 + (in3 >> 4);
   7
   8 endmodule