manual/CHAPTER_StateOfTheArt/always01.v

   1 module uut_always01(clock, reset, c3, c2, c1, c0);
   2
   3 input clock, reset;
   4 output c3, c2, c1, c0;
   5 reg [3:0] count;
   6
   7 assign {c3, c2, c1, c0} = count;
   8
   9 always @(posedge clock)
  10         count <= reset ? 0 : count + 1;
  11
  12 endmodule