manual/CHAPTER_StateOfTheArt/always01_pub.v

   1 module uut_always01(clock,
   2                 reset, count);
   3
   4 input clock, reset;
   5 output [3:0] count;
   6 reg [3:0] count;
   7
   8 always @(posedge clock)
   9         count <= reset ?
  10                 0 : count + 1;
  11
  12
  13
  14 endmodule