manual/CHAPTER_StateOfTheArt/arrays01.v

   1 module uut_arrays01(clock, we, addr, wr_data, rd_data);
   2
   3 input clock, we;
   4 input [3:0] addr, wr_data;
   5 output [3:0] rd_data;
   6 reg [3:0] rd_data;
   7
   8 reg [3:0] memory [15:0];
   9
  10 always @(posedge clock) begin
  11         if (we)
  12                 memory[addr] <= wr_data;
  13         rd_data <= memory[addr];
  14 end
  15
  16 endmodule