kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git] / manual / CHAPTER_StateOfTheArt / forgen02.v
1 module uut_forgen02(a, b, cin, y, cout);
2
3 parameter WIDTH = 8;
4
5 input [WIDTH-1:0] a, b;
6 input cin;
7
8 output [WIDTH-1:0] y;
9 output cout;
10
11 genvar i;
12 wire [WIDTH-1:0] carry;
13
14 generate
15 for (i = 0; i < WIDTH; i=i+1) begin:adder
16 wire [2:0] D;
17 assign D[1:0] = { a[i], b[i] };
18 if (i == 0) begin:chain
19 assign D[2] = cin;
20 end else begin:chain
21 assign D[2] = carry[i-1];
22 end
23 assign y[i] = ^D;
24 assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
25 end
26 endgenerate
27
28 assign cout = carry[WIDTH-1];
29
30 endmodule