manual/CHAPTER_StateOfTheArt/simlib_icarus.v

   1
   2 module cell0(Result0);
   3 output Result0;
   4 assign Result0 = 0;
   5 endmodule
   6
   7 module cell1(Result0);
   8 output Result0;
   9 assign Result0 = 1;
  10 endmodule
  11
  12 module ADD4(
  13         DataA0, DataA1, DataA2, DataA3,
  14         DataB0, DataB1, DataB2, DataB3,
  15         Result0, Result1, Result2, Result3, Cout
  16 );
  17 input DataA0, DataA1, DataA2, DataA3;
  18 input DataB0, DataB1, DataB2, DataB3;
  19 output Result0, Result1, Result2, Result3, Cout;
  20 assign {Cout, Result3, Result2, Result1, Result0} = {DataA3, DataA2, DataA1, DataA0} + {DataB3, DataB2, DataB1, DataB0};
  21 endmodule
  22
  23 module BUF(DATA, RESULT);
  24 input DATA;
  25 output RESULT;
  26 assign RESULT = DATA;
  27 endmodule
  28
  29 module INV(DATA, RESULT);
  30 input DATA;
  31 output RESULT;
  32 assign RESULT = ~DATA;
  33 endmodule
  34
  35 module fd4(
  36         Clock,
  37         Data0, Data1, Data2, Data3,
  38         Q0, Q1, Q2, Q3
  39 );
  40 input Clock;
  41 input Data0, Data1, Data2, Data3;
  42 output reg Q0, Q1, Q2, Q3;
  43 always @(posedge Clock)
  44         {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
  45 endmodule
  46
  47 module fdce1(
  48         Clock, Enable,
  49         Data0,
  50         Q0
  51 );
  52 input Clock, Enable;
  53 input Data0;
  54 output reg Q0;
  55 always @(posedge Clock)
  56         if (Enable)
  57                 Q0 <= Data0;
  58 endmodule
  59
  60 module fdce4(
  61         Clock, Enable,
  62         Data0, Data1, Data2, Data3,
  63         Q0, Q1, Q2, Q3
  64 );
  65 input Clock, Enable;
  66 input Data0, Data1, Data2, Data3;
  67 output reg Q0, Q1, Q2, Q3;
  68 always @(posedge Clock)
  69         if (Enable)
  70                 {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
  71 endmodule
  72
  73 module mux4_1_2(
  74         Sel0,
  75         Data0x0, Data0x1, Data0x2, Data0x3,
  76         Data1x0, Data1x1, Data1x2, Data1x3,
  77         Result0, Result1, Result2, Result3
  78 );
  79 input Sel0;
  80 input Data0x0, Data0x1, Data0x2, Data0x3;
  81 input Data1x0, Data1x1, Data1x2, Data1x3;
  82 output Result0, Result1, Result2, Result3;
  83 assign {Result0, Result1, Result2, Result3} = Sel0 ? {Data1x0, Data1x1, Data1x2, Data1x3} : {Data0x0, Data0x1, Data0x2, Data0x3};
  84 endmodule
  85
  86 module mux1_1_2(
  87         Sel0,
  88         Data0x0,
  89         Data1x0,
  90         Result0
  91 );
  92 input Sel0;
  93 input Data0x0;
  94 input Data1x0;
  95 output Result0;
  96 assign Result0 = Sel0 ? Data1x0 : Data0x0;
  97 endmodule
  98
  99 module xor2(
 100         DATA0X0,
 101         DATA1X0,
 102         RESULT0
 103 );
 104 input DATA0X0;
 105 input DATA1X0;
 106 output RESULT0;
 107 assign RESULT0 = DATA1X0 ^ DATA0X0;
 108 endmodule
 109
 110 module fdce64(
 111         Clock, Enable,
 112         Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
 113         Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
 114 );
 115 input Clock, Enable;
 116 input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
 117 output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
 118 always @(posedge Clock)
 119         if (Enable)
 120                 { Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
 121 endmodule
 122
 123 module mux4_4_16(
 124         Sel0, Sel1, Sel2, Sel3,
 125         Result0, Result1, Result2, Result3,
 126         Data0x0, Data0x1, Data0x2, Data0x3,
 127         Data1x0, Data1x1, Data1x2, Data1x3,
 128         Data2x0, Data2x1, Data2x2, Data2x3,
 129         Data3x0, Data3x1, Data3x2, Data3x3,
 130         Data4x0, Data4x1, Data4x2, Data4x3,
 131         Data5x0, Data5x1, Data5x2, Data5x3,
 132         Data6x0, Data6x1, Data6x2, Data6x3,
 133         Data7x0, Data7x1, Data7x2, Data7x3,
 134         Data8x0, Data8x1, Data8x2, Data8x3,
 135         Data9x0, Data9x1, Data9x2, Data9x3,
 136         Data10x0, Data10x1, Data10x2, Data10x3,
 137         Data11x0, Data11x1, Data11x2, Data11x3,
 138         Data12x0, Data12x1, Data12x2, Data12x3,
 139         Data13x0, Data13x1, Data13x2, Data13x3,
 140         Data14x0, Data14x1, Data14x2, Data14x3,
 141         Data15x0, Data15x1, Data15x2, Data15x3
 142 );
 143 input Sel0, Sel1, Sel2, Sel3;
 144 output Result0, Result1, Result2, Result3;
 145 input Data0x0, Data0x1, Data0x2, Data0x3;
 146 input Data1x0, Data1x1, Data1x2, Data1x3;
 147 input Data2x0, Data2x1, Data2x2, Data2x3;
 148 input Data3x0, Data3x1, Data3x2, Data3x3;
 149 input Data4x0, Data4x1, Data4x2, Data4x3;
 150 input Data5x0, Data5x1, Data5x2, Data5x3;
 151 input Data6x0, Data6x1, Data6x2, Data6x3;
 152 input Data7x0, Data7x1, Data7x2, Data7x3;
 153 input Data8x0, Data8x1, Data8x2, Data8x3;
 154 input Data9x0, Data9x1, Data9x2, Data9x3;
 155 input Data10x0, Data10x1, Data10x2, Data10x3;
 156 input Data11x0, Data11x1, Data11x2, Data11x3;
 157 input Data12x0, Data12x1, Data12x2, Data12x3;
 158 input Data13x0, Data13x1, Data13x2, Data13x3;
 159 input Data14x0, Data14x1, Data14x2, Data14x3;
 160 input Data15x0, Data15x1, Data15x2, Data15x3;
 161 assign {Result0, Result1, Result2, Result3} =
 162         {Sel3, Sel2, Sel1, Sel0} == 0 ? { Data0x0, Data0x1, Data0x2, Data0x3 } :
 163         {Sel3, Sel2, Sel1, Sel0} == 1 ? { Data1x0, Data1x1, Data1x2, Data1x3 } :
 164         {Sel3, Sel2, Sel1, Sel0} == 2 ? { Data2x0, Data2x1, Data2x2, Data2x3 } :
 165         {Sel3, Sel2, Sel1, Sel0} == 3 ? { Data3x0, Data3x1, Data3x2, Data3x3 } :
 166         {Sel3, Sel2, Sel1, Sel0} == 4 ? { Data4x0, Data4x1, Data4x2, Data4x3 } :
 167         {Sel3, Sel2, Sel1, Sel0} == 5 ? { Data5x0, Data5x1, Data5x2, Data5x3 } :
 168         {Sel3, Sel2, Sel1, Sel0} == 6 ? { Data6x0, Data6x1, Data6x2, Data6x3 } :
 169         {Sel3, Sel2, Sel1, Sel0} == 7 ? { Data7x0, Data7x1, Data7x2, Data7x3 } :
 170         {Sel3, Sel2, Sel1, Sel0} == 8 ? { Data8x0, Data8x1, Data8x2, Data8x3 } :
 171         {Sel3, Sel2, Sel1, Sel0} == 9 ? { Data9x0, Data9x1, Data9x2, Data9x3 } :
 172         {Sel3, Sel2, Sel1, Sel0} == 10 ? { Data10x0, Data10x1, Data10x2, Data10x3 } :
 173         {Sel3, Sel2, Sel1, Sel0} == 11 ? { Data11x0, Data11x1, Data11x2, Data11x3 } :
 174         {Sel3, Sel2, Sel1, Sel0} == 12 ? { Data12x0, Data12x1, Data12x2, Data12x3 } :
 175         {Sel3, Sel2, Sel1, Sel0} == 13 ? { Data13x0, Data13x1, Data13x2, Data13x3 } :
 176         {Sel3, Sel2, Sel1, Sel0} == 14 ? { Data14x0, Data14x1, Data14x2, Data14x3 } :
 177         {Sel3, Sel2, Sel1, Sel0} == 15 ? { Data15x0, Data15x1, Data15x2, Data15x3 } : 'bx;
 178 endmodule
 179
 180 module mux1_5_32(
 181         Sel0, Sel1, Sel2, Sel3, Sel4,
 182         Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0,
 183         Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0,
 184         Result0
 185 );
 186 input Sel0, Sel1, Sel2, Sel3, Sel4;
 187 input Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0;
 188 input Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0;
 189 output Result0;
 190 assign Result0 =
 191         {Sel4, Sel3, Sel2, Sel1, Sel0} == 0 ? Data0x0 :
 192         {Sel4, Sel3, Sel2, Sel1, Sel0} == 1 ? Data1x0 :
 193         {Sel4, Sel3, Sel2, Sel1, Sel0} == 2 ? Data2x0 :
 194         {Sel4, Sel3, Sel2, Sel1, Sel0} == 3 ? Data3x0 :
 195         {Sel4, Sel3, Sel2, Sel1, Sel0} == 4 ? Data4x0 :
 196         {Sel4, Sel3, Sel2, Sel1, Sel0} == 5 ? Data5x0 :
 197         {Sel4, Sel3, Sel2, Sel1, Sel0} == 6 ? Data6x0 :
 198         {Sel4, Sel3, Sel2, Sel1, Sel0} == 7 ? Data7x0 :
 199         {Sel4, Sel3, Sel2, Sel1, Sel0} == 8 ? Data8x0 :
 200         {Sel4, Sel3, Sel2, Sel1, Sel0} == 9 ? Data9x0 :
 201         {Sel4, Sel3, Sel2, Sel1, Sel0} == 10 ? Data10x0 :
 202         {Sel4, Sel3, Sel2, Sel1, Sel0} == 11 ? Data11x0 :
 203         {Sel4, Sel3, Sel2, Sel1, Sel0} == 12 ? Data12x0 :
 204         {Sel4, Sel3, Sel2, Sel1, Sel0} == 13 ? Data13x0 :
 205         {Sel4, Sel3, Sel2, Sel1, Sel0} == 14 ? Data14x0 :
 206         {Sel4, Sel3, Sel2, Sel1, Sel0} == 15 ? Data15x0 :
 207         {Sel4, Sel3, Sel2, Sel1, Sel0} == 16 ? Data16x0 :
 208         {Sel4, Sel3, Sel2, Sel1, Sel0} == 17 ? Data17x0 :
 209         {Sel4, Sel3, Sel2, Sel1, Sel0} == 18 ? Data18x0 :
 210         {Sel4, Sel3, Sel2, Sel1, Sel0} == 19 ? Data19x0 :
 211         {Sel4, Sel3, Sel2, Sel1, Sel0} == 20 ? Data20x0 :
 212         {Sel4, Sel3, Sel2, Sel1, Sel0} == 21 ? Data21x0 :
 213         {Sel4, Sel3, Sel2, Sel1, Sel0} == 22 ? Data22x0 :
 214         {Sel4, Sel3, Sel2, Sel1, Sel0} == 23 ? Data23x0 :
 215         {Sel4, Sel3, Sel2, Sel1, Sel0} == 24 ? Data24x0 :
 216         {Sel4, Sel3, Sel2, Sel1, Sel0} == 25 ? Data25x0 :
 217         {Sel4, Sel3, Sel2, Sel1, Sel0} == 26 ? Data26x0 :
 218         {Sel4, Sel3, Sel2, Sel1, Sel0} == 27 ? Data27x0 :
 219         {Sel4, Sel3, Sel2, Sel1, Sel0} == 28 ? Data28x0 :
 220         {Sel4, Sel3, Sel2, Sel1, Sel0} == 29 ? Data29x0 :
 221         {Sel4, Sel3, Sel2, Sel1, Sel0} == 30 ? Data30x0 :
 222         {Sel4, Sel3, Sel2, Sel1, Sel0} == 31 ? Data31x0 : 'bx;
 223 endmodule
 224