manual/CHAPTER_StateOfTheArt/simlib_yosys.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell simulation library.
  21  *
  22  *  This Verilog library contains simple simulation models for the internal
  23  *  logic cells (_NOT_, _AND_, ...) that are generated by the default technology
  24  *  mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
  25  *
  26  */
  27
  28 module _NOT_(A, Y);
  29 input A;
  30 output Y;
  31 assign Y = ~A;
  32 endmodule
  33
  34 module _AND_(A, B, Y);
  35 input A, B;
  36 output Y;
  37 assign Y = A & B;
  38 endmodule
  39
  40 module _OR_(A, B, Y);
  41 input A, B;
  42 output Y;
  43 assign Y = A | B;
  44 endmodule
  45
  46 module _XOR_(A, B, Y);
  47 input A, B;
  48 output Y;
  49 assign Y = A ^ B;
  50 endmodule
  51
  52 module _MUX_(A, B, S, Y);
  53 input A, B, S;
  54 output reg Y;
  55 always @* begin
  56         if (S)
  57                 Y = B;
  58         else
  59                 Y = A;
  60 end
  61 endmodule
  62
  63 module _DFF_N_(D, Q, C);
  64 input D, C;
  65 output reg Q;
  66 always @(negedge C) begin
  67         Q <= D;
  68 end
  69 endmodule
  70
  71 module _DFF_P_(D, Q, C);
  72 input D, C;
  73 output reg Q;
  74 always @(posedge C) begin
  75         Q <= D;
  76 end
  77 endmodule
  78
  79 module _DFF_NN0_(D, Q, C, R);
  80 input D, C, R;
  81 output reg Q;
  82 always @(negedge C or negedge R) begin
  83         if (R == 0)
  84                 Q <= 0;
  85         else
  86                 Q <= D;
  87 end
  88 endmodule
  89
  90 module _DFF_NN1_(D, Q, C, R);
  91 input D, C, R;
  92 output reg Q;
  93 always @(negedge C or negedge R) begin
  94         if (R == 0)
  95                 Q <= 1;
  96         else
  97                 Q <= D;
  98 end
  99 endmodule
 100
 101 module _DFF_NP0_(D, Q, C, R);
 102 input D, C, R;
 103 output reg Q;
 104 always @(negedge C or posedge R) begin
 105         if (R == 1)
 106                 Q <= 0;
 107         else
 108                 Q <= D;
 109 end
 110 endmodule
 111
 112 module _DFF_NP1_(D, Q, C, R);
 113 input D, C, R;
 114 output reg Q;
 115 always @(negedge C or posedge R) begin
 116         if (R == 1)
 117                 Q <= 1;
 118         else
 119                 Q <= D;
 120 end
 121 endmodule
 122
 123 module _DFF_PN0_(D, Q, C, R);
 124 input D, C, R;
 125 output reg Q;
 126 always @(posedge C or negedge R) begin
 127         if (R == 0)
 128                 Q <= 0;
 129         else
 130                 Q <= D;
 131 end
 132 endmodule
 133
 134 module _DFF_PN1_(D, Q, C, R);
 135 input D, C, R;
 136 output reg Q;
 137 always @(posedge C or negedge R) begin
 138         if (R == 0)
 139                 Q <= 1;
 140         else
 141                 Q <= D;
 142 end
 143 endmodule
 144
 145 module _DFF_PP0_(D, Q, C, R);
 146 input D, C, R;
 147 output reg Q;
 148 always @(posedge C or posedge R) begin
 149         if (R == 1)
 150                 Q <= 0;
 151         else
 152                 Q <= D;
 153 end
 154 endmodule
 155
 156 module _DFF_PP1_(D, Q, C, R);
 157 input D, C, R;
 158 output reg Q;
 159 always @(posedge C or posedge R) begin
 160         if (R == 1)
 161                 Q <= 1;
 162         else
 163                 Q <= D;
 164 end
 165 endmodule
 166