Document division and modulo cells
[yosys.git] / manual / PRESENTATION_ExOth / axis_test.v
1 module axis_test(aclk, tready);
2 input aclk, tready;
3 wire aresetn, tvalid;
4 wire [7:0] tdata;
5
6 integer counter = 0;
7 reg aresetn = 0;
8
9 axis_master uut (aclk, aresetn, tvalid, tready, tdata);
10
11 always @(posedge aclk) begin
12 if (aresetn && tready && tvalid) begin
13 if (counter == 0) assert(tdata == 19);
14 if (counter == 1) assert(tdata == 99);
15 if (counter == 2) assert(tdata == 1);
16 if (counter == 3) assert(tdata == 244);
17 if (counter == 4) assert(tdata == 133);
18 if (counter == 5) assert(tdata == 209);
19 if (counter == 6) assert(tdata == 241);
20 if (counter == 7) assert(tdata == 137);
21 if (counter == 8) assert(tdata == 176);
22 if (counter == 9) assert(tdata == 6);
23 counter <= counter + 1;
24 end
25 aresetn <= 1;
26 end
27 endmodule