manual/PRESENTATION_ExOth/scrambler.v

   1 module scrambler(
   2         input clk, rst, in_bit,
   3         output reg out_bit
   4 );
   5     reg [31:0] xs;
   6     always @(posedge clk) begin
   7         if (rst)
   8             xs = 1;
   9         xs = xs ^ (xs << 13);
  10         xs = xs ^ (xs >> 17);
  11         xs = xs ^ (xs << 5);
  12         out_bit <= in_bit ^ xs[0];
  13     end
  14 endmodule