manual/PRESENTATION_ExSyn/abc_01.v

   1 module test(input clk, a, b, c,
   2             output reg y);
   3
   4         reg [2:0] q1, q2;
   5         always @(posedge clk) begin
   6                 q1 <= { a, b, c };
   7                 q2 <= q1;
   8                 y <= ^q2;
   9         end
  10 endmodule