manual/PRESENTATION_ExSyn/abc_01_cells.v

   1
   2 module BUF(A, Y);
   3 input A;
   4 output Y = A;
   5 endmodule
   6
   7 module NOT(A, Y);
   8 input A;
   9 output Y = ~A;
  10 endmodule
  11
  12 module NAND(A, B, Y);
  13 input A, B;
  14 output Y = ~(A & B);
  15 endmodule
  16
  17 module NOR(A, B, Y);
  18 input A, B;
  19 output Y = ~(A | B);
  20 endmodule
  21
  22 module DFF(C, D, Q);
  23 input C, D;
  24 output reg Q;
  25 always @(posedge C)
  26         Q <= D;
  27 endmodule
  28
  29 module DFFSR(C, D, Q, S, R);
  30 input C, D, S, R;
  31 output reg Q;
  32 always @(posedge C, posedge S, posedge R)
  33         if (S)
  34                 Q <= 1'b1;
  35         else if (R)
  36                 Q <= 1'b0;
  37         else
  38                 Q <= D;
  39 endmodule
  40