manual/PRESENTATION_ExSyn/memory_01.v

   1 module test(input      CLK, ADDR,
   2             input      [7:0] DIN,
   3             output reg [7:0] DOUT);
   4     reg [7:0] mem [0:1];
   5     always @(posedge CLK) begin
   6         mem[ADDR] <= DIN;
   7         DOUT <= mem[ADDR];
   8     end
   9 endmodule