manual/PRESENTATION_ExSyn/memory_02.v

   1 module test(
   2     input             WR1_CLK,  WR2_CLK,
   3     input             WR1_WEN,  WR2_WEN,
   4     input      [7:0]  WR1_ADDR, WR2_ADDR,
   5     input      [7:0]  WR1_DATA, WR2_DATA,
   6     input             RD1_CLK,  RD2_CLK,
   7     input      [7:0]  RD1_ADDR, RD2_ADDR,
   8     output reg [7:0]  RD1_DATA, RD2_DATA
   9 );
  10
  11 reg [7:0] memory [0:255];
  12
  13 always @(posedge WR1_CLK)
  14     if (WR1_WEN)
  15         memory[WR1_ADDR] <= WR1_DATA;
  16
  17 always @(posedge WR2_CLK)
  18     if (WR2_WEN)
  19         memory[WR2_ADDR] <= WR2_DATA;
  20
  21 always @(posedge RD1_CLK)
  22     RD1_DATA <= memory[RD1_ADDR];
  23
  24 always @(posedge RD2_CLK)
  25     RD2_DATA <= memory[RD2_ADDR];
  26
  27 endmodule