manual/PRESENTATION_ExSyn/opt_04.v

   1 module test(input CLK, ARST,
   2             output [7:0] Q1, Q2, Q3);
   3
   4 wire NO_CLK = 0;
   5
   6 always @(posedge CLK, posedge ARST)
   7         if (ARST)
   8                 Q1 <= 42;
   9
  10 always @(posedge NO_CLK, posedge ARST)
  11         if (ARST)
  12                 Q2 <= 42;
  13         else
  14                 Q2 <= 23;
  15
  16 always @(posedge CLK)
  17         Q3 <= 42;
  18
  19 endmodule