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kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git]
/
manual
/
PRESENTATION_ExSyn
/
proc_01.v
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module test(input D, C, R, output reg Q);
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always @(posedge C, posedge R)
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if (R)
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Q <= 0;
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else
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Q <= D;
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endmodule