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Improve igloo2 example
[yosys.git]
/
manual
/
PRESENTATION_ExSyn
/
proc_03.v
1
module test(input A, B, C, D, E,
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output reg Y);
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always @* begin
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Y <= A;
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if (B)
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Y <= C;
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if (D)
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Y <= E;
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end
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endmodule