2 \section{Yosys by example -- Synthesis
}
8 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
10 \subsection{Typical Phases of a Synthesis Flow
}
12 \begin{frame
}{\subsecname}
14 \item Reading and elaborating the design
15 \item Higher-level synthesis and optimization
17 \item Converting
{\tt always
}-blocks to logic and registers
18 \item Perform coarse-grain optimizations (resource sharing, const folding, ...)
19 \item Handling of memories and other coarse-grain blocks
20 \item Extracting and optimizing finite state machines
22 \item Convert remaining logic to bit-level logic functions
23 \item Perform optimizations on bit-level logic functions
24 \item Map bit-level logic gates and registers to cell library
25 \item Write results to output file
29 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
31 \subsection{Reading the design
}
33 \begin{frame
}[fragile
]{\subsecname}
34 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
36 read_verilog -I include_dir -D enable_foo -D WIDTH=
12 file2.v
37 read_verilog -lib cell_library.v
39 verilog_defaults -add -I include_dir
42 verilog_defaults -clear
44 verilog_defaults -push
45 verilog_defaults -add -I include_dir
52 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
54 \subsection{Design elaboration
}
56 \begin{frame
}[fragile
]{\subsecname}
57 During design elaboration Yosys figures out how the modules are hierarchically
58 connected. It also re-runs the AST parts of the Verilog frontend to create
59 all needed variations of parametric modules.
62 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
63 # simplest form. at least this version should be used after reading all input files
67 # recommended form. fails if parts of the design hierarchy are missing, removes
68 # everything that is unreachable from the top module, and marks the top module.
70 hierarchy -check -top top_module
74 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
76 \subsection{The
{\tt proc
} command
}
78 \begin{frame
}[fragile
]{\subsecname}
79 The Verilog frontend converts
{\tt always
}-blocks to RTL netlists for the
80 expressions and ``processes'' for the control- and memory elements.
83 The
{\tt proc
} command transforms this ``processes'' to netlists of RTL
84 multiplexer and register cells.
87 The
{\tt proc
} command is actually a macro-command that calls the following
90 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
91 proc_clean # remove empty branches and processes
92 proc_rmdead # remove unreachable branches
93 proc_init # special handling of "initial" blocks
94 proc_arst # identify modeling of async resets
95 proc_mux # convert decision trees to multiplexer networks
96 proc_dff # extract registers from processes
97 proc_clean # if all went fine, this should remove all the processes
101 Many commands can not operate on modules with ``processes'' in them. Usually
102 a call to
{\tt proc
} is the first command in the actual synthesis procedure
103 after design elaboration.
106 \begin{frame
}[fragile
]{\subsecname{} -- Example
1/
3}
109 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_01.v
}
111 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/proc_01.ys
}
113 \hfil\includegraphics[width=
8cm,trim=
0 0cm
0 0cm
]{PRESENTATION_ExSyn/proc_01.pdf
}
116 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
3}
117 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
2.5cm
]{PRESENTATION_ExSyn/proc_02.pdf
}\vss}
121 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_02.v
}
123 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/proc_02.ys
}
127 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
3/
3}
128 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
1.5cm
]{PRESENTATION_ExSyn/proc_03.pdf
}\vss}
132 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/proc_03.ys
}
134 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_03.v
}
138 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
140 \subsection{The
{\tt opt
} command
}
142 \begin{frame
}[fragile
]{\subsecname}
143 The
{\tt opt
} command implements a series of simple optimizations. It also
144 is a macro command that calls other commands:
146 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
147 opt_expr # const folding and simple expression rewriting
148 opt_merge -nomux # merging identical cells
151 opt_muxtree # remove never-active branches from multiplexer tree
152 opt_reduce # consolidate trees of boolean ops to reduce functions
153 opt_merge # merging identical cells
154 opt_rmdff # remove/simplify registers with constant inputs
155 opt_clean # remove unused objects (cells, wires) from design
156 opt_expr # const folding and simple expression rewriting
157 while
[changed design
]
160 The command
{\tt clean
} can be used as alias for
{\tt opt
\_clean}. And
{\tt ;;
}
161 can be used as shortcut for
{\tt clean
}. For example:
163 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
164 proc; opt; memory; opt_expr;; fsm;;
168 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
1/
4}
169 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
0.5cm
]{PRESENTATION_ExSyn/opt_01.pdf
}\vss}
173 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/opt_01.ys
}
175 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_01.v
}
179 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
4}
180 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm
0cm
]{PRESENTATION_ExSyn/opt_02.pdf
}\vss}
184 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/opt_02.ys
}
186 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_02.v
}
190 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
3/
4}
191 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
2cm
]{PRESENTATION_ExSyn/opt_03.pdf
}\vss}
195 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/opt_03.ys
}
197 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_03.v
}
201 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
4/
4}
202 \vbox to
0cm
{\hskip6cm\includegraphics[width=
6cm,trim=
0cm
0cm
0cm -
3cm
]{PRESENTATION_ExSyn/opt_04.pdf
}\vss}
206 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_04.v
}
208 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/opt_04.ys
}
212 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
214 \subsection{When to use
{\tt opt
} or
{\tt clean
}}
216 \begin{frame
}{\subsecname}
217 Usually it does not hurt to call
{\tt opt
} after each regular command in the
218 synthesis script. But it increases the synthesis time, so it is favourable
219 to only call
{\tt opt
} when an improvement can be achieved.
222 The designs in
{\tt yosys-bigsim
} are a good playground for experimenting with
223 the effects of calling
{\tt opt
} in various places of the flow.
226 It generally is a good idea to call
{\tt opt
} before inherently expensive
227 commands such as
{\tt sat
} or
{\tt freduce
}, as the possible gain is much
228 higher in this cases as the possible loss.
231 The
{\tt clean
} command on the other hand is very fast and many commands leave
232 a mess (dangling signal wires, etc). For example, most commands do not remove
233 any wires or cells. They just change the connections and depend on a later
234 call to clean to get rid of the now unused objects. So the occasional
{\tt ;;
}
235 is a good idea in every synthesis script.
238 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
240 \subsection{The
{\tt memory
} command
}
242 \begin{frame
}[fragile
]{\subsecname}
243 In the RTL netlist, memory reads and writes are individual cells. This makes
244 consolidating the number of ports for a memory easier. The
{\tt memory
}
245 transforms memories to an implementation. Per default that is logic for address
246 decoders and registers. It also is a macro command that calls other commands:
248 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
249 # this merges registers into the memory read- and write cells.
252 # this collects all read and write cells for a memory and transforms them
253 # into one multi-port memory cell.
256 # this takes the multi-port memory cell and transforms it to address decoder
257 # logic and registers. This step is skipped if "memory" is called with -nomap.
262 Usually it is preferred to use architecture-specific RAM resources for memory.
265 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
266 memory -nomap; techmap -map my_memory_map.v; memory_map
270 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
1/
2}
271 \vbox to
0cm
{\includegraphics[width=
0.7\linewidth,trim=
0cm
0cm
0cm -
10cm
]{PRESENTATION_ExSyn/memory_01.pdf
}\vss}
275 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/memory_01.ys
}
277 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/memory_01.v
}
281 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
2}
282 \vbox to
0cm
{\hfill\includegraphics[width=
7.5cm,trim=
0cm
0cm
0cm -
5cm
]{PRESENTATION_ExSyn/memory_02.pdf
}\vss}
286 \lstinputlisting[basicstyle=
\ttfamily\fontsize{6pt
}{8pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/memory_02.v
}
288 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/memory_02.ys
}
292 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
294 \subsection{The
{\tt fsm
} command
}
296 \begin{frame
}[fragile
]{\subsecname{}}
297 The
{\tt fsm
} command identifies, extracts, optimizes (re-encodes), and
298 re-synthesizes finite state machines. It again is a macro that calls
299 a series of other commands:
301 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
302 fsm_detect # unless got option -nodetect
309 fsm_expand # if got option -expand
310 clean # if got option -expand
311 fsm_opt # if got option -expand
313 fsm_recode # unless got option -norecode
317 fsm_export # if got option -export
318 fsm_map # unless got option -nomap
322 \begin{frame
}{\subsecname{} -- details
}
323 Some details on the most important commands from the
{\tt fsm
\_*
} group:
326 The
{\tt fsm
\_detect} command identifies FSM state registers and marks them
327 with the
{\tt (* fsm\_encoding = "auto" *)} attribute, if they do not have the
328 {\tt fsm
\_encoding} set already. Mark registers with
{\tt (* fsm\_encoding =
329 "none" *)} to disable FSM optimization for a register.
332 The
{\tt fsm
\_extract} command replaces the entire FSM (logic and state
333 registers) with a
{\tt \$fsm
} cell.
336 The commands
{\tt fsm
\_opt} and
{\tt fsm
\_recode} can be used to optimize the
340 Finally the
{\tt fsm
\_map} command can be used to convert the (optimized)
{\tt
341 \$fsm
} cell back to logic and registers.
344 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
346 \subsection{The
{\tt techmap
} command
}
348 \begin{frame
}[t
]{\subsecname}
349 \vbox to
0cm
{\includegraphics[width=
12cm,trim=-
15cm
0cm
0cm -
20cm
]{PRESENTATION_ExSyn/techmap_01.pdf
}\vss}
351 The
{\tt techmap
} command replaces cells with implementations given as
352 verilog source. For example implementing a
32 bit adder using
16 bit adders:
356 \lstinputlisting[basicstyle=
\ttfamily\fontsize{6pt
}{7pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/techmap_01_map.v
}
359 \lstinputlisting[xleftmargin=
5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single, language=verilog
]{PRESENTATION_ExSyn/techmap_01.v
}
360 \lstinputlisting[xleftmargin=
5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/techmap_01.ys
}
364 \begin{frame
}[t
]{\subsecname{} -- stdcell mapping
}
365 When
{\tt techmap
} is used without a map file, it uses a built-in map file
366 to map all RTL cell types to a generic library of built-in logic gates and registers.
369 \begin{block
}{The built-in logic gate types are:
}
370 {\tt \$
\_NOT\_ \$
\_AND\_ \$
\_OR\_ \$
\_XOR\_ \$
\_MUX\_}
374 \begin{block
}{The register types are:
}
375 {\tt \$
\_SR\_NN\_ \$
\_SR\_NP\_ \$
\_SR\_PN\_ \$
\_SR\_PP\_ \\
376 \$
\_DFF\_N\_ \$
\_DFF\_P\_ \\
377 \$
\_DFF\_NN0\_ \$
\_DFF\_NN1\_ \$
\_DFF\_NP0\_ \$
\_DFF\_NP1\_ \\
378 \$
\_DFF\_PN0\_ \$
\_DFF\_PN1\_ \$
\_DFF\_PP0\_ \$
\_DFF\_PP1\_ \\
379 \$
\_DFFSR\_NNN\_ \$
\_DFFSR\_NNP\_ \$
\_DFFSR\_NPN\_ \$
\_DFFSR\_NPP\_ \\
380 \$
\_DFFSR\_PNN\_ \$
\_DFFSR\_PNP\_ \$
\_DFFSR\_PPN\_ \$
\_DFFSR\_PPP\_ \\
381 \$
\_DLATCH\_N\_ \$
\_DLATCH\_P\_}
385 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
387 \subsection{The
{\tt abc
} command
}
389 \begin{frame
}{\subsecname}
390 The
{\tt abc
} command provides an interface to ABC
\footnote[frame
]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/
}},
391 an open source tool for low-level logic synthesis.
394 The
{\tt abc
} command processes a netlist of internal gate types and can perform:
396 \item logic minimization (optimization)
397 \item mapping of logic to standard cell library (liberty format)
398 \item mapping of logic to k-LUTs (for FPGA synthesis)
402 Optionally
{\tt abc
} can process registers from one clock domain and perform
403 sequential optimization (such as register balancing).
406 ABC is also controlled using scripts. An ABC script can be specified to use
407 more advanced ABC features. It is also possible to write the design with
408 {\tt write
\_blif} and load the output file into ABC outside of Yosys.
411 \begin{frame
}[fragile
]{\subsecname{} -- Example
}
414 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/abc_01.v
}
416 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys, frame=single
]{PRESENTATION_ExSyn/abc_01.ys
}
418 \includegraphics[width=
\linewidth,trim=
0 0cm
0 0cm
]{PRESENTATION_ExSyn/abc_01.pdf
}
421 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
423 \subsection{Other special-purpose mapping commands
}
425 \begin{frame
}{\subsecname}
426 \begin{block
}{\tt dfflibmap
}
427 This command maps the internal register cell types to the register types
428 described in a liberty file.
432 \begin{block
}{\tt hilomap
}
433 Some architectures require special driver cells for driving a constant hi or lo
434 value. This command replaces simple constants with instances of such driver cells.
438 \begin{block
}{\tt iopadmap
}
439 Top-level input/outputs must usually be implemented using special I/O-pad cells.
440 This command inserts this cells to the design.
444 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
446 \subsection{Example Synthesis Script
}
448 \begin{frame
}[fragile
]{\subsecname}
451 \begin{lstlisting
}[basicstyle=
\ttfamily\fontsize{6pt
}{7pt
}\selectfont, language=ys
]
452 # read and elaborate design
453 read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
454 read_verilog -D WITH_MULT cpu_alu.v
455 hierarchy -check -top cpu_top
457 # high-level synthesis
458 proc; opt; fsm;; memory -nomap; opt
460 # substitute block rams
461 techmap -map map_rams.v
463 # map remaining memories
466 # low-level synthesis
467 techmap; opt; flatten;; abc -lut6
468 techmap -map map_xl_cells.v
471 select -set xl_clocks t:FDRE
%x:+FDRE[C] t:FDRE %d
472 iopadmap -inpad BUFGP O:I @xl_clocks
475 select -set xl_nonclocks w:* t:BUFGP
%x:+BUFGP[I] %d
476 iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
478 # write synthesis results
479 write_edif synth.edif
483 \begin{block
}{Teaser / Outlook
}
485 The weird
{\tt select
} expressions at the end of this script are discussed in
486 the next part (Section
3, ``Advanced Synthesis'') of this presentation.
}
491 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
495 \begin{frame
}{\subsecname}
497 \item Yosys provides commands for each phase of the synthesis.
498 \item Each command solves a (more or less) simple problem.
499 \item Complex commands are often only front-ends to simple commands.
500 \item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;
}
512 \url{http://www.clifford.at/yosys/
}
projects / yosys.git / blob