2 \section{Yosys by example -- Synthesis
}
8 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
10 \subsection{Typical Phases of a Synthesis Flow
}
12 \begin{frame
}{\subsecname}
14 \item Reading and elaborating the design
15 \item High-level synthesis and optimization
17 \item Converting
{\tt always
}-blocks to logic and registers
18 \item Perform coarse-grain optimizations (resource sharing, const folding, ...)
19 \item Handling of memories and other coarse-grain blocks
20 \item Extracting and optimizing finite state machines
22 \item Convert remaining logic to bit-level logic functions
23 \item Perform optimizations on bit-level logic functions
24 \item Map bit-level logic and register to gates from cell library
25 \item Write results to output file
29 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
31 \subsection{Reading the design
}
33 \begin{frame
}[fragile
]{\subsecname}
34 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
36 read_verilog -I include_dir -D enable_foo -D WIDTH=
12 file2.v
37 read_verilog -lib cell_library.v
39 verilog_defaults -add -I include_dir
42 verilog_defaults -clear
44 verilog_defaults -push
45 verilog_defaults -add -I include_dir
52 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
54 \subsection{Design elaboration
}
56 \begin{frame
}[fragile
]{\subsecname}
57 During design elaboration Yosys figures out how the modules are hierarchically
58 connected. It also re-runs the AST parts of the Verilog frontend to create
59 all needed variations of parametric modules.
62 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
63 # simplest form. at least this version should be used after reading all input files
67 # recommended form. fail if parts of the design hierarchy are missing. remove
68 # everything that is unreachable by the top module. mark the top module.
70 hierarchy -check -top top_module
74 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
76 \subsection{The ``proc'' commands
}
78 \begin{frame
}[fragile
]{\subsecname}
79 The Verilog frontend converts
{\tt always
}-blocks to RTL netlists for the
80 expressions and ``processes'' for the control- and memory elements.
83 The
{\tt proc
} command transforms this ``processes'' to netlists of RTL
84 multiplexer and register cells.
87 The
{\tt proc
} command is actually a macro-command that calls the following
90 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
91 proc_clean # remove empty branches and processes
92 proc_rmdead # remove unreachable branches
93 proc_init # special handling of "initial" blocks
94 proc_arst # identify modeling of async resets
95 proc_mux # convert decision trees to multiplexer networks
96 proc_dff # extract registers from processes
97 proc_clean # if all went fine, this should remove all the processes
101 Many commands can not operate on modules with ``processes'' in them. Usually
102 a call to
{\tt proc
} is the first command in the actual synthesis procedure
103 after design elaboration.
106 \begin{frame
}[fragile
]{\subsecname{} -- Example
1/
3}
109 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_01.v
}
111 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/proc_01.ys
}
113 \hfil\includegraphics[width=
8cm,trim=
0 0cm
0 0cm
]{PRESENTATION_ExSyn/proc_01.pdf
}
116 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
3}
117 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
2.5cm
]{PRESENTATION_ExSyn/proc_02.pdf
}\vss}
121 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_02.v
}
123 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/proc_02.ys
}
127 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
3/
3}
128 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
1.5cm
]{PRESENTATION_ExSyn/proc_03.pdf
}\vss}
132 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/proc_03.ys
}
134 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/proc_03.v
}
138 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
140 \subsection{The ``opt'' commands
}
142 \begin{frame
}[fragile
]{\subsecname}
143 The
{\tt opt
} command implements a series of simple optimizations. It also
144 is a macro command that calls other commands:
146 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
147 opt_const # const folding
148 opt_share -nomux # merging identical cells
151 opt_muxtree # remove never-active branches from multiplexer tree
152 opt_reduce # consolidate trees of boolean ops to reduce functions
153 opt_share # merging identical cells
154 opt_rmdff # remove/simplify registers with constant inputs
155 opt_clean # remove unused objects (cells, wires) from design
156 opt_const # const folding
157 while
[changed design
]
160 The command
{\tt clean
} can be used as alias for
{\tt opt
\_clean}. And
{\tt ;;
}
161 can be used as shortcut for
{\tt clean
}. For example:
163 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
164 proc; opt; memory; opt_const;; fsm;;
168 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
1/
4}
169 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
0.5cm
]{PRESENTATION_ExSyn/opt_01.pdf
}\vss}
173 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/opt_01.ys
}
175 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_01.v
}
179 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
4}
180 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm
0cm
]{PRESENTATION_ExSyn/opt_02.pdf
}\vss}
184 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/opt_02.ys
}
186 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_02.v
}
190 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
3/
4}
191 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
2cm
]{PRESENTATION_ExSyn/opt_03.pdf
}\vss}
195 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/opt_03.ys
}
197 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_03.v
}
201 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
4/
4}
202 \vbox to
0cm
{\hskip6cm\includegraphics[width=
6cm,trim=
0cm
0cm
0cm -
3cm
]{PRESENTATION_ExSyn/opt_04.pdf
}\vss}
206 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/opt_04.v
}
208 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/opt_04.ys
}
212 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
214 \subsection{When to use ``opt'' or ``clean''
}
216 \begin{frame
}{\subsecname}
217 Usually it does not hurt to call
{\tt opt
} after each regular command in the
218 synthesis script. But it increases the synthesis time, so it is favourable
219 to only call
{\tt opt
} when an improvement can be archieved.
222 The designs in
{\tt yosys-bigsim
} are a good playground for experimenting with
223 the effects of calling
{\tt opt
} in various places of the flow.
226 It generally is a good idea us call
{\tt opt
} before inherently expensive
227 commands such as
{\tt sat
} or
{\tt freduce
}, as the possible gain is much
228 higher in this cases as the possible loss.
231 The
{\tt clean
} command on the other hand is very fast and many commands leave
232 a mess (dangling signal wires, etc). For example, most commands do not remove
233 any wires or cells. They just change the connections and depend on a later
234 call to clean to get rid of the now unused objects. So the occasional
{\tt ;;
}
235 is a good idea in every synthesis script.
238 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
240 \subsection{The ``memory'' commands
}
242 \begin{frame
}[fragile
]{\subsecname}
243 In the RTL netlist, memory reads and writes are individual cells. This makes
244 consolidating the number of ports for a memory easier. The
{\tt memory
}
245 transforms memories to an implementation. Per default that is logic for address
246 decoders and registers. It also is a macro command that calls other commands:
248 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
249 # this merges registers into the memory read- and write cells.
252 # this collects all read and write cells for a memory and transforms them
253 # into one multi-port memory cell.
256 # this takes the multi-port memory cells and transforms it to address decoder
257 # logic and registers. This step is skipped if "memory" is called with -nomap.
262 Usually it is preferred to use architecture-specific RAM resources for memory.
265 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
266 memory -nomap; techmap -map my_memory_map.v; memory_map
270 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
1/
2}
271 \vbox to
0cm
{\includegraphics[width=
\linewidth,trim=
0cm
0cm
0cm -
10cm
]{PRESENTATION_ExSyn/memory_01.pdf
}\vss}
275 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/memory_01.ys
}
277 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/memory_01.v
}
281 \begin{frame
}[t, fragile
]{\subsecname{} -- Example
2/
2}
282 \vbox to
0cm
{\hfill\includegraphics[width=
7.5cm,trim=
0cm
0cm
0cm -
6cm
]{PRESENTATION_ExSyn/memory_02.pdf
}\vss}
286 \lstinputlisting[basicstyle=
\ttfamily\fontsize{6pt
}{8pt
}\selectfont, language=verilog
]{PRESENTATION_ExSyn/memory_02.v
}
288 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, frame=single
]{PRESENTATION_ExSyn/memory_02.ys
}
292 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
294 \subsection{The ``fsm'' commands
}
296 \begin{frame
}[fragile
]{\subsecname{}}
297 The
{\tt fsm
} command identifies, extracts, optimizes (re-encodes), and
298 re-synthesizes finite state machines. It again is a macro that calls
299 a series of other commands:
301 \begin{lstlisting
}[xleftmargin=
0.5cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont]
302 fsm_detect # unless got option -nodetect
309 fsm_expand # if got option -expand
310 opt_clean # if got option -expand
311 fsm_opt # if got option -expand
313 fsm_recode # unless got option -norecode
317 fsm_export # if got option -export
318 fsm_map # unless got option -nomap
322 \begin{frame
}{\subsecname{} -- details
}
323 Some details on the most importand commands from the
{\tt fsm
\_*
} group:
326 The
{\tt fsm
\_detect} command identifies FSM state registers and marks them
327 with the
{\tt (* fsm\_encoding = "auto" *)} attribute, if they do not have the
328 {\tt fsm
\_encoding} set already. Mark registers with
{\tt (* fsm\_encoding =
329 "none" *)} to disable FSM optimization for a register.
332 The
{\tt fsm
\_extract} command replaces the entire FSM (logic and state
333 registers) with a
{\tt \$fsm
} cell.
336 The commands
{\tt fsm
\_opt} and
{\tt fsm
\_recode} can be used to optimize the
340 Finally the
{\tt fsm
\_map} command can be used to convert the (optimized)
{\tt
341 \$fsm
} cell back to logic and registers.
344 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
346 \subsection{The ``techmap'' command
}
348 \begin{frame
}{\subsecname}
352 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
354 \subsection{The ``abc'' command
}
356 \begin{frame
}{\subsecname}
360 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
362 \subsection{Other special-purpose mapping commands
}
364 \begin{frame
}{\subsecname}
368 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%