2 \section{Introduction to Yosys
}
9 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
11 \subsection{Representations of (digital) Circuits
}
13 \begin{frame
}[t
]{\subsecname}
17 \item \alert<
1>
{Schematic Diagram
}
18 \item \alert<
2>
{Physical Layout
}
23 \item \alert<
3>
{Netlists
}
24 \item \alert<
4>
{Hardware Description Languages (HDLs)
}
28 \begin{block
}{Definition:
29 \only<
1>
{Schematic Diagram
}%
30 \only<
2>
{Physical Layout
}%
32 \only<
4>
{Hardware Description Languages (HDLs)
}}
34 Graphical representation of the circuit topology. Circuit elements
35 are represented by symbols and electrical connections by lines. The geometric
36 layout is for readability only.
39 The actual physical geometry of the device (PCB or ASIC manufacturing masks).
40 This is the final product of the design process.
43 A list of circuit elements and a list of connections. This is the raw circuit
47 Computer languages (like programming languages) that can be used to describe
48 circuits. HDLs are much more powerful in describing huge circuits than
54 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
57 \subsection{Levels of Abstraction for Digital Circuits
}
59 \begin{frame
}[t
]{\subsecname}
61 \item \alert<
1>
{System Level
}
62 \item \alert<
2>
{High Level
}
63 \item \alert<
3>
{Behavioral Level
}
64 \item \alert<
4>
{Register-Transfer Level (RTL)
}
65 \item \alert<
5>
{Logical Gate Level
}
66 \item \alert<
6>
{Physical Gate Level
}
67 \item \alert<
7>
{Switch Level
}
70 \begin{block
}{Definition:
71 \only<
1>
{System Level
}%
73 \only<
3>
{Behavioral Level
}%
74 \only<
4>
{Register-Transfer Level (RTL)
}%
75 \only<
5>
{Logical Gate Level
}%
76 \only<
6>
{Physical Gate Level
}%
77 \only<
7>
{Switch Level
}}
79 Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
82 Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
85 Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
88 List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
89 a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
92 Netlist of single-bit registers and basic logic gates (such as AND, OR,
93 NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
94 inputs and outputs for each register bit.
97 Netlist of cells that actually are available on the target architecture
98 (such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
99 area, power, and/or speed (static timing or number of logic levels).
102 Netlist of individual transistors.
107 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
109 \subsection{Digital Circuit Synthesis
}
111 \begin{frame
}{\subsecname}
112 Synthesis Tools (such as Yosys) can transform HDL code to circuits:
116 \begin{tikzpicture
}[scale=
0.8, every node/.style=
{transform shape
}]
117 \tikzstyle{lvl
} =
[draw, fill=MyBlue, rectangle, minimum height=
2em, minimum width=
15em
]
118 \node[lvl
] (sys)
{System Level
};
119 \node[lvl
] (hl)
[below of=sys
] {High Level
};
120 \node[lvl
] (beh)
[below of=hl
] {Behavioral Level
};
121 \node[lvl
] (rtl)
[below of=beh
] {Register-Transfer Level (RTL)
};
122 \node[lvl
] (lg)
[below of=rtl
] {Logical Gate Level
};
123 \node[lvl
] (pg)
[below of=lg
] {Physical Gate Level
};
124 \node[lvl
] (sw)
[below of=pg
] {Switch Level
};
126 \draw[dotted
] (sys.east) -- ++(
1,
0) coordinate (sysx);
127 \draw[dotted
] (hl.east) -- ++(
1,
0) coordinate (hlx);
128 \draw[dotted
] (beh.east) -- ++(
1,
0) coordinate (behx);
129 \draw[dotted
] (rtl.east) -- ++(
1,
0) coordinate (rtlx);
130 \draw[dotted
] (lg.east) -- ++(
1,
0) coordinate (lgx);
131 \draw[dotted
] (pg.east) -- ++(
1,
0) coordinate (pgx);
132 \draw[dotted
] (sw.east) -- ++(
1,
0) coordinate (swx);
134 \draw[gray,|->
] (sysx) -- node
[right
] {System Design
} (hlx);
135 \draw[|->|
] (hlx) -- node
[right
] {High Level Synthesis (HLS)
} (behx);
136 \draw[->|
] (behx) -- node
[right
] {Behavioral Synthesis
} (rtlx);
137 \draw[->|
] (rtlx) -- node
[right
] {RTL Synthesis
} (lgx);
138 \draw[->|
] (lgx) -- node
[right
] {Logic Synthesis
} (pgx);
139 \draw[gray,->|
] (pgx) -- node
[right
] {Cell Library
} (swx);
141 \draw[dotted
] (behx) -- ++(
4,
0) coordinate (a);
142 \draw[dotted
] (pgx) -- ++(
4,
0) coordinate (b);
143 \draw[|->|
] (a) -- node
[right
] {Yosys
} (b);
148 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
150 \subsection{What Yosys can and can't do
}
152 \begin{frame
}{\subsecname}
156 \item Read and process (most of) modern Verilog-
2005 code.
157 \item Perform all kinds of operations on netlist (RTL, Logic, Gate).
158 \item Perform logic optimizations and gate mapping with ABC
\footnote[frame
]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/
}}.
162 Things Yosys can't do:
164 \item Process high-level languages such as C/C++/SystemC.
165 \item Create physical layouts (place\&route).
169 A typical flow combines Yosys with with a low-level implementation tool, such
170 as Qflow
\footnote[frame
]{\url{http://opencircuitdesign.com/qflow/
}} for ASIC designs.
174 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
176 \subsection{Yosys Data- and Control-Flow
}
178 \begin{frame
}{\subsecname}
179 A (usually short) synthesis script controls Yosys.
181 This scripts contain three types of commands:
183 \item {\bf Frontends
}, that read input files (usually Verilog).
184 \item {\bf Passes
}, that perform transformations on the design in memory.
185 \item {\bf Backends
}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR,
\dots).
190 \begin{tikzpicture
}[scale=
0.6, every node/.style=
{transform shape
}]
191 \path (-
1.5,
3) coordinate (cursor);
192 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
193 \draw[fill=orange!
10] ($ (cursor) + (
1,-
3) $) rectangle node
[rotate=
90] {Frontend
} ++(
1,
3) coordinate (cursor);
194 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
195 \draw[fill=green!
10] ($ (cursor) + (
1,-
3) $) rectangle node
[rotate=
90] {Pass
} ++(
1,
3) coordinate (cursor);
196 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
197 \draw[fill=green!
10] ($ (cursor) + (
1,-
3) $) rectangle node
[rotate=
90] {Pass
} ++(
1,
3) coordinate (cursor);
198 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
199 \draw[fill=green!
10] ($ (cursor) + (
1,-
3) $) rectangle node
[rotate=
90] {Pass
} ++(
1,
3) coordinate (cursor);
200 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
201 \draw[fill=orange!
10] ($ (cursor) + (
1,-
3) $) rectangle node
[rotate=
90] {Backend
} ++(
1,
3) coordinate (cursor);
202 \draw[-latex
] ($ (cursor) + (
0,-
1.5) $) -- ++(
1,
0);
204 \path (-
3,-
0.5) coordinate (cursor);
205 \draw (cursor) -- node
[below
] {HDL
} ++(
3,
0) coordinate (cursor);
206 \draw[|-|
] (cursor) -- node
[below
] {Internal Format (RTLIL)
} ++(
8,
0) coordinate (cursor);
207 \draw (cursor) -- node
[below
] {Netlist
} ++(
3,
0);
209 \path (-
3,
3.5) coordinate (cursor);
210 \draw[-
] (cursor) -- node
[above
] {High-Level
} ++(
3,
0) coordinate (cursor);
211 \draw[-
] (cursor) -- ++(
8,
0) coordinate (cursor);
212 \draw[->
] (cursor) -- node
[above
] {Low-Level
} ++(
3,
0);
217 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
219 \subsection{Program Components and Data Formats
}
221 \begin{frame
}{\subsecname}
223 \begin{tikzpicture
}[scale=
0.6, every node/.style=
{transform shape
}]
224 \tikzstyle{process
} =
[draw, fill=green!
10, rectangle, minimum height=
3em, minimum width=
10em, node distance=
15em
]
225 \tikzstyle{data
} =
[draw, fill=blue!
10, ellipse, minimum height=
3em, minimum width=
7em, node distance=
15em
]
226 \node[process
] (vlog)
{Verilog Frontend
};
227 \node[process, dashed, fill=green!
5] (vhdl)
[right of=vlog
] {VHDL Frontend
};
228 \node[process
] (ilang)
[right of=vhdl
] {Other Frontends
};
229 \node[data
] (ast)
[below of=vlog, node distance=
5em, xshift=
7.5em
] {AST
};
230 \node[process
] (astfe)
[below of=ast, node distance=
5em
] {AST Frontend
};
231 \node[data
] (rtlil)
[below of=astfe, node distance=
5em, xshift=
7.5em
] {RTLIL
};
232 \node[process
] (pass)
[right of=rtlil, node distance=
5em, xshift=
7.5em
] {Passes
};
233 \node[process
] (vlbe)
[below of=rtlil, node distance=
7em, xshift=-
13em
] {Verilog Backend
};
234 \node[process
] (ilangbe)
[below of=rtlil, node distance=
7em, xshift=
0em
] {ILANG Backend
};
235 \node[process, fill=green!
5] (otherbe)
[below of=rtlil, node distance=
7em, xshift=+
13em
] {Other Backends
};
237 \draw[-latex
] (vlog) -- (ast);
238 \draw[-latex
] (vhdl) -- (ast);
239 \draw[-latex
] (ast) -- (astfe);
240 \draw[-latex
] (astfe) -- (rtlil);
241 \draw[-latex
] (ilang) -- (rtlil);
242 \draw[latex-latex
] (rtlil) -- (pass);
243 \draw[-latex
] (rtlil) -- (vlbe);
244 \draw[-latex
] (rtlil) -- (ilangbe);
245 \draw[-latex
] (rtlil) -- (otherbe);
250 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
252 \subsection{Example Project
}
254 \begin{frame
}[t
]{\subsecname}
255 The following slides cover an example project. This project contains three files:
257 \item A simple ASIC synthesis script
258 \item A digital design written in Verilog
259 \item A simple CMOS cell library
262 Direct link to the files: \\
\footnotesize
263 \url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro
}
266 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
268 \begin{frame
}[t
]{\subsecname{} -- Synthesis Script
}
270 \setbeamercolor{alerted text
}{fg=white,bg=red
}
272 \begin{minipage
}[t
]{6cm
}
274 {\color{YosysGreen
}\# read design
}\\
275 \boxalert<
1>
{read
\_verilog counter.v
}\\
276 \boxalert<
2>
{hierarchy -check -top counter
}
279 {\color{YosysGreen
}\# the high-level stuff
}\\
280 \boxalert<
3>
{proc
};
\boxalert<
4>
{opt
};
\boxalert<
5>
{fsm
};
\boxalert<
6>
{opt
};
\boxalert<
7>
{memory
};
\boxalert<
8>
{opt
}
283 {\color{YosysGreen
}\# mapping to internal cell library
}\\
284 \boxalert<
9>
{techmap
};
\boxalert<
10>
{opt
}
286 \begin{minipage
}[t
]{5cm
}
288 {\color{YosysGreen
}\# mapping flip-flops to mycells.lib
}\\
289 \boxalert<
11>
{dfflibmap -liberty mycells.lib
}
292 {\color{YosysGreen
}\# mapping logic to mycells.lib
}\\
293 \boxalert<
12>
{abc -liberty mycells.lib
}
296 {\color{YosysGreen
}\# cleanup
}\\
300 {\color{YosysGreen
}\# write synthesized design
}\\
301 \boxalert<
14>
{write
\_verilog synth.v
}
306 \begin{block
}{Command:
\tt
307 \only<
1>
{read
\_verilog counter.v
}%
308 \only<
2>
{hierarchy -check -top counter
}%
317 \only<
11>
{dfflibmap -liberty mycells.lib
}%
318 \only<
12>
{abc -liberty mycells.lib
}%
320 \only<
14>
{write
\_verilog synth.v
}}
322 Read Verilog source file and convert to internal representation.
325 Elaborate the design hierarchy. Should always be the first
326 command after reading the design. Can re-run AST front-end.
329 Convert ``processes'' (the internal representation of behavioral
330 Verilog code) into multiplexers and registers.
333 Perform some basic optimizations and cleanups.
336 Analyze and optimize finite state machines.
339 Perform some basic optimizations and cleanups.
342 Analyze memories and create circuits to implement them.
345 Perform some basic optimizations and cleanups.
348 Map coarse-grain RTL cells (adders, etc.) to fine-grain
349 logic gates (AND, OR, NOT, etc.).
352 Perform some basic optimizations and cleanups.
355 Map registers to available hardware flip-flops.
358 Map logic to available hardware gates.
361 Clean up the design (just the last step of
{\tt opt
}).
364 Write final synthesis result to output file.
370 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
372 \begin{frame
}[fragile
]{\subsecname{} -- Verilog Source:
\tt counter.v
}
373 \lstinputlisting[xleftmargin=
1cm, language=Verilog
]{PRESENTATION_Intro/counter.v
}
376 \begin{frame
}[fragile
]{\subsecname{} -- Cell Library:
\tt mycells.lib
}
379 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=liberty, lastline=
20]{PRESENTATION_Intro/mycells.lib
}
381 \lstinputlisting[basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=liberty, firstline=
21]{PRESENTATION_Intro/mycells.lib
}
385 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
387 \subsection{Running the Synthesis Script
}
389 \begin{frame
}[t, fragile
]{\subsecname{} -- Step
1/
4}
391 read_verilog counter.v
392 hierarchy -check -top counter
396 \includegraphics[width=
\linewidth,trim=
0 0cm
0 0cm
]{PRESENTATION_Intro/counter_00.pdf
}
399 \begin{frame
}[t, fragile
]{\subsecname{} -- Step
2/
4}
401 proc; opt; fsm; opt; memory; opt
405 \includegraphics[width=
\linewidth,trim=
0 0cm
0 0cm
]{PRESENTATION_Intro/counter_01.pdf
}
408 \begin{frame
}[t, fragile
]{\subsecname{} -- Step
3/
4}
414 \includegraphics[width=
\linewidth,trim=
0 0cm
0 2cm
]{PRESENTATION_Intro/counter_02.pdf
}
417 \begin{frame
}[t, fragile
]{\subsecname{} -- Step
4/
4}
419 dfflibmap -liberty mycells.lib
420 abc -liberty mycells.lib
425 \includegraphics[width=
10cm,trim=
0 0cm
0 0cm
]{PRESENTATION_Intro/counter_03.pdf
}
428 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
430 \subsection{The synth command
}
432 \begin{frame
}[fragile
]{\subsecname{}}
433 Yosys contains a default (recommended example) synthesis script in form of the
434 {\tt synth
} command. The following commands are executed by this synthesis command:
438 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
440 hierarchy -check
[-top <top>
]
455 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
470 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
472 \subsection{Yosys Commands
}
474 \begin{frame
}[fragile
]{\subsecname{} 1/
3 \hspace{0pt plus
1 filll
} (excerpt)
}
477 \item Use ``
{\tt help
}'' for a command list and ``
{\tt help
\it command
}'' for details.
478 \item Or run ``
{\tt yosys -H
}'' or ``
{\tt yosys -h
\it command
}''.
479 \item Or go to
\url{http://www.clifford.at/yosys/documentation.html
}.
483 Commands for design navigation and investigation:
484 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
485 cd # a shortcut for 'select -module <name>'
486 ls # list modules or objects in modules
487 dump # print parts of the design in ilang format
488 show # generate schematics using graphviz
489 select # modify and view the list of selected objects
493 Commands for executing scripts or entering interactive mode:
494 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
495 shell # enter interactive command mode
496 history # show last interactive commands
497 script # execute commands from script file
498 tcl # execute a TCL script file
502 \begin{frame
}[fragile
]{\subsecname{} 2/
3 \hspace{0pt plus
1 filll
} (excerpt)
}
503 Commands for reading and elaborating the design:
504 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
505 read_ilang # read modules from ilang file
506 read_verilog # read modules from Verilog file
507 hierarchy # check, expand and clean up design hierarchy
511 Commands for high-level synthesis:
512 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
513 proc # translate processes to netlists
514 fsm # extract and optimize finite state machines
515 memory # translate memories to basic cells
516 opt # perform simple optimizations
520 Commands for technology mapping:
521 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
522 techmap # generic technology mapper
523 abc # use ABC for technology mapping
524 dfflibmap # technology mapping of flip-flops
525 hilomap # technology mapping of constant hi- and/or lo-drivers
526 iopadmap # technology mapping of i/o pads (or buffers)
527 flatten # flatten design
531 \begin{frame
}[fragile
]{\subsecname{} 3/
3 \hspace{0pt plus
1 filll
} (excerpt)
}
532 Commands for writing the results:
533 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
534 write_blif # write design to BLIF file
535 write_btor # write design to BTOR file
536 write_edif # write design to EDIF netlist file
537 write_ilang # write design to ilang file
538 write_spice # write design to SPICE netlist file
539 write_verilog # write design to Verilog file
543 Script-Commands for standard synthesis tasks:
544 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
545 synth # generic synthesis script
546 synth_xilinx # synthesis for Xilinx FPGAs
550 Commands for model checking:
551 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=ys
]
552 sat # solve a SAT problem in the circuit
553 miter # automatically create a miter circuit
554 scc # detect strongly connected components (logic loops)
558 ... and many many more.
561 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
563 \subsection{More Verilog Examples
}
565 \begin{frame
}[fragile
]{\subsecname{} 1/
3}
566 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=Verilog
]
567 module detectprime(a, y);
575 for (i =
0; i <
32; i = i+
1) begin
577 for (j =
2; j*j <= i; j = j+
1)
588 \begin{frame
}[fragile
]{\subsecname{} 2/
3}
589 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=Verilog
]
590 module carryadd(a, b, y);
592 input
[WIDTH-
1:
0] a, b;
593 output
[WIDTH-
1:
0] y;
597 for (i =
0; i < WIDTH; i = i+
1) begin:STAGE
598 wire IN1 = a
[i
], IN2 = b
[i
];
601 assign C = IN1 & IN2, Y = IN1 ^ IN2;
603 assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE
[i-
1].C),
604 Y = IN1 ^ IN2 ^ STAGE
[i-
1].C;
612 \begin{frame
}[fragile
]{\subsecname{} 3/
3}
613 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{7pt
}{8.5pt
}\selectfont, language=Verilog
]
614 module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
616 parameter DEPTH =
16;
617 localparam ADDR_BITS = $clog2(DEPTH-
1);
619 input clk, wr_enable;
620 input
[ADDR_BITS-
1:
0] wr_addr;
621 input
[WIDTH-
1:
0] wr_data, rd_data;
622 output reg
[ADDR_BITS-
1:
0] rd_addr;
626 reg
[WIDTH-
1:
0] mem
[0:DEPTH-
1];
628 always @(posedge clk) begin
631 for (i =
0; i < DEPTH; i = i+
1)
632 if (mem
[i
] == rd_data) begin
637 mem
[wr_addr
] <= wr_data;
643 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
645 \subsection{Currently unsupported Verilog-
2005 language features
}
647 \begin{frame
}{\subsecname}
649 \item Tri-state logic
650 \item The wor/wand wire types (maybe for
0.5)
651 \item Latched logic (is synthesized as logic with feedback loops)
652 \item Some non-synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error (file a bug
report if you encounter this problem)
656 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
658 \subsection{Verification of Yosys
}
660 \begin{frame
}{\subsecname}
661 Continuously checking the correctness of Yosys and making sure that new features
662 do not break old ones is a high priority in Yosys.
665 Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
669 In addition to that, yosys comes with $
\approx\!
200$ test cases used in ``
{\tt make test
}''.
672 A debug build of Yosys also contains a lot of asserts and checks the integrity of
673 the internal state after each command.
676 \begin{frame
}[fragile
]{\subsecname{} -- VlogHammer
}
677 VlogHammer is a Verilog regression test suite developed to test the different
678 subsystems in Yosys by comparing them to each other and to the output created
679 by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
682 Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
683 simulation models, SAT models.
686 Thousands of auto-generated test cases containing code such as:
687 \begin{lstlisting
}[xleftmargin=
1cm, basicstyle=
\ttfamily\fontsize{8pt
}{10pt
}\selectfont, language=Verilog
]
688 assign y9 = $signed(((+$signed((^(
6'd2 ** a2))))<$unsigned($unsigned(((+a3))))));
689 assign y10 = (-((+((+
{2{(~^p13)
}})))^~(!
{{b5,b1,a0
},(a1&p12),(a4+a3)
})));
690 assign y11 = (~&(-
{(-
3'sd3),($unsigned($signed($unsigned(
{p0,b4,b1
}))))
}));
694 Some bugs in Yosys where found and fixed thanks to VlogHammer. Over
50 bugs in
695 the other tools used as external reference where found and reported so far.
698 \begin{frame
}{\subsecname{} -- yosys-bigsim
}
699 yosys-bigsim is a collection of real-world open-source Verilog designs and test
700 benches. yosys-bigsim compares the testbench outputs of simulations of the original
701 Verilog code and synthesis results.
704 The following designs are included in yosys-bigsim (excerpt):
706 \item {\tt openmsp430
} -- an MSP430 compatible
16 bit CPU
707 \item {\tt aes
\_5cycle\_2stage} -- an AES encryption core
708 \item {\tt softusb
\_navre} -- an AVR compatible
8 bit CPU
709 \item {\tt amber23
} -- an ARMv2 compatible
32 bit CPU
710 \item {\tt lm32
} -- another
32 bit CPU from Lattice Semiconductor
711 \item {\tt verilog-pong
} -- a hardware pong game with VGA output
712 \item {\tt elliptic
\_curve\_group} -- ECG point-add and point-scalar-mul core
713 \item {\tt reed
\_solomon\_decoder} -- a Reed-Solomon Error Correction Decoder
717 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
719 \subsection{Benefits of Open Source HDL Synthesis
}
721 \begin{frame
}{\subsecname}
723 \item Cost (also applies to ``free as in free beer'' solutions)
724 \item Availability and Reproducibility
725 \item Framework- and all-in-one-aspects
726 \item Educational Tool
731 Yosys is open source under the ISC license.
734 \begin{frame
}{\subsecname{} --
1/
3}
736 \item Cost (also applies to ``free as in free beer'' solutions):
\smallskip\par
737 Today the cost for a mask set in $
\unit[180]{nm
}$ technology is far less than
738 the cost for the design tools needed to design the mask layouts. Open Source
739 ASIC flows are an important enabler for ASIC-level Open Source Hardware.
742 \item Availability and Reproducibility:
\smallskip\par
743 If you are a researcher who is publishing, you want to use tools that everyone
744 else can also use. Even if most universities have access to all major
745 commercial tools, you usually do not have easy access to the version that was
746 used in a research project a couple of years ago. With Open Source tools you
747 can even release the source code of the tool you have used alongside your data.
751 \begin{frame
}{\subsecname{} --
2/
3}
753 \item Framework:
\smallskip\par
754 Yosys is not only a tool. It is a framework that can be used as basis for other
755 developments, so researchers and hackers alike do not need to re-invent the
756 basic functionality. Extensibility was one of Yosys' design goals.
759 \item All-in-one:
\smallskip\par
760 Because of the framework characteristics of Yosys, an increasing number of features
761 become available in one tool. Yosys not only can be used for circuit synthesis but
762 also for formal equivalence checking, SAT solving, and for circuit analysis, to
763 name just a few other application domains. With proprietary software one needs to
764 learn a new tool for each of these applications.
768 \begin{frame
}{\subsecname{} --
3/
3}
770 \item Educational Tool:
\smallskip\par
771 Proprietary synthesis tools are at times very secretive about their inner
772 workings. They often are ``black boxes''. Yosys is very open about its
773 internals and it is easy to observe the different steps of synthesis.
777 \begin{block
}{Yosys is licensed under the ISC license:
}
778 Permission to use, copy, modify, and/or distribute this software for any
779 purpose with or without fee is hereby granted, provided that the above
780 copyright notice and this permission notice appear in all copies.
784 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
786 \subsection{Typical Applications for Yosys
}
788 \begin{frame
}{\subsecname}
790 \item Synthesis of final production designs
791 \item Pre-production synthesis (trial runs before investing in other tools)
792 \item Conversion of full-featured Verilog to simple Verilog
793 \item Conversion of Verilog to other formats (BLIF, BTOR, etc)
794 \item Demonstrating synthesis algorithms (e.g. for educational purposes)
795 \item Framework for experimenting with new algorithms
796 \item Framework for building custom flows
\footnote[frame
]{Not limited to synthesis
797 but also formal verification, reverse engineering, ...
}
801 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
803 \subsection{Projects (that I know of) using Yosys
}
805 \begin{frame
}{\subsecname{} -- (
1/
2)
}
807 \item Ongoing PhD project on coarse grain synthesis \\
808 {\setlength{\parindent}{0.5cm
}\footnotesize
809 Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
810 Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
811 Architectures. In Jan Haase, editor,
\it Models, Methods, and Tools for Complex
812 Chip Design. Lecture Notes in Electrical Engineering. Volume
265,
2014, pp
813 201-
221. Springer,
2013.
}
816 \item I know several people that use Yosys simply as Verilog frontend for other
817 flows (using either the BLIF and BTOR backends).
820 \item I know some analog chip designers that use Yosys for small digital
821 control logic because it is simpler than setting up a commercial flow.
825 \begin{frame
}{\subsecname{} -- (
2/
2)
}
829 \smallskip \item Not much information on the website (
\url{http://efabless.com
}) yet.
830 \smallskip \item Very cheap
180nm prototyping process (partnering with various fabs)
831 \smallskip \item A semiconductor company, NOT an EDA company
832 \smallskip \item Web-based design environment
833 \smallskip \item HDL Synthesis using Yosys
834 \smallskip \item Custom place\&route tool
837 \item efabless is building an Open Source IC as reference design. \\
838 \hskip1cm (to be announced soon:
\url{http://www.openic.io
})
843 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
845 \subsection{Supported Platforms
}
847 \begin{frame
}{\subsecname}
849 \item Main development OS: Kubuntu
14.04
850 \item There is a PPA for ubuntu (not maintained by me)
851 \item Any current Debian-based system should work out of the box
852 \item When building on other Linux distributions:
854 \item Needs compiler with some C++
11 support
855 \item See README file for build instructions
856 \item Post to the subreddit if you get stuck
858 \item Ported to OS X (Darwin) and OpenBSD
859 \item Native win32 build with VisualStudio
860 \item Cross win32 build with MXE
864 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
866 \subsection{Other Open Source Tools
}
868 \begin{frame
}{\subsecname}
870 \item Icarus Verilog \\
871 \smallskip\hskip1cm{}Verilog Simulation (and also a good syntax checker) \\
872 \smallskip\hskip1cm{}\url{http://iverilog.icarus.com/
}
875 \item Qflow (incl. TimberWolf, qrouter and Magic) \\
876 \smallskip\hskip1cm{}A complete ASIC synthesis flow, using Yosys and ABC \\
877 \smallskip\hskip1cm{}\url{http://opencircuitdesign.com/qflow/
}
881 \smallskip\hskip1cm{}Logic optimization, technology mapping, and more \\
882 \smallskip\hskip1cm{}\url{http://www.eecs.berkeley.edu/~alanmi/abc/
}
886 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
888 \subsection{Yosys needs you
}
890 \begin{frame
}{\subsecname}
891 \dots as an active user:
893 \item Use Yosys for on your own projects
894 \item .. even if you are not using it as final synthesis tool
895 \item Join the discussion on the Subreddit
896 \item Report bugs and send in feature requests
900 \dots as a developer:
902 \item Use Yosys as environment for your (research) work
903 \item .. you might also want to look into ABC for logic-level stuff
904 \item Fork the project on github or create loadable plugins
905 \item We need a VHDL frontend or a good VHDL-to-Verilog converter
909 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
911 \subsection{Documentation, Downloads, Contacts
}
913 \begin{frame
}{\subsecname}
916 \smallskip\hskip1cm\url{http://www.clifford.at/yosys/
}
919 \item Manual, Command Reference, Application Notes: \\
920 \smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html
}
923 \item Instead of a mailing list we have a SubReddit: \\
924 \smallskip\hskip1cm\url{http://www.reddit.com/r/yosys/
}
927 \item Direct link to the source code: \\
928 \smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys
}
932 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
936 \begin{frame
}{\subsecname}
938 \item Yosys is a powerful tool and framework for Verilog synthesis.
939 \item It uses a command-based interface and can be controlled by scripts.
940 \item By combining existing commands and implementing new commands Yosys can
941 be used in a wide range of application far beyond simple synthesis.
953 \url{http://www.clifford.at/yosys/
}