manual/PRESENTATION_Prog/my_cmd.cc

   1 #include "kernel/yosys.h"
   2 #include "kernel/sigtools.h"
   3
   4 USING_YOSYS_NAMESPACE
   5 PRIVATE_NAMESPACE_BEGIN
   6
   7 struct MyPass : public Pass {
   8     MyPass() : Pass("my_cmd", "just a simple test") { }
   9     void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  10     {
  11         log("Arguments to my_cmd:\n");
  12         for (auto &arg : args)
  13             log("  %s\n", arg.c_str());
  14
  15         log("Modules in current design:\n");
  16         for (auto mod : design->modules())
  17             log("  %s (%zd wires, %zd cells)\n", log_id(mod),
  18                     GetSize(mod->wires()), GetSize(mod->cells()));
  19     }
  20 } MyPass;
  21
  22
  23 struct Test1Pass : public Pass {
  24     Test1Pass() : Pass("test1", "creating the absval module") { }
  25     void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
  26     {
  27         if (design->has("\\absval") != 0)
  28             log_error("A module with the name absval already exists!\n");
  29
  30         RTLIL::Module *module = design->addModule("\\absval");
  31         log("Name of this module: %s\n", log_id(module));
  32
  33         RTLIL::Wire *a = module->addWire("\\a", 4);
  34         a->port_input = true;
  35         a->port_id = 1;
  36
  37         RTLIL::Wire *y = module->addWire("\\y", 4);
  38         y->port_output = true;
  39         y->port_id = 2;
  40
  41         RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
  42         module->addNeg(NEW_ID, a, a_inv, true);
  43         module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
  44
  45         module->fixup_ports();
  46     }
  47 } Test1Pass;
  48
  49
  50 struct Test2Pass : public Pass {
  51     Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
  52     void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
  53     {
  54         if (design->selection_stack.back().empty())
  55             log_cmd_error("This command can't operator on an empty selection!\n");
  56
  57         RTLIL::Module *module = design->modules_.at("\\test");
  58
  59         RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
  60         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
  61
  62         SigMap sigmap(module);
  63         log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
  64                           sigmap(y) == sigmap(a)); // will print "1 1 1"
  65
  66         log("Mapped signal x: %s\n", log_signal(sigmap(x)));
  67
  68         log_header(design, "Doing important stuff!\n");
  69         log_push();
  70         for (int i = 0; i < 10; i++)
  71             log("Log message #%d.\n", i);
  72         log_pop();
  73     }
  74 } Test2Pass;
  75
  76 PRIVATE_NAMESPACE_END