Merge pull request #1571 from YosysHQ/eddie/fix_1570
[yosys.git] / manual / appnotes.sh
1 #!/bin/bash
2
3 set -ex
4 for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR
5 do
6 [ -f $job.ok -a $job.ok -nt $job.tex ] && continue
7 if [ -f $job/make.sh ]; then
8 cd $job
9 bash make.sh
10 cd ..
11 fi
12 old_md5=$([ -f $job.aux ] && md5sum < $job.aux || true)
13 while
14 pdflatex -shell-escape -halt-on-error $job.tex || exit
15 new_md5=$(md5sum < $job.aux)
16 [ "$old_md5" != "$new_md5" ]
17 do
18 old_md5="$new_md5"
19 done
20 touch $job.ok
21 done
22