1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command name instead of "yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
19 generate netlists for the specified cell library (using the liberty
20 file format). Without this option, ABC is used to optimize the netlist
21 but keeps using yosys's internal gate library. This option is ignored if
22 the -script option is also used.
25 pass this file with timing constraints to ABC
28 generate netlist using luts of (max) the specified width.
31 when this option is used, the temporary files created by this pass
32 are not removed. this is useful for debugging.
34 This pass does not operate on modules with unprocessed processes in it.
35 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
37 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
40 \section{add -- add objects to the design
}
42 \begin{lstlisting
}[numbers=left,frame=single
]
43 add <command>
[selection
]
45 This command adds objects to the design. It operates on all fully selected
46 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
49 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
51 Add a wire (input, inout, output port) with the given name and width. The
52 command will fail if the object exists already and has different properties
53 than the object to be created.
56 add -global_input <name> <width>
[selection
]
58 Like 'add -input', but also connect the signal between instances of the
62 \section{cd -- a shortcut for 'select -module <name>'
}
64 \begin{lstlisting
}[numbers=left,frame=single
]
67 This is just a shortcut for 'select -module <modname>'.
72 When no module with the specified name is found, but there is a cell
73 with the specified name in the current module, then this is equivialent
78 This is just a shortcut for 'select -clear'.
81 \section{clean -- remove unused cells and wires
}
83 \begin{lstlisting
}[numbers=left,frame=single
]
84 clean
[options
] [selection
]
86 This is identical to 'opt_clean', but less verbose.
88 When commands are seperated using the ';;' token, this command will be executed
91 When commands are seperated using the ';;;' token, this command will be executed
92 in -purge mode between the commands.
95 \section{design -- save, restore and reset current design
}
97 \begin{lstlisting
}[numbers=left,frame=single
]
100 Clear the current design.
105 Save the current design under the given name.
110 Reset the current design and load the design previously saved under the given
114 \section{dfflibmap -- technology mapping of flip-flops
}
115 \label{cmd:dfflibmap
}
116 \begin{lstlisting
}[numbers=left,frame=single
]
117 dfflibmap -liberty <file>
[selection
]
119 Map internal flip-flop cells to the flip-flop cells in the technology
120 library specified in the given liberty file.
122 This pass may add inverters as needed. Therefore it is recommended to
123 first run this pass and then map the logic paths to the target technology.
126 \section{dump -- print parts of the design in ilang format
}
128 \begin{lstlisting
}[numbers=left,frame=single
]
129 dump
[options
] [selection
]
131 Write the selected parts of the design to the console or specified file in
135 Write to the specified file.
138 \section{eval -- evaluate the circuit given an input
}
140 \begin{lstlisting
}[numbers=left,frame=single
]
141 eval
[options
] [selection
]
143 This command evaluates the value of a signal given the value of all required
146 -set <signal> <value>
147 set the specified signal to the specified value.
150 show the value for the specified signal. if no -show option is passed
151 then all output ports of the current module are used.
154 \section{extract -- find subcircuits and replace them with cells
}
156 \begin{lstlisting
}[numbers=left,frame=single
]
157 extract -map <map_file>
[options
] [selection
]
158 extract -mine <out_file>
[options
] [selection
]
160 This pass looks for subcircuits that are isomorphic to any of the modules
161 in the given map file and replaces them with instances of this modules. The
162 map file can be a verilog source file
(*.v) or an ilang file (*.il).
165 use the modules in this file as reference
168 print debug output while analyzing
171 also find instances with constant drivers. this may be much
172 slower than the normal operation.
175 normally builtin port swapping rules for internal cells are used per
176 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
177 when this option is used.
179 -compat <needle_type> <haystack_type>
180 Per default, the cells in the map file (needle) must have the
181 type as the cells in the active design (haystack). This option
182 can be used to register additional pairs of types that should
183 match. This option can be used multiple times.
185 -swap <needle_type> <port1>,<port2>[,...]
186 Register a set of swapable ports for a needle cell type.
187 This option can be used multiple times.
189 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
190 Register a valid permutation of swapable ports for a needle
191 cell type. This option can be used multiple times.
193 -cell_attr <attribute_name>
194 Attributes on cells with the given name must match.
196 -wire_attr <attribute_name>
197 Attributes on wires with the given name must match.
199 This pass does not operate on modules with uprocessed processes in it.
200 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
202 This pass can also be used for mining for frequent subcircuits. In this mode
203 the following options are to be used instead of the -map option.
206 mine for frequent subcircuits and write them to the given ilang file
208 -mine_cells_span <min> <max>
209 only mine for subcircuits with the specified number of cells
213 only mine for subcircuits with at least the specified number of matches
216 -mine_limit_matches_per_module <num>
217 when calculating the number of matches for a subcircuit, don't count
218 more than the specified number of matches per module
220 -mine_max_fanout <num>
221 don't consider internal signals with more than <num> connections
223 The modules in the map file may have the attribute 'extract_order' set to an
224 integer value. Then this value is used to determine the order in which the pass
225 tries to map the modules to the design (ascending, default value is 0).
227 See 'help techmap' for a pass that does the opposite thing.
230 \section{flatten -- flatten design}
232 \begin{lstlisting}[numbers=left,frame=single]
235 This pass flattens the design by replacing cells by their implementation. This
236 pass is very simmilar to the 'techmap' pass. The only difference is that this
237 pass is using the current design as mapping library.
240 \section{freduce -- perform functional reduction}
242 \begin{lstlisting}[numbers=left,frame=single]
243 freduce [options] [selection]
245 This pass performs functional reduction in the circuit. I.e. if two nodes are
246 equivialent, they are merged to one node and one of the redundant drivers is
250 do not issue an error when the analysis fails.
251 (usually beacause of logic loops in the design)
254 \section{fsm -- extract and optimize finite state machines}
256 \begin{lstlisting}[numbers=left,frame=single]
257 fsm [options] [selection]
259 This pass calls all the other fsm_* passes in a useful order. This performs
260 FSM extraction and optimiziation. It also calls opt_clean as needed:
262 fsm_detect unless got option -nodetect
269 fsm_expand if got option -expand
270 opt_clean if got option -expand
271 fsm_opt if got option -expand
273 fsm_recode unless got option -norecode
277 fsm_export if got option -export
278 fsm_map unless got option -nomap
282 -expand, -norecode, -export, -nomap
283 enable or disable passes as indicated above
286 -fm_set_fsm_file file
287 passed through to fsm_recode pass
290 \section{fsm\_detect -- finding FSMs in design}
291 \label{cmd:fsm_detect}
292 \begin{lstlisting}[numbers=left,frame=single]
293 fsm_detect [selection]
295 This pass detects finite state machines by identifying the state signal.
296 The state signal is then marked by setting the attribute 'fsm_encoding'
297 on the state signal to "auto".
299 Existing 'fsm_encoding' attributes are not changed by this pass.
301 Signals can be protected from being detected by this pass by setting the
302 'fsm_encoding' attribute to "none".
305 \section{fsm\_expand -- expand FSM cells by merging logic into it}
306 \label{cmd:fsm_expand}
307 \begin{lstlisting}[numbers=left,frame=single]
308 fsm_expand [selection]
310 The fsm_extract pass is conservative about the cells that belong to a finite
311 state machine. This pass can be used to merge additional auxiliary gates into
312 the finate state machine.
315 \section{fsm\_export -- exporting FSMs to KISS2 files}
316 \label{cmd:fsm_export}
317 \begin{lstlisting}[numbers=left,frame=single]
318 fsm_export [-noauto] [-o filename] [-origenc] [selection]
320 This pass creates a KISS2 file for every selected FSM. For FSMs with the
321 'fsm_export' attribute set, the attribute value is used as filename, otherwise
322 the module and cell name is used as filename. If the parameter '-o' is given,
323 the first exported FSM is written to the specified filename. This overwrites
324 the setting as specified with the 'fsm_export' attribute. All other FSMs are
325 exported to the default name as mentioned above.
328 only export FSMs that have the 'fsm_export' attribute set
331 filename of the first exported FSM
334 use binary state encoding as state names instead of s0, s1, ...
337 \section{fsm\_extract -- extracting FSMs in design}
338 \label{cmd:fsm_extract}
339 \begin{lstlisting}[numbers=left,frame=single]
340 fsm_extract [selection]
342 This pass operates on all signals marked as FSM state signals using the
343 'fsm_encoding' attribute. It consumes the logic that creates the state signal
344 and uses the state signal to generate control signal and replaces it with an
347 The generated FSM cell still generates the original state signal with its
348 original encoding. The 'fsm_opt' pass can be used in combination with the
349 'opt_clean' pass to eliminate this signal.
352 \section{fsm\_info -- print information on finite state machines}
354 \begin{lstlisting}[numbers=left,frame=single]
357 This pass dumps all internal information on FSM cells. It can be useful for
358 analyzing the synthesis process and is called automatically by the 'fsm'
359 pass so that this information is included in the synthesis log file.
362 \section{fsm\_map -- mapping FSMs to basic logic}
364 \begin{lstlisting}[numbers=left,frame=single]
367 This pass translates FSM cells to flip-flops and logic.
370 \section{fsm\_opt -- optimize finite state machines}
372 \begin{lstlisting}[numbers=left,frame=single]
375 This pass optimizes FSM cells. It detects which output signals are actually
376 not used and removes them from the FSM. This pass is usually used in
377 combination with the 'opt_clean' pass (see also 'help fsm').
380 \section{fsm\_recode -- recoding finite state machines}
381 \label{cmd:fsm_recode}
382 \begin{lstlisting}[numbers=left,frame=single]
383 fsm_recode [-encoding type] [-fm_set_fsm_file file] [selection]
385 This pass reassign the state encodings for FSM cells. At the moment only
386 one-hot encoding and binary encoding is supported. The option -encoding
387 can be used to specify the encoding scheme used for FSMs without the
388 `fsm_encoding' attribute (or with the attribute set to `auto'.
390 The option -fm_set_fsm_file can be used to generate a file containing the
391 mapping from old to new FSM encoding in form of Synopsys Formality set_fsm_*
395 \section{help -- display help messages}
397 \begin{lstlisting}[numbers=left,frame=single]
398 help ............. list all commands
399 help <command> ... print help message for given command
400 help -all ........ print complete command reference
403 \section{hierarchy -- check, expand and clean up design hierarchy}
404 \label{cmd:hierarchy}
405 \begin{lstlisting}[numbers=left,frame=single]
406 hierarchy [-check] [-top <module>]
407 hierarchy -generate <cell-types> <port-decls>
409 In parametric designs, a module might exists in serveral variations with
410 different parameter values. This pass looks at all modules in the current
411 design an re-runs the language frontends for the parametric modules as
415 also check the design hierarchy. this generates an error when
416 an unknown module is used as cell type.
419 per default this pass also converts positional arguments in cells
420 to arguments using port names. this option disables this behavior.
423 use the specified top module to built a design hierarchy. modules
424 outside this tree (unused modules) are removed.
426 In -generate mode this pass generates blackbox modules for the given cell
427 types (wildcards supported). For this the design is searched for cells that
428 match the given types and then the given port declarations are used to
429 determine the direction of the ports. The syntax for a port declaration is:
431 {i|o|io}[@<num>]:<portname>
433 Input ports are specified with the 'i' prefix, output ports with the 'o'
434 prefix and inout ports with the 'io' prefix. The optional <num> specifies
435 the position of the port in the parameter list (needed when instanciated
436 using positional arguments). When <num> is not specified, the <portname> can
437 also contain wildcard characters.
439 This pass ignores the current selection and always operates on all modules
440 in the current design.
443 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
445 \begin{lstlisting}[numbers=left,frame=single]
446 iopadmap [options] [selection]
448 Map module inputs/outputs to PAD cells from a library. This pass
449 can only map to very simple PAD cells. Use 'techmap' to further map
450 the resulting cells to more sophisticated PAD cells.
452 -inpad <celltype> <portname>[:<portname>]
453 Map module input ports to the given cell type with
454 the given port name. if a 2nd portname is given, the
455 signal is passed through the pad call, using the 2nd
458 -outpad <celltype> <portname>[:<portname>]
459 -inoutpad <celltype> <portname>[:<portname>]
460 Similar to -inpad, but for output and inout ports.
462 -widthparam <param_name>
463 Use the specified parameter name to set the port width.
465 -nameparam <param_name>
466 Use the specified parameter to set the port name.
469 \section{ls -- list modules or objects in modules}
471 \begin{lstlisting}[numbers=left,frame=single]
474 When no active module is selected, this prints a list of all module.
476 When an active module is selected, this prints a list of objects in the module.
479 \section{memory -- translate memories to basic cells}
481 \begin{lstlisting}[numbers=left,frame=single]
482 memory [-nomap] [selection]
484 This pass calls all the other memory_* passes in a useful order:
488 memory_map (skipped if called with -nomap)
490 This converts memories to word-wide DFFs and address decoders
491 or multiport memory blocks if called with the -nomap option.
494 \section{memory\_collect -- creating multi-port memory cells}
495 \label{cmd:memory_collect}
496 \begin{lstlisting}[numbers=left,frame=single]
497 memory_collect [selection]
499 This pass collects memories and memory ports and creates generic multiport
503 \section{memory\_dff -- merge input/output DFFs into memories}
504 \label{cmd:memory_dff}
505 \begin{lstlisting}[numbers=left,frame=single]
506 memory_dff [selection]
508 This pass detects DFFs at memory ports and merges them into the memory port.
509 I.e. it consumes an asynchronous memory port and the flip-flops at its
510 interface and yields a synchronous memory port.
513 \section{memory\_map -- translate multiport memories to basic cells}
514 \label{cmd:memory_map}
515 \begin{lstlisting}[numbers=left,frame=single]
516 memory_map [selection]
518 This pass converts multiport memory cells as generated by the memory_collect
519 pass to word-wide DFFs and address decoders.
522 \section{opt -- perform simple optimizations}
524 \begin{lstlisting}[numbers=left,frame=single]
527 This pass calls all the other opt_* passes in a useful order. This performs
528 a series of trivial optimizations and cleanups. This pass executes the other
529 passes in the following order:
541 while [changed design]
544 \section{opt\_clean -- remove unused cells and wires}
545 \label{cmd:opt_clean}
546 \begin{lstlisting}[numbers=left,frame=single]
547 opt_clean [options] [selection]
549 This pass identifies wires and cells that are unused and removes them. Other
550 passes often remove cells but leave the wires in the design or reconnect the
551 wires but leave the old cells in the design. This pass can be used to clean up
552 after the passes that do the actual work.
554 This pass only operates on completely selected modules without processes.
557 also remove internal nets if they have a public name
560 \section{opt\_const -- perform const folding}
561 \label{cmd:opt_const}
562 \begin{lstlisting}[numbers=left,frame=single]
563 opt_const [selection]
565 This pass performs const folding on internal cell types with constant inputs.
568 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
569 \label{cmd:opt_muxtree}
570 \begin{lstlisting}[numbers=left,frame=single]
571 opt_muxtree [selection]
573 This pass analyzes the control signals for the multiplexer trees in the design
574 and identifies inputs that can never be active. It then removes this dead
575 branches from the multiplexer trees.
577 This pass only operates on completely selected modules without processes.
580 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
581 \label{cmd:opt_reduce}
582 \begin{lstlisting}[numbers=left,frame=single]
583 opt_reduce [selection]
585 This pass performs two interlinked optimizations:
587 1. it consolidates trees of large AND gates or OR gates and eliminates
590 2. it identifies duplicated inputs to MUXes and replaces them with a single
591 input with the original control signals OR'ed together.
594 \section{opt\_rmdff -- remove DFFs with constant inputs}
595 \label{cmd:opt_rmdff}
596 \begin{lstlisting}[numbers=left,frame=single]
597 opt_rmdff [selection]
599 This pass identifies flip-flops with constant inputs and replaces them with
603 \section{opt\_share -- consolidate identical cells}
604 \label{cmd:opt_share}
605 \begin{lstlisting}[numbers=left,frame=single]
606 opt_share [-nomux] [selection]
608 This pass identifies cells with identical type and input signals. Such cells
609 are then merged to one cell.
612 Do not merge MUX cells.
615 \section{proc -- translate processes to netlists}
617 \begin{lstlisting}[numbers=left,frame=single]
618 proc [options] [selection]
620 This pass calls all the other proc_* passes in the most common order.
630 This replaces the processes in the design with multiplexers and flip-flops.
632 The following options are supported:
634 -global_arst [!]<netname>
635 This option is passed through to proc_arst.
638 \section{proc\_arst -- detect asynchronous resets}
639 \label{cmd:proc_arst}
640 \begin{lstlisting}[numbers=left,frame=single]
641 proc_arst [-global_arst [!]<netname>] [selection]
643 This pass identifies asynchronous resets in the processes and converts them
644 to a different internal representation that is suitable for generating
645 flip-flop cells with asynchronous resets.
647 -global_arst [!]<netname>
648 In modules that have a net with the given name, use this net as async
649 reset for registers that have been assign initial values in their
650 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
651 active low reset signals. Note: the frontend stores the default value
652 in the 'init' attribute on the net.
655 \section{proc\_clean -- remove empty parts of processes}
656 \label{cmd:proc_clean}
657 \begin{lstlisting}[numbers=left,frame=single]
658 proc_clean [selection]
660 This pass removes empty parts of processes and ultimately removes a process
661 if it contains only empty structures.
664 \section{proc\_dff -- extract flip-flops from processes}
666 \begin{lstlisting}[numbers=left,frame=single]
669 This pass identifies flip-flops in the processes and converts them to
670 d-type flip-flop cells.
673 \section{proc\_init -- convert initial block to init attributes}
674 \label{cmd:proc_init}
675 \begin{lstlisting}[numbers=left,frame=single]
676 proc_init [selection]
678 This pass extracts the 'init' actions from processes (generated from verilog
679 'initial' blocks) and sets the initial value to the 'init' attribute on the
683 \section{proc\_mux -- convert decision trees to multiplexers}
685 \begin{lstlisting}[numbers=left,frame=single]
688 This pass converts the decision trees in processes (originating from if-else
689 and case statements) to trees of multiplexer cells.
692 \section{proc\_rmdead -- eliminate dead trees in decision trees}
693 \label{cmd:proc_rmdead}
694 \begin{lstlisting}[numbers=left,frame=single]
695 proc_rmdead [selection]
697 This pass identifies unreachable branches in decision trees and removes them.
700 \section{read\_ilang -- read modules from ilang file}
701 \label{cmd:read_ilang}
702 \begin{lstlisting}[numbers=left,frame=single]
703 read_ilang [filename]
705 Load modules from an ilang file to the current design. (ilang is a text
706 representation of a design in yosys's internal format.)
709 \section{read\_verilog -- read modules from verilog file}
710 \label{cmd:read_verilog}
711 \begin{lstlisting}[numbers=left,frame=single]
712 read_verilog [filename]
714 Load modules from a verilog file to the current design. A large subset of
715 Verilog-2005 is supported.
718 dump abstract syntax tree (before simplification)
721 dump abstract syntax tree (after simplification)
724 dump ast as verilog code (after simplification)
727 enable parser debug output
730 usually latches are synthesized into logic loops
731 this option prohibits this and sets the output to 'x'
732 in what would be the latches hold condition
734 this behavior can also be achieved by setting the
735 'nolatches' attribute on the respective module or
739 under certain conditions memories are converted to registers
740 early during simplification to ensure correct handling of
741 complex corner cases. this option disables this behavior.
743 this can also be achieved by setting the 'nomem2reg'
744 attribute on the respective module or register.
747 always convert memories to registers. this can also be
748 achieved by setting the 'mem2reg' attribute on the respective
752 dump verilog code after pre-processor
755 do not run the pre-processor
758 only create empty blackbox modules
761 don't perform basic optimizations (such as const folding) in the
762 high-level front-end.
765 define the preprocessor symbol 'name' and set its optional value
769 add 'dir' to the directories which are used when searching include
773 \section{rename -- rename object in the design}
775 \begin{lstlisting}[numbers=left,frame=single]
776 rename old_name new_name
778 Rename the specified object. Note that selection patterns are not supported
782 rename -enumerate [selection]
784 Assign short auto-generated names to all selected wires and cells with private
788 \section{sat -- solve a SAT problem in the circuit}
790 \begin{lstlisting}[numbers=left,frame=single]
791 sat [options] [selection]
793 This command solves a SAT problem defined over the currently selected circuit
794 and additional constraints passed as parameters.
797 show all solutions to the problem (this can grow exponentially, use
798 -max <N> instead to get <N> solutions)
801 like -all, but limit number of solutions to <N>
803 -set <signal> <value>
804 set the specified signal to the specified value.
807 show the model for the specified signal. if no -show option is
808 passed then a set of signals to be shown is automatically selected.
811 ignore all solutions that involve a division by zero
813 The following options can be used to set up a sequential problem:
816 set up a sequential problem with <N> time steps. The steps will
817 be numbered from 1 to N.
819 -set-at <N> <signal> <value>
820 -unset-at <N> <signal>
821 set or unset the specified signal to the specified value in the
822 given timestep. this has priority over a -set for the same signal.
824 The following additional options can be used to set up a proof. If also -seq
825 is passed, a temporal induction proof is performed.
827 -prove <signal> <value>
828 Attempt to proof that <signal> is always <value>. In a temporal
829 induction proof it is proven that the condition holds forever after
830 the number of time steps passed using -seq.
833 Set a maximum length for the induction.
836 Maximum number of seconds a single SAT instance may take.
839 Return an error and stop the synthesis script if the proof fails.
842 Like -verify but do not return an error for timeouts.
845 \section{scatter -- add additional intermediate nets}
847 \begin{lstlisting}[numbers=left,frame=single]
850 This command adds additional intermediate nets on all cell ports. This is used
851 for testing the correct use of the SigMap helper in passes. If you don't know
852 what this means: don't worry -- you only need this pass when testing your own
855 Use the opt_clean command to get rid of the additional nets.
858 \section{scc -- detect strongly connected components (logic loops)}
860 \begin{lstlisting}[numbers=left,frame=single]
861 scc [options] [selection]
863 This command identifies strongly connected components (aka logic loops) in the
867 limit to loops not longer than the specified number of cells. This can
868 e.g. be useful in identifying local loops in a module that turns out
869 to be one gigantic SCC.
872 Usually this command only considers internal non-memory cells. With
873 this option set, all cells are considered. For unkown cells all ports
874 are assumed to be bidirectional 'inout' ports.
876 -set_attr <name> <value>
877 -set_cell_attr <name> <value>
878 -set_wire_attr <name> <value>
879 set the specified attribute on all cells and/or wires that are part of
880 a logic loop. the special token {} in the value is replaced with a
881 unique identifier for the logic loop.
884 replace the current selection with a selection of all cells and wires
885 that are part of a found logic loop
888 \section{script -- execute commands from script file}
890 \begin{lstlisting}[numbers=left,frame=single]
893 This command executes the yosys commands in the specified file.
896 \section{select -- modify and view the list of selected objects}
898 \begin{lstlisting}[numbers=left,frame=single]
899 select [ -add | -del | -set <name> ] <selection>
900 select [ -list | -write <filename> | -count | -clear ]
901 select -module <modname>
903 Most commands use the list of currently selected objects to determine which part
904 of the design to operate on. This command can be used to modify and view this
905 list of selected objects.
907 Note that many commands support an optional [selection] argument that can be
908 used to override the global selection for the command. The syntax of this
909 optional argument is identical to the syntax of the <selection> argument
913 add or remove the given objects to the current selection.
914 without this options the current selection is replaced.
917 do not modify the current selection. instead save the new selection
918 under the given name (see @<name> below).
921 list all objects in the current selection
924 like -list but write the output to the specified file
927 count all objects in the current selection
930 clear the current selection. this effectively selects the
934 limit the current scope to the specified module.
935 the difference between this and simply selecting the module
936 is that all object names are interpreted relative to this
937 module after this command until the selection is cleared again.
939 When this command is called without an argument, the current selection
940 is displayed in a compact form (i.e. only the module name when a whole module
943 The <selection> argument itself is a series of commands for a simple stack
944 machine. Each element on the stack represents a set of selected objects.
945 After this commands have been executed, the union of all remaining sets
946 on the stack is computed and used as selection for the command.
948 Pushing (selecting) object when not in -module mode:
951 select the specified module(s)
953 <mod_pattern>/<obj_pattern>
954 select the specified object(s) from the module(s)
956 Pushing (selecting) object when in -module mode:
959 select the specified object(s) from the current module
961 A <mod_pattern> can be a module name or wildcard expression (*, ?, [..])
962 matching module names.
964 An <obj_pattern> can be an object name, wildcard expression, or one of
968 all wires with a name matching the given wildcard pattern
971 all memories with a name matching the given pattern
974 all cells with a name matching the given pattern
977 all cells with a type matching the given pattern
980 all processes with a name matching the given pattern
983 all objects with an attribute name matching the given pattern
985 a:<pattern>=<pattern>
986 all objects with a matching attribute name-value-pair
989 all objects with a name matching the given pattern
990 (i.e. 'n:' is optional as it is the default matching rule)
993 push the selection saved prior with 'select -set <name> ...'
995 The following actions can be performed on the top sets on the stack:
998 push a copy of the current selection to the stack
1001 replace the stack with a union of all elements on it
1004 replace top set with its invert
1007 replace the two top sets on the stack with their union
1010 replace the two top sets on the stack with their intersection
1013 pop the top set from the stack and subtract it from the new top
1015 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1016 expand top set <num1> num times according to the specified rules.
1017 (i.e. select all cells connected to selected wires and select all
1018 wires connected to selected cells) The rules specify which cell
1019 ports to use for this. the syntax for a rule is a '-' for exclusion
1020 and a '+' for inclusion, followed by an optional comma seperated
1021 list of cell types followed by an optional comma separated list of
1022 cell ports in square brackets. a rule can also be just a cell or wire
1023 name that limits the expansion (is included but does not go beyond).
1024 select at most <num2> objects. a warning message is printed when this
1025 limit is reached. When '*' is used instead of <num1> then the process
1026 is repeated until no further object are selected.
1028 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1029 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1030 simmilar to %x, but only select input (%ci) or output cones (%co)
1032 Example: the following command selects all wires that are connected to a
1033 'GATE' input of a 'SWITCH' cell:
1035 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
1038 \section{shell -- enter interactive command mode}
1040 \begin{lstlisting}[numbers=left,frame=single]
1043 This command enters the interactive command mode. This can be useful
1044 in a script to interrupt the script at a certain point and allow for
1045 interactive inspection or manual synthesis of the design at this point.
1047 The command prompt of the interactive shell indicates the current
1048 selection (see 'help select'):
1051 the entire design is selected
1054 only part of the design is selected
1057 the entire module 'modname' is selected using 'select -module modname'
1060 only part of current module 'modname' is selected
1062 When in interactive shell, some errors (e.g. invalid command arguments)
1063 do not terminate yosys but return to the command prompt.
1065 This command is the default action if nothing else has been specified
1066 on the command line.
1068 Press Ctrl-D or type 'exit' to leave the interactive shell.
1071 \section{show -- generate schematics using graphviz}
1073 \begin{lstlisting}[numbers=left,frame=single]
1074 show [options] [selection]
1076 Create a graphviz DOT file for the selected part of the design and compile it
1077 to a graphics file (usually SVG or PostScript).
1080 Run the specified command with the graphics file as parameter.
1083 Generate a graphics file in the specified format.
1084 Usually <format> is 'svg' or 'ps'.
1086 -lib <verilog_or_ilang_file>
1087 Use the specified library file for determining whether cell ports are
1088 inputs or outputs. This option can be used multiple times to specify
1089 more than one library.
1092 generate <prefix>.* instead of ~/.yosys_show.*
1094 -color <color> <wire>
1095 assign the specified color to the specified wire. The object can be
1096 a single selection wildcard expressions or a saved set of objects in
1097 the @<name> syntax (see "help select" for details).
1100 Randomly assign colors to the wires. The integer argument is the seed
1101 for the random number generator. Change the seed value if the colored
1102 graph still is ambigous. A seed of zero deactivates the coloring.
1105 annotate busses with a label indicating the width of the bus.
1108 stretch the graph so all inputs are on the left side and all outputs
1109 (including inout ports) are on the right side.
1111 When no <format> is specified, SVG is used. When no <format> and <viewer> is
1112 specified, 'yosys-svgviewer' is used to display the schematic.
1114 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
1115 unless another prefix is specified using -prefix <prefix>.
1118 \section{splitnets -- split up multi-bit nets}
1119 \label{cmd:splitnets}
1120 \begin{lstlisting}[numbers=left,frame=single]
1121 splitnets [options] [selection]
1123 This command splits multi-bit nets into single-bit nets.
1125 -format char1[char2]
1126 the first char is inserted between the net name and the bit index, the
1127 second char is appended to the netname. e.g. -format () creates net
1128 names like 'mysignal(42)'. the default is '[]'.
1131 also split module ports. per default only internal signals are split.
1134 \section{submod -- moving part of a module to a new submodule}
1136 \begin{lstlisting}[numbers=left,frame=single]
1139 This pass identifies all cells with the 'submod' attribute and moves them to
1140 a newly created module. The value of the attribute is used as name for the
1141 cell that replaces the group of cells with the same attribute value.
1143 This pass can be used to create a design hierarchy in flat design. This can
1144 be useful for analyzing or reverse-engineering a design.
1146 This pass only operates on completely selected modules with no processes
1150 submod -name <name> [selection]
1152 As above, but don't use the 'submod' attribute but instead use the selection.
1153 Only objects from one module might be selected. The value of the -name option
1154 is used as the value of the 'submod' attribute above.
1157 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
1158 \label{cmd:synth_xilinx}
1159 \begin{lstlisting}[numbers=left,frame=single]
1160 synth_xilinx [options]
1162 This command runs synthesis for Xilinx FPGAs. This command does not operate on
1163 partly selected designs.
1166 use the specified module as top module (default='top')
1169 select architecture. the following architectures are supported:
1170 spartan6 (default), artix7, kintex7, virtex7, zynq7000
1171 (this parameter is not used by the command at the moment)
1174 write the design to the specified edif file. writing of an output file
1175 is omitted if this parameter is not specified.
1177 -run <from_label>:<to_label>
1178 only run the commands between the labels (see below). an empty
1179 from label is synonymous to 'begin', and empty to label is
1180 synonymous to the end of the command list.
1183 The following commands are executed by this synthesis command:
1186 hierarchy -check -top <top>
1205 techmap -map <share_dir>/xilinx/cells.v
1209 select -set xilinx_clocks <top>/t:FDRE %x:+FDRE[C] <top>/t:FDRE %d
1210 iopadmap -inpad BUFGP O:I @xilinx_clocks
1213 select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %x:+BUFGP[I] %d
1214 iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks
1217 write_edif -top <top> synth.edif
1220 \section{tcl -- execute a TCL script file}
1222 \begin{lstlisting}[numbers=left,frame=single]
1225 This command executes the tcl commands in the specified file.
1226 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
1228 The tcl command 'yosys -import' can be used to import all yosys
1229 commands directly as tcl commands to the tcl shell. The yosys
1230 command 'proc' is wrapped using the tcl command 'procs' in order
1231 to avoid a name collision with the tcl builting command 'proc'.
1234 \section{techmap -- simple technology mapper}
1236 \begin{lstlisting}[numbers=left,frame=single]
1237 techmap [-map filename] [selection]
1239 This pass implements a very simple technology mapper that replaces cells in
1240 the design with implementations given in form of a verilog or ilang source
1244 the library of cell implementations to be used.
1245 without this parameter a builtin library is used that
1246 transforms the internal RTL cells to the internal gate
1249 When a module in the map file has the 'techmap_celltype' attribute set, it will
1250 match cells with a type that match the text value of this attribute.
1252 All wires in the modules from the map file matching the pattern _TECHMAP_*
1253 or *._TECHMAP_* are special wires that are used to pass instructions from
1254 the mapping module to the techmap command. At the moment the following spoecial
1255 wires are supported:
1258 When this wire is set to a non-zero constant value, techmap will not
1259 use this module and instead try the next module with a matching
1260 'techmap_celltype' attribute.
1262 When such a wire exists but does not have a constant value after all
1263 _TECHMAP_DO_* commands have been executed, an error is generated.
1266 This wires are evaluated in alphabetical order. The constant text value
1267 of this wire is a yosys command (or sequence of commands) that is run
1268 by techmap on the module. A common use case is to run 'proc' on modules
1269 that are written using always-statements.
1271 When such a wire has a non-constant value at the time it is to be
1272 evaluated, an error is produced. That means it is possible for such a
1273 wire to start out as non-constant and evaluate to a constant value
1274 during processing of other _TECHMAP_DO_* commands.
1276 When a module in the map file has a parameter where the according cell in the
1277 design has a port, the module from the map file is only used if the port in
1278 the design is connected to a constant value. The parameter is then set to the
1281 See 'help extract' for a pass that does the opposite thing.
1283 See 'help flatten' for a pass that does flatten the design (which is
1284 esentially techmap but using the design itself as map library).
1287 \section{write\_autotest -- generate simple test benches}
1288 \label{cmd:write_autotest}
1289 \begin{lstlisting}[numbers=left,frame=single]
1290 write_autotest [filename]
1292 Automatically create primitive verilog test benches for all modules in the
1293 design. The generated testbenches toggle the input pins of the module in
1294 a semi-random manner and dumps the resulting output signals.
1296 This can be used to check the synthesis results for simple circuits by
1297 comparing the testbench output for the input files and the synthesis results.
1299 The backend automatically detects clock signals. Additionally a signal can
1300 be forced to be interpreted as clock signal by setting the attribute
1301 'gentb_clock' on the signal.
1303 The attribute 'gentb_constant' can be used to force a signal to a constant
1304 value after initialization. This can e.g. be used to force a reset signal
1305 low in order to explore more inner states in a state machine.
1308 \section{write\_blif -- write design to BLIF file}
1309 \label{cmd:write_blif}
1310 \begin{lstlisting}[numbers=left,frame=single]
1311 write_blif [options] [filename]
1313 Write the current design to an BLIF file.
1316 set the specified module as design top module
1318 -buf <cell-type> <in-port> <out-port>
1319 use cells of type <cell-type> with the specified port names for buffers
1321 -true <cell-type> <out-port>
1322 -false <cell-type> <out-port>
1323 use the specified cell types to drive nets that are constant 1 or 0
1325 The following options can be usefull when the generated file is not going to be
1326 read by a BLIF parser but a custom tool. It is recommended to not name the output
1327 file *.blif when any of this options is used.
1330 do not translate Yosys's internal gates to generic BLIF logic
1331 functions. Instead create .subckt lines for all cells.
1334 do not generate buffers for connected wires. instead use the
1335 non-standard .conn statement.
1338 do not write definitions for the $true and $false wires.
1341 \section{write\_edif -- write design to EDIF netlist file}
1342 \label{cmd:write_edif}
1343 \begin{lstlisting}[numbers=left,frame=single]
1344 write_edif [options] [filename]
1346 Write the current design to an EDIF netlist file.
1349 set the specified module as design top module
1351 Unfortunately there are different "flavors" of the EDIF file format. This
1352 command generates EDIF files for the Xilinx place&route tools. It might be
1353 necessary to make small modifications to this command when a different tool
1357 \section{write\_ilang -- write design to ilang file}
1358 \label{cmd:write_ilang}
1359 \begin{lstlisting}[numbers=left,frame=single]
1360 write_ilang [filename]
1362 Write the current design to an 'ilang' file. (ilang is a text representation
1363 of a design in yosys's internal format.)
1366 only write selected parts of the design.
1369 \section{write\_intersynth -- write design to InterSynth netlist file}
1370 \label{cmd:write_intersynth}
1371 \begin{lstlisting}[numbers=left,frame=single]
1372 write_intersynth [options] [filename]
1374 Write the current design to an 'intersynth' netlist file. InterSynth is
1375 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
1378 do not generate celltypes and conntypes commands. i.e. just output
1379 the netlists. this is used for postsilicon synthesis.
1381 -lib <verilog_or_ilang_file>
1382 Use the specified library file for determining whether cell ports are
1383 inputs or outputs. This option can be used multiple times to specify
1384 more than one library.
1387 only write selected modules. modules must be selected entirely or
1390 http://www.clifford.at/intersynth/
1393 \section{write\_spice -- write design to SPICE netlist file}
1394 \label{cmd:write_spice}
1395 \begin{lstlisting}[numbers=left,frame=single]
1396 write_spice [options] [filename]
1398 Write the current design to an SPICE netlist file.
1401 generate multi-bit ports in MSB first order
1402 (default is LSB first)
1405 set the net name for constant 0 (default: Vss)
1408 set the net name for constant 1 (default: Vdd)
1411 prefix for not-connected nets (default: _NC)
1414 set the specified module as design top module
1417 \section{write\_verilog -- write design to verilog file}
1418 \label{cmd:write_verilog}
1419 \begin{lstlisting}[numbers=left,frame=single]
1420 write_verilog [options] [filename]
1422 Write the current design to a verilog file.
1425 without this option all internal object names (the ones with a dollar
1426 instead of a backslash prefix) are changed to short names in the
1427 format '_<number>_'.
1430 with this option no attributes are included in the output
1433 with this option attributes are included as comments in the output
1436 without this option all internal cells are converted to verilog
1440 usually modules with the 'blackbox' attribute are ignored. with
1441 this option set only the modules with the 'blackbox' attribute
1442 are written to the output file.
1445 only write selected modules. modules must be selected entirely or