1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interpreted as the command string to be passed to ABC. The
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
29 for -liberty with -constr:
30 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
31 &nf
{D
}; &put; buffer; upsize
{D
}; dnsize
{D
}; stime -p
33 for -lut/-luts (only one LUT size):
34 strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2;
37 for -lut/-luts (different LUT sizes):
38 strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2
41 strash; ifraig; scorr; dc2; dretime; strash; dch -f;
45 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
49 use different default scripts that are slightly faster (at the cost
52 for -liberty without -constr:
53 strash; dretime; map
{D
}
55 for -liberty with -constr:
56 strash; dretime; map
{D
}; buffer; upsize
{D
}; dnsize
{D
};
63 strash; dretime; cover -I
{I
} -P
{P
}
69 generate netlists for the specified cell library (using the liberty
73 pass this file with timing constraints to ABC. use with -liberty.
75 a constr file contains two lines:
76 set_driving_cell <cell_name>
77 set_load <floating_point_number>
79 the set_driving_cell statement defines which cell type is assumed to
80 drive the primary inputs and the set_load statement sets the load in
81 femtofarads for each primary output.
84 set delay target. the string
{D
} in the default scripts above is
85 replaced by this option when used, and an empty string otherwise.
86 this also replaces 'dretime' with 'dretime; retime -o
{D
}' in the
87 default scripts above.
90 maximum number of SOP inputs.
91 (replaces
{I
} in the default scripts above)
94 maximum number of SOP products.
95 (replaces
{P
} in the default scripts above)
98 maximum number of LUT inputs shared.
99 (replaces
{S
} in the default scripts above, default: -S
1)
102 generate netlist using luts of (max) the specified width.
105 generate netlist using luts of (max) the specified width <w2>. All
106 luts with width <= <w1> have constant cost. for luts larger than <w1>
107 the area cost doubles with each additional input bit. the delay cost
108 is still constant for all lut widths.
110 -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
111 generate netlist using luts. Use the specified costs for luts with
1,
115 map to sum-of-product cells and inverters
118 Map to the specified list of gate types. Supported gates types are:
119 AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.
120 (The NOT gate is always added to this list automatically.)
122 The following aliases can be used to reference common sets of gate types:
123 simple: AND OR XOR MUX
125 cmos3: NAND NOR AOI3 OAI3
126 cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4
127 gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT
128 aig: AND NAND OR NOR ANDNOT ORNOT
130 Prefix a gate type with a '-' to remove it from the list. For example
131 the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.
134 also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
135 clock domains are automatically partitioned in clock domains and each
136 domain is passed through ABC independently.
138 -clk
[!
]<clock-signal-name>
[,
[!
]<enable-signal-name>
]
139 use only the specified clock domain. this is like -dff, but only FF
140 cells that belong to the specified clock domain are used.
143 set the "keep" attribute on flip-flop output wires. (and thus preserve
144 them, for example for equivalence checking.)
147 when this option is used, the temporary files created by this pass
148 are not removed. this is useful for debugging.
151 print the temp dir name in log. usually this is suppressed so that the
152 command output is identical across runs.
155 set a 'abcgroup' attribute on all objects created by ABC. The value of
156 this attribute is a unique integer for each ABC process started. This
157 is useful for debugging the partitioning of clock domains.
159 When neither -liberty nor -lut is used, the Yosys standard cell library is
160 loaded into ABC before the ABC script is executed.
162 Note that this is a logic optimization pass within Yosys that is calling ABC
163 internally. This is not going to "run ABC on your design". It will instead run
164 ABC on logic snippets extracted from your design. You will not get any useful
165 output when passing an ABC script that writes a file. Instead write your full
166 design as BLIF file with write_blif and the load that into ABC externally if
167 you want to use ABC to convert your design into another format.
169 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
172 \section{add -- add objects to the design
}
174 \begin{lstlisting
}[numbers=left,frame=single
]
175 add <command>
[selection
]
177 This command adds objects to the design. It operates on all fully selected
178 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
181 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
183 Add a wire (input, inout, output port) with the given name and width. The
184 command will fail if the object exists already and has different properties
185 than the object to be created.
188 add -global_input <name> <width>
[selection
]
190 Like 'add -input', but also connect the signal between instances of the
194 \section{aigmap -- map logic to and-inverter-graph circuit
}
196 \begin{lstlisting
}[numbers=left,frame=single
]
197 aigmap
[options
] [selection
]
199 Replace all logic cells with circuits made of only $_AND_ and
203 Enable creation of $_NAND_ cells
206 \section{alumacc -- extract ALU and MACC cells
}
208 \begin{lstlisting
}[numbers=left,frame=single
]
211 This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
215 \section{assertpmux -- convert internal signals to module ports
}
216 \label{cmd:assertpmux
}
217 \begin{lstlisting
}[numbers=left,frame=single
]
218 assertpmux
[options
] [selection
]
220 This command adds asserts to the design that assert that all parallel muxes
221 ($pmux cells) have a maximum of one of their inputs enable at any time.
224 do not enforce the pmux condition during the init state
227 usually the $pmux condition is only checked when the $pmux output
228 is used be the mux tree it drives. this option will deactivate this
229 additional constrained and check the $pmux condition always.
232 \section{async2sync -- convert async FF inputs to sync circuits
}
233 \label{cmd:async2sync
}
234 \begin{lstlisting
}[numbers=left,frame=single
]
235 async2sync
[options
] [selection
]
237 This command replaces async FF inputs with sync circuits emulating the same
238 behavior for when the async signals are actually synchronized to the clock.
240 This pass assumes negative hold time for the async FF inputs. For example when
241 a reset deasserts with the clock edge, then the FF output will still drive the
242 reset value in the next cycle regardless of the data-in value at the time of
245 Currently only $adff cells are supported by this pass.
248 \section{attrmap -- renaming attributes
}
250 \begin{lstlisting
}[numbers=left,frame=single
]
251 attrmap
[options
] [selection
]
253 This command renames attributes and/or mapps key/value pairs to
254 other key/value pairs.
257 Match attribute names case-insensitively and set it to the specified
260 -rename <old_name> <new_name>
261 Rename attributes as specified
263 -map <old_name>=<old_value> <new_name>=<new_value>
264 Map key/value pairs as indicated.
266 -imap <old_name>=<old_value> <new_name>=<new_value>
267 Like -map, but use case-insensitive match for <old_value> when
268 it is a string value.
270 -remove <name>=<value>
271 Remove attributes matching this pattern.
274 Operate on module attributes instead of attributes on wires and cells.
276 For example, mapping Xilinx-style "keep" attributes to Yosys-style:
278 attrmap -tocase keep -imap keep="true" keep=
1 \
279 -imap keep="false" keep=
0 -remove keep=
0
282 \section{attrmvcp -- move or copy attributes from wires to driving cells
}
284 \begin{lstlisting
}[numbers=left,frame=single
]
285 attrmvcp
[options
] [selection
]
287 Move or copy attributes on wires to the cells driving them.
290 By default, attributes are moved. This will only add
291 the attribute to the cell, without removing it from
295 If no selected cell consumes the attribute, then it is
296 left on the wire by default. This option will cause the
297 attribute to be removed from the wire, even if no selected
301 By default, attriburtes are moved to the cell driving the
302 wire. With this option set it will be moved to the cell
303 driven by the wire instead.
306 Move or copy this attribute. This option can be used
310 \section{blackbox -- change type of cells in the design
}
312 \begin{lstlisting
}[numbers=left,frame=single
]
313 blackbox
[options
] [selection
]
315 Convert modules into blackbox modules (remove contents and set the blackbox
319 \section{cd -- a shortcut for 'select -module <name>'
}
321 \begin{lstlisting
}[numbers=left,frame=single
]
324 This is just a shortcut for 'select -module <modname>'.
329 When no module with the specified name is found, but there is a cell
330 with the specified name in the current module, then this is equivalent
335 Remove trailing substrings that start with '.' in current module name until
336 the name of a module in the current design is generated, then switch to that
337 module. Otherwise clear the current selection.
341 This is just a shortcut for 'select -clear'.
344 \section{check -- check for obvious problems in the design
}
346 \begin{lstlisting
}[numbers=left,frame=single
]
347 check
[options
] [selection
]
349 This pass identifies the following problems in the current design:
351 - combinatorial loops
353 - two or more conflicting drivers for one wire
355 - used wires that do not have a driver
357 When called with -noinit then this command also checks for wires which have
358 the 'init' attribute set.
360 When called with -initdrv then this command also checks for wires which have
361 the 'init' attribute set and aren't driven by a FF cell type.
363 When called with -assert then the command will produce an error if any
364 problems are found in the current design.
367 \section{chformal -- change formal constraints of the design
}
369 \begin{lstlisting
}[numbers=left,frame=single
]
370 chformal
[types
] [mode
] [options
] [selection
]
372 Make changes to the formal constraints of the design. The
[types
] options
373 the type of constraint to operate on. If none of the folling options is given,
374 the command will operate on all constraint types:
376 -assert $assert cells, representing assert(...) constraints
377 -assume $assume cells, representing assume(...) constraints
378 -live $live cells, representing assert(s_eventually ...)
379 -fair $fair cells, representing assume(s_eventually ...)
380 -cover $cover cells, representing cover() statements
382 Exactly one of the following modes must be specified:
385 remove the cells and thus constraints from the design
388 bypass FFs that only delay the activation of a constraint
391 delay activation of the constraint by <N> clock cycles
394 ignore activation of the constraint in the first <N> clock cycles
400 change the roles of cells as indicated. this options can be combined
403 \section{chparam -- re-evaluate modules with new parameters
}
405 \begin{lstlisting
}[numbers=left,frame=single
]
406 chparam
[ -set name value
]...
[selection
]
408 Re-evaluate the selected modules with new parameters. String values must be
409 passed in double quotes (").
412 chparam -list
[selection
]
414 List the available parameters of the selected modules.
417 \section{chtype -- change type of cells in the design
}
419 \begin{lstlisting
}[numbers=left,frame=single
]
420 chtype
[options
] [selection
]
422 Change the types of cells in the design.
425 set the cell type to the given type
427 -map <old_type> <new_type>
428 change cells types that match <old_type> to <new_type>
431 \section{clean -- remove unused cells and wires
}
433 \begin{lstlisting
}[numbers=left,frame=single
]
434 clean
[options
] [selection
]
436 This is identical to 'opt_clean', but less verbose.
438 When commands are separated using the ';;' token, this command will be executed
439 between the commands.
441 When commands are separated using the ';;;' token, this command will be executed
442 in -purge mode between the commands.
445 \section{clk2fflogic -- convert clocked FFs to generic \$ff cells
}
446 \label{cmd:clk2fflogic
}
447 \begin{lstlisting
}[numbers=left,frame=single
]
448 clk2fflogic
[options
] [selection
]
450 This command replaces clocked flip-flops with generic $ff cells that use the
451 implicit global clock. This is useful for formal verification of designs with
455 \section{connect -- create or remove connections
}
457 \begin{lstlisting
}[numbers=left,frame=single
]
458 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
460 Create a connection. This is equivalent to adding the statement 'assign
461 <lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
462 drivers for <lhs-expr> are unconnected. This can be overwritten by using
466 connect
[-nomap
] -unset <expr>
468 Unconnect all existing drivers for the specified expression.
471 connect
[-nomap
] -port <cell> <port> <expr>
473 Connect the specified cell port to the specified cell port.
476 Per default signal alias names are resolved and all signal names are mapped
477 the the signal name of the primary driver. Using the -nomap option deactivates
480 The connect command operates in one module only. Either only one module must
481 be selected or an active module must be set using the 'cd' command.
483 This command does not operate on module with processes.
486 \section{connwrappers -- match width of input-output port pairs
}
487 \label{cmd:connwrappers
}
488 \begin{lstlisting
}[numbers=left,frame=single
]
489 connwrappers
[options
] [selection
]
491 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
492 in wrapper cells with a (larger) constant port size. I.e. the upper bits
493 of the wrapper output are signed/unsigned bit extended. This command uses this
494 knowledge to rewire the inputs of the driven cells to match the output of
497 -signed <cell_type> <port_name> <width_param>
498 -unsigned <cell_type> <port_name> <width_param>
499 consider the specified signed/unsigned wrapper output
501 -port <cell_type> <port_name> <width_param> <sign_param>
502 use the specified parameter to decide if signed or unsigned
504 The options -signed, -unsigned, and -port can be specified multiple times.
507 \section{coolrunner2
\_sop -- break \$sop cells into ANDTERM/ORTERM cells
}
508 \label{cmd:coolrunner2_sop
}
509 \begin{lstlisting
}[numbers=left,frame=single
]
510 coolrunner2_sop
[options
] [selection
]
512 Break $sop cells into ANDTERM/ORTERM cells.
515 \section{copy -- copy modules in the design
}
517 \begin{lstlisting
}[numbers=left,frame=single
]
518 copy old_name new_name
520 Copy the specified module. Note that selection patterns are not supported
524 \section{cover -- print code coverage counters
}
526 \begin{lstlisting
}[numbers=left,frame=single
]
527 cover
[options
] [pattern
]
529 Print the code coverage counters collected using the cover() macro in the Yosys
530 C++ code. This is useful to figure out what parts of Yosys are utilized by a
534 Do not print output to the normal destination (console and/or log file)
537 Write output to this file, truncate if exists.
540 Write output to this file, append if exists.
543 Write output to a newly created file in the specified directory.
545 When one or more pattern (shell wildcards) are specified, then only counters
546 matching at least one pattern are printed.
549 It is also possible to instruct Yosys to print the coverage counters on program
550 exit to a file using environment variables:
552 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
554 This will create a file (with an auto-generated name) in this
555 directory and write the coverage counters to it.
557 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
559 This will append the coverage counters to the specified file.
562 Hint: Use the following AWK command to consolidate Yosys coverage files:
564 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
565 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
568 Coverage counters are only available in Yosys for Linux.
571 \section{delete -- delete objects in the design
}
573 \begin{lstlisting
}[numbers=left,frame=single
]
576 Deletes the selected objects. This will also remove entire modules, if the
577 whole module is selected.
580 delete
{-input|-output|-port
} [selection
]
582 Does not delete any object but removes the input and/or output flag on the
583 selected wires, thus 'deleting' module ports.
586 \section{deminout -- demote inout ports to input or output
}
588 \begin{lstlisting
}[numbers=left,frame=single
]
589 deminout
[options
] [selection
]
591 "Demote" inout ports to input or output ports, if possible.
594 \section{design -- save, restore and reset current design
}
596 \begin{lstlisting
}[numbers=left,frame=single
]
599 Clear the current design.
604 Save the current design under the given name.
609 Save the current design under the given name and then clear the current design.
614 Push the current design to the stack and then clear the current design.
619 Reset the current design and pop the last design from the stack.
624 Reset the current design and load the design previously saved under the given
628 design -copy-from <name>
[-as <new_mod_name>
] <selection>
630 Copy modules from the specified design into the current one. The selection is
631 evaluated in the other design.
634 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
636 Copy modules from the current design into the specified one.
639 design -import <name>
[-as <new_top_name>
] [selection
]
641 Import the specified design into the current design. The source design must
642 either have a selected top module or the selection must contain exactly one
643 module that is then used as top module for this command.
648 The Verilog front-end remembers defined macros and top-level declarations
649 between calls to 'read_verilog'. This command resets this memory.
652 \section{dff2dffe -- transform \$dff cells to \$dffe cells
}
654 \begin{lstlisting
}[numbers=left,frame=single
]
655 dff2dffe
[options
] [selection
]
657 This pass transforms $dff cells driven by a tree of multiplexers with one or
658 more feedback paths to $dffe cells. It also works on gate-level cells such as
659 $_DFF_P_, $_DFF_N_ and $_MUX_.
662 operate in the opposite direction: replace $dffe cells with combinations
663 of $dff and $mux cells. the options below are ignore in unmap mode.
665 -direct <internal_gate_type> <external_gate_type>
666 map directly to external gate type. <internal_gate_type> can
667 be any internal gate-level FF cell (except $_DFFE_??_). the
668 <external_gate_type> is the cell type name for a cell with an
669 identical interface to the <internal_gate_type>, except it
670 also has an high-active enable port 'E'.
671 Usually <external_gate_type> is an intermediate cell type
672 that is then translated to the final type using 'techmap'.
674 -direct-match <pattern>
675 like -direct for all DFF cell types matching the expression.
676 this will use $__DFFE_* as <external_gate_type> matching the
677 internal gate type $_DFF_*_, and $__DFFSE_* for those matching
678 $_DFFS_*_, except for $_DFF_
[NP
]_, which is converted to
682 \section{dff2dffs -- process sync set/reset with SR over CE priority
}
684 \begin{lstlisting
}[numbers=left,frame=single
]
685 dff2dffs
[options
] [selection
]
687 Merge synchronous set/reset $_MUX_ cells to create $__DFFS_
[NP
][NP
][01], to be run before
688 dff2dffe for SR over CE priority.
691 \section{dffinit -- set INIT param on FF cells
}
693 \begin{lstlisting
}[numbers=left,frame=single
]
694 dffinit
[options
] [selection
]
696 This pass sets an FF cell parameter to the the initial value of the net it
697 drives. (This is primarily used in FPGA flows.)
699 -ff <cell_name> <output_port> <init_param>
700 operate on the specified cell type. this option can be used
704 use the string values "high" and "low" to represent a single-bit
705 initial value of
1 or
0. (multi-bit values are not supported in this
709 \section{dfflibmap -- technology mapping of flip-flops
}
710 \label{cmd:dfflibmap
}
711 \begin{lstlisting
}[numbers=left,frame=single
]
712 dfflibmap
[-prepare
] -liberty <file>
[selection
]
714 Map internal flip-flop cells to the flip-flop cells in the technology
715 library specified in the given liberty file.
717 This pass may add inverters as needed. Therefore it is recommended to
718 first run this pass and then map the logic paths to the target technology.
720 When called with -prepare, this command will convert the internal FF cells
721 to the internal cell types that best match the cells found in the given
725 \section{dffsr2dff -- convert DFFSR cells to simpler FF cell types
}
726 \label{cmd:dffsr2dff
}
727 \begin{lstlisting
}[numbers=left,frame=single
]
728 dffsr2dff
[options
] [selection
]
730 This pass converts DFFSR cells ($dffsr, $_DFFSR_???_) and ADFF cells ($adff,
731 $_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.
734 \section{dump -- print parts of the design in ilang format
}
736 \begin{lstlisting
}[numbers=left,frame=single
]
737 dump
[options
] [selection
]
739 Write the selected parts of the design to the console or specified file in
743 also dump the module headers, even if only parts of a single
747 only dump the module headers if the entire module is selected
750 write to the specified file.
753 like -outfile but append instead of overwrite
756 \section{echo -- turning echoing back of commands on and off
}
758 \begin{lstlisting
}[numbers=left,frame=single
]
761 Print all commands to log before executing them.
766 Do not print all commands to log before executing them. (default)
769 \section{edgetypes -- list all types of edges in selection
}
770 \label{cmd:edgetypes
}
771 \begin{lstlisting
}[numbers=left,frame=single
]
772 edgetypes
[options
] [selection
]
774 This command lists all unique types of 'edges' found in the selection. An 'edge'
775 is a
4-tuple of source and sink cell type and port name.
778 \section{equiv
\_add -- add a \$equiv cell
}
779 \label{cmd:equiv_add
}
780 \begin{lstlisting
}[numbers=left,frame=single
]
781 equiv_add
[-try
] gold_sig gate_sig
783 This command adds an $equiv cell for the specified signals.
786 equiv_add
[-try
] -cell gold_cell gate_cell
788 This command adds $equiv cells for the ports of the specified cells.
791 \section{equiv
\_induct -- proving \$equiv cells using temporal induction
}
792 \label{cmd:equiv_induct
}
793 \begin{lstlisting
}[numbers=left,frame=single
]
794 equiv_induct
[options
] [selection
]
796 Uses a version of temporal induction to prove $equiv cells.
798 Only selected $equiv cells are proven and only selected cells are used to
802 enable modelling of undef states
805 the max. number of time steps to be considered (default =
4)
807 This command is very effective in proving complex sequential circuits, when
808 the internal state of the circuit quickly propagates to $equiv cells.
810 However, this command uses a weak definition of 'equivalence': This command
811 proves that the two circuits will not diverge after they produce equal
812 outputs (observable points via $equiv) for at least <N> cycles (the <N>
815 Combined with simulation this is very powerful because simulation can give
816 you confidence that the circuits start out synced for at least <N> cycles
820 \section{equiv
\_make -- prepare a circuit for equivalence checking
}
821 \label{cmd:equiv_make
}
822 \begin{lstlisting
}[numbers=left,frame=single
]
823 equiv_make
[options
] gold_module gate_module equiv_module
825 This creates a module annotated with $equiv cells from two presumably
826 equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
827 to work with the created equivalent checking module.
830 Also match cells and wires with $... names.
833 Do not match cells or signals that match the names in the file.
836 Match FSM encodings using the description from the file.
837 See 'help fsm_recode' for details.
839 Note: The circuit created by this command is not a miter (with something like
840 a trigger output), but instead uses $equiv cells to encode the equivalence
841 checking problem. Use 'miter -equiv' if you want to create a miter circuit.
844 \section{equiv
\_mark -- mark equivalence checking regions
}
845 \label{cmd:equiv_mark
}
846 \begin{lstlisting
}[numbers=left,frame=single
]
847 equiv_mark
[options
] [selection
]
849 This command marks the regions in an equivalence checking module. Region
0 is
850 the proven part of the circuit. Regions with higher numbers are connected
851 unproven subcricuits. The integer attribute 'equiv_region' is set on all
855 \section{equiv
\_miter -- extract miter from equiv circuit
}
856 \label{cmd:equiv_miter
}
857 \begin{lstlisting
}[numbers=left,frame=single
]
858 equiv_miter
[options
] miter_module
[selection
]
860 This creates a miter module for further analysis of the selected $equiv cells.
863 Create a trigger output
866 Create cmp_* outputs for individual unproven $equiv cells
869 Create a $assert cell for each unproven $equiv cell
872 Create compare logic that handles undefs correctly
875 \section{equiv
\_purge -- purge equivalence checking module
}
876 \label{cmd:equiv_purge
}
877 \begin{lstlisting
}[numbers=left,frame=single
]
878 equiv_purge
[options
] [selection
]
880 This command removes the proven part of an equivalence checking module, leaving
881 only the unproven segments in the design. This will also remove and add module
885 \section{equiv
\_remove -- remove \$equiv cells
}
886 \label{cmd:equiv_remove
}
887 \begin{lstlisting
}[numbers=left,frame=single
]
888 equiv_remove
[options
] [selection
]
890 This command removes the selected $equiv cells. If neither -gold nor -gate is
891 used then only proven cells are removed.
900 \section{equiv
\_simple -- try proving simple \$equiv instances
}
901 \label{cmd:equiv_simple
}
902 \begin{lstlisting
}[numbers=left,frame=single
]
903 equiv_simple
[options
] [selection
]
905 This command tries to prove $equiv cells using a simple direct SAT approach.
911 enable modelling of undef states
914 create shorter input cones that stop at shared nodes. This yields
915 simpler SAT problems but sometimes fails to prove equivalence.
918 disabling grouping of $equiv cells by output wire
921 the max. number of time steps to be considered (default =
1)
924 \section{equiv
\_status -- print status of equivalent checking module
}
925 \label{cmd:equiv_status
}
926 \begin{lstlisting
}[numbers=left,frame=single
]
927 equiv_status
[options
] [selection
]
929 This command prints status information for all selected $equiv cells.
932 produce an error if any unproven $equiv cell is found
935 \section{equiv
\_struct -- structural equivalence checking
}
936 \label{cmd:equiv_struct
}
937 \begin{lstlisting
}[numbers=left,frame=single
]
938 equiv_struct
[options
] [selection
]
940 This command adds additional $equiv cells based on the assumption that the
941 gold and gate circuit are structurally equivalent. Note that this can introduce
942 bad $equiv cells in cases where the netlists are not structurally equivalent,
943 for example when analyzing circuits with cells with commutative inputs. This
944 command will also de-duplicate gates.
947 by default this command performans forward sweeps until nothing can
948 be merged by forwards sweeps, then backward sweeps until forward
949 sweeps are effective again. with this option set only forward sweeps
953 add the specified cell type to the list of cell types that are only
954 merged in forward sweeps and never in backward sweeps. $equiv is in
955 this list automatically.
958 by default, the internal RTL and gate cell types are ignored. add
959 this option to also process those cell types with this command.
962 maximum number of iterations to run before aborting
965 \section{eval -- evaluate the circuit given an input
}
967 \begin{lstlisting
}[numbers=left,frame=single
]
968 eval
[options
] [selection
]
970 This command evaluates the value of a signal given the value of all required
973 -set <signal> <value>
974 set the specified signal to the specified value.
977 set all unspecified source signals to undef (x)
980 create a truth table using the specified input signals
983 show the value for the specified signal. if no -show option is passed
984 then all output ports of the current module are used.
987 \section{expose -- convert internal signals to module ports
}
989 \begin{lstlisting
}[numbers=left,frame=single
]
990 expose
[options
] [selection
]
992 This command exposes all selected internal signals of a module as additional
996 only consider wires that are directly driven by register cell.
999 when exposing a wire, create an input/output pair and cut the internal
1000 signal path at that wire.
1003 when exposing a wire, create an input port and disconnect the internal
1007 only expose those signals that are shared among the selected modules.
1008 this is useful for preparing modules for equivalence checking.
1011 also turn connections to instances of other modules to additional
1012 inputs and outputs and remove the module instances.
1015 turn flip-flops to sets of inputs and outputs.
1018 when creating new wire/port names, the original object name is suffixed
1019 with this separator (default: '.') and the port name or a type
1020 designator for the exposed signal.
1023 \section{extract -- find subcircuits and replace them with cells
}
1025 \begin{lstlisting
}[numbers=left,frame=single
]
1026 extract -map <map_file>
[options
] [selection
]
1027 extract -mine <out_file>
[options
] [selection
]
1029 This pass looks for subcircuits that are isomorphic to any of the modules
1030 in the given map file and replaces them with instances of this modules. The
1031 map file can be a Verilog source file
(*.v) or an ilang file (*.il).
1034 use the modules in this file as reference. This option can be used
1038 use the modules in this in-memory design as reference. This option can
1039 be used multiple times.
1042 print debug output while analyzing
1045 also find instances with constant drivers. this may be much
1046 slower than the normal operation.
1049 normally builtin port swapping rules for internal cells are used per
1050 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
1051 when this option is used.
1053 -compat <needle_type> <haystack_type>
1054 Per default, the cells in the map file (needle) must have the
1055 type as the cells in the active design (haystack). This option
1056 can be used to register additional pairs of types that should
1057 match. This option can be used multiple times.
1059 -swap <needle_type> <port1>,<port2>[,...]
1060 Register a set of swappable ports for a needle cell type.
1061 This option can be used multiple times.
1063 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
1064 Register a valid permutation of swappable ports for a needle
1065 cell type. This option can be used multiple times.
1067 -cell_attr <attribute_name>
1068 Attributes on cells with the given name must match.
1070 -wire_attr <attribute_name>
1071 Attributes on wires with the given name must match.
1074 Do not use parameters when matching cells.
1076 -ignore_param <cell_type> <parameter_name>
1077 Do not use this parameter when matching cells.
1079 This pass does not operate on modules with unprocessed processes in it.
1080 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
1082 This pass can also be used for mining for frequent subcircuits. In this mode
1083 the following options are to be used instead of the -map option.
1086 mine for frequent subcircuits and write them to the given ilang file
1088 -mine_cells_span <min> <max>
1089 only mine for subcircuits with the specified number of cells
1092 -mine_min_freq <num>
1093 only mine for subcircuits with at least the specified number of matches
1096 -mine_limit_matches_per_module <num>
1097 when calculating the number of matches for a subcircuit, don't count
1098 more than the specified number of matches per module
1100 -mine_max_fanout <num>
1101 don't consider internal signals with more than <num> connections
1103 The modules in the map file may have the attribute 'extract_order' set to an
1104 integer value. Then this value is used to determine the order in which the pass
1105 tries to map the modules to the design (ascending, default value is 0).
1107 See 'help techmap' for a pass that does the opposite thing.
1110 \section{extract\_counter -- Extract GreenPak4 counter cells}
1111 \label{cmd:extract_counter}
1112 \begin{lstlisting}[numbers=left,frame=single]
1113 extract_counter [options] [selection]
1115 This pass converts non-resettable or async resettable down counters to
1116 counter cells. Use a target-specific 'techmap' map file to convert those cells
1117 to the actual target cells.
1120 Only extract counters up to N bits wide
1123 Only allow parallel output from the counter to the listed cell types
1124 (if not specified, parallel outputs are not restricted)
1127 \section{extract\_fa -- find and extract full/half adders}
1128 \label{cmd:extract_fa}
1129 \begin{lstlisting}[numbers=left,frame=single]
1130 extract_fa [options] [selection]
1132 This pass extracts full/half adders from a gate-level design.
1135 Enable cell types (fa=full adder, ha=half adder)
1136 All types are enabled if none of this options is used
1139 Set maximum depth for extracted logic cones (default=20)
1142 Set maximum breadth for extracted logic cones (default=6)
1148 \section{extract\_reduce -- converts gate chains into \$reduce\_* cells}
1149 \label{cmd:extract_reduce}
1150 \begin{lstlisting}[numbers=left,frame=single]
1151 extract_reduce [options] [selection]
1153 converts gate chains into $reduce_* cells
1155 This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them
1156 with their corresponding $reduce_* cells. Because this command only operates on
1157 these cell types, it is recommended to map the design to only these cell types
1158 using the `abc -g` command. Note that, in some cases, it may be more effective
1159 to map the design to only $_AND_ cells, run extract_reduce, map the remaining
1160 parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.
1163 Allows matching of cells that have loads outside the chain. These cells
1164 will be replicated and folded into the $reduce_* cell, but the original
1165 cell will remain, driving its original loads.
1168 \section{flatten -- flatten design}
1170 \begin{lstlisting}[numbers=left,frame=single]
1173 This pass flattens the design by replacing cells by their implementation. This
1174 pass is very similar to the 'techmap' pass. The only difference is that this
1175 pass is using the current design as mapping library.
1177 Cells and/or modules with the 'keep_hierarchy' attribute set will not be
1178 flattened by this command.
1181 \section{freduce -- perform functional reduction}
1183 \begin{lstlisting}[numbers=left,frame=single]
1184 freduce [options] [selection]
1186 This pass performs functional reduction in the circuit. I.e. if two nodes are
1187 equivalent, they are merged to one node and one of the redundant drivers is
1188 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
1191 enable verbose or very verbose output
1194 enable explicit handling of inverted signals
1197 stop after <n> reduction operations. this is mostly used for
1198 debugging the freduce command itself.
1201 dump the design to <prefix>_<module>_<num>.il after each reduction
1202 operation. this is mostly used for debugging the freduce command.
1204 This pass is undef-aware, i.e. it considers don't-care values for detecting
1207 All selected wires are considered for rewiring. The selected cells cover the
1208 circuit that is analyzed.
1211 \section{fsm -- extract and optimize finite state machines}
1213 \begin{lstlisting}[numbers=left,frame=single]
1214 fsm [options] [selection]
1216 This pass calls all the other fsm_* passes in a useful order. This performs
1217 FSM extraction and optimization. It also calls opt_clean as needed:
1219 fsm_detect unless got option -nodetect
1226 fsm_expand if got option -expand
1227 opt_clean if got option -expand
1228 fsm_opt if got option -expand
1230 fsm_recode unless got option -norecode
1234 fsm_export if got option -export
1235 fsm_map unless got option -nomap
1239 -expand, -norecode, -export, -nomap
1240 enable or disable passes as indicated above
1243 call expand with -full option
1246 -fm_set_fsm_file file
1248 passed through to fsm_recode pass
1251 \section{fsm\_detect -- finding FSMs in design}
1252 \label{cmd:fsm_detect}
1253 \begin{lstlisting}[numbers=left,frame=single]
1254 fsm_detect [selection]
1256 This pass detects finite state machines by identifying the state signal.
1257 The state signal is then marked by setting the attribute 'fsm_encoding'
1258 on the state signal to "auto".
1260 Existing 'fsm_encoding' attributes are not changed by this pass.
1262 Signals can be protected from being detected by this pass by setting the
1263 'fsm_encoding' attribute to "none".
1266 \section{fsm\_expand -- expand FSM cells by merging logic into it}
1267 \label{cmd:fsm_expand}
1268 \begin{lstlisting}[numbers=left,frame=single]
1269 fsm_expand [-full] [selection]
1271 The fsm_extract pass is conservative about the cells that belong to a finite
1272 state machine. This pass can be used to merge additional auxiliary gates into
1273 the finite state machine.
1275 By default, fsm_expand is still a bit conservative regarding merging larger
1276 word-wide cells. Call with -full to consider all cells for merging.
1279 \section{fsm\_export -- exporting FSMs to KISS2 files}
1280 \label{cmd:fsm_export}
1281 \begin{lstlisting}[numbers=left,frame=single]
1282 fsm_export [-noauto] [-o filename] [-origenc] [selection]
1284 This pass creates a KISS2 file for every selected FSM. For FSMs with the
1285 'fsm_export' attribute set, the attribute value is used as filename, otherwise
1286 the module and cell name is used as filename. If the parameter '-o' is given,
1287 the first exported FSM is written to the specified filename. This overwrites
1288 the setting as specified with the 'fsm_export' attribute. All other FSMs are
1289 exported to the default name as mentioned above.
1292 only export FSMs that have the 'fsm_export' attribute set
1295 filename of the first exported FSM
1298 use binary state encoding as state names instead of s0, s1, ...
1301 \section{fsm\_extract -- extracting FSMs in design}
1302 \label{cmd:fsm_extract}
1303 \begin{lstlisting}[numbers=left,frame=single]
1304 fsm_extract [selection]
1306 This pass operates on all signals marked as FSM state signals using the
1307 'fsm_encoding' attribute. It consumes the logic that creates the state signal
1308 and uses the state signal to generate control signal and replaces it with an
1311 The generated FSM cell still generates the original state signal with its
1312 original encoding. The 'fsm_opt' pass can be used in combination with the
1313 'opt_clean' pass to eliminate this signal.
1316 \section{fsm\_info -- print information on finite state machines}
1317 \label{cmd:fsm_info}
1318 \begin{lstlisting}[numbers=left,frame=single]
1319 fsm_info [selection]
1321 This pass dumps all internal information on FSM cells. It can be useful for
1322 analyzing the synthesis process and is called automatically by the 'fsm'
1323 pass so that this information is included in the synthesis log file.
1326 \section{fsm\_map -- mapping FSMs to basic logic}
1328 \begin{lstlisting}[numbers=left,frame=single]
1331 This pass translates FSM cells to flip-flops and logic.
1334 \section{fsm\_opt -- optimize finite state machines}
1336 \begin{lstlisting}[numbers=left,frame=single]
1339 This pass optimizes FSM cells. It detects which output signals are actually
1340 not used and removes them from the FSM. This pass is usually used in
1341 combination with the 'opt_clean' pass (see also 'help fsm').
1344 \section{fsm\_recode -- recoding finite state machines}
1345 \label{cmd:fsm_recode}
1346 \begin{lstlisting}[numbers=left,frame=single]
1347 fsm_recode [options] [selection]
1349 This pass reassign the state encodings for FSM cells. At the moment only
1350 one-hot encoding and binary encoding is supported.
1352 specify the encoding scheme used for FSMs without the
1353 'fsm_encoding' attribute or with the attribute set to `auto'.
1355 -fm_set_fsm_file <file>
1356 generate a file containing the mapping from old to new FSM encoding
1357 in form of Synopsys Formality set_fsm_* commands.
1360 write the mappings from old to new FSM encoding to a file in the
1363 .fsm <module_name> <state_signal>
1364 .map <old_bitpattern> <new_bitpattern>
1367 \section{greenpak4\_dffinv -- merge greenpak4 inverters and DFF/latches}
1368 \label{cmd:greenpak4_dffinv}
1369 \begin{lstlisting}[numbers=left,frame=single]
1370 greenpak4_dffinv [options] [selection]
1372 Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.
1375 \section{help -- display help messages}
1377 \begin{lstlisting}[numbers=left,frame=single]
1378 help ................ list all commands
1379 help <command> ...... print help message for given command
1380 help -all ........... print complete command reference
1382 help -cells .......... list all cell types
1383 help <celltype> ..... print help message for given cell type
1384 help <celltype>+ .... print verilog code for given cell type
1387 \section{hierarchy -- check, expand and clean up design hierarchy}
1388 \label{cmd:hierarchy}
1389 \begin{lstlisting}[numbers=left,frame=single]
1390 hierarchy [-check] [-top <module>]
1391 hierarchy -generate <cell-types> <port-decls>
1393 In parametric designs, a module might exists in several variations with
1394 different parameter values. This pass looks at all modules in the current
1395 design an re-runs the language frontends for the parametric modules as
1399 also check the design hierarchy. this generates an error when
1400 an unknown module is used as cell type.
1403 like -check, but also thow an error if blackbox modules are
1404 instantiated, and throw an error if the design has no top module
1407 by default the hierarchy command will not remove library (blackbox)
1408 modules. use this option to also remove unused blackbox modules.
1411 search for files named <module_name>.v in the specified directory
1412 for unknown modules and automatically run read_verilog for each
1416 per default this pass also converts positional arguments in cells
1417 to arguments using port names. this option disables this behavior.
1420 per default this pass adjusts the port width on cells that are
1421 module instances when the width does not match the module port. this
1422 option disables this behavior.
1425 per default this pass sets the "keep" attribute on all modules
1426 that directly or indirectly contain one or more $assert cells. this
1427 option disables this behavior.
1430 use the specified top module to built a design hierarchy. modules
1431 outside this tree (unused modules) are removed.
1433 when the -top option is used, the 'top' attribute will be set on the
1434 specified top module. otherwise a module with the 'top' attribute set
1435 will implicitly be used as top module, if such a module exists.
1438 automatically determine the top of the design hierarchy and mark it.
1440 In -generate mode this pass generates blackbox modules for the given cell
1441 types (wildcards supported). For this the design is searched for cells that
1442 match the given types and then the given port declarations are used to
1443 determine the direction of the ports. The syntax for a port declaration is:
1445 {i|o|io}[@<num>]:<portname>
1447 Input ports are specified with the 'i' prefix, output ports with the 'o'
1448 prefix and inout ports with the 'io' prefix. The optional <num> specifies
1449 the position of the port in the parameter list (needed when instantiated
1450 using positional arguments). When <num> is not specified, the <portname> can
1451 also contain wildcard characters.
1453 This pass ignores the current selection and always operates on all modules
1454 in the current design.
1457 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers}
1459 \begin{lstlisting}[numbers=left,frame=single]
1460 hilomap [options] [selection]
1462 Map constants to 'tielo' and 'tiehi' driver cells.
1464 -hicell <celltype> <portname>
1465 Replace constant hi bits with this cell.
1467 -locell <celltype> <portname>
1468 Replace constant lo bits with this cell.
1471 Create only one hi/lo cell and connect all constant bits
1472 to that cell. Per default a separate cell is created for
1476 \section{history -- show last interactive commands}
1478 \begin{lstlisting}[numbers=left,frame=single]
1481 This command prints all commands in the shell history buffer. This are
1482 all commands executed in an interactive session, but not the commands
1483 from executed scripts.
1486 \section{ice40\_ffinit -- iCE40: handle FF init values}
1487 \label{cmd:ice40_ffinit}
1488 \begin{lstlisting}[numbers=left,frame=single]
1489 ice40_ffinit [options] [selection]
1491 Remove zero init values for FF output signals. Add inverters to implement
1492 nonzero init values.
1495 \section{ice40\_ffssr -- iCE40: merge synchronous set/reset into FF cells}
1496 \label{cmd:ice40_ffssr}
1497 \begin{lstlisting}[numbers=left,frame=single]
1498 ice40_ffssr [options] [selection]
1500 Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.
1503 \section{ice40\_opt -- iCE40: perform simple optimizations}
1504 \label{cmd:ice40_opt}
1505 \begin{lstlisting}[numbers=left,frame=single]
1506 ice40_opt [options] [selection]
1508 This command executes the following script:
1511 <ice40 specific optimizations>
1512 opt_expr -mux_undef -undriven [-full]
1516 while <changed design>
1518 When called with the option -unlut, this command will transform all already
1519 mapped SB_LUT4 cells back to logic.
1522 \section{insbuf -- insert buffer cells for connected wires}
1524 \begin{lstlisting}[numbers=left,frame=single]
1525 insbuf [options] [selection]
1527 Insert buffer cells into the design for directly connected wires.
1529 -buf <celltype> <in-portname> <out-portname>
1530 Use the given cell type instead of $_BUF_. (Notice that the next
1531 call to "clean" will remove all $_BUF_ in the design.)
1534 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
1535 \label{cmd:iopadmap}
1536 \begin{lstlisting}[numbers=left,frame=single]
1537 iopadmap [options] [selection]
1539 Map module inputs/outputs to PAD cells from a library. This pass
1540 can only map to very simple PAD cells. Use 'techmap' to further map
1541 the resulting cells to more sophisticated PAD cells.
1543 -inpad <celltype> <portname>[:<portname>]
1544 Map module input ports to the given cell type with the
1545 given output port name. if a 2nd portname is given, the
1546 signal is passed through the pad call, using the 2nd
1547 portname as the port facing the module port.
1549 -outpad <celltype> <portname>[:<portname>]
1550 -inoutpad <celltype> <portname>[:<portname>]
1551 Similar to -inpad, but for output and inout ports.
1553 -toutpad <celltype> <portname>:<portname>[:<portname>]
1554 Merges $_TBUF_ cells into the output pad cell. This takes precedence
1555 over the other -outpad cell. The first portname is the enable input
1556 of the tristate driver.
1558 -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]
1559 Merges $_TBUF_ cells into the inout pad cell. This takes precedence
1560 over the other -inoutpad cell. The first portname is the enable input
1561 of the tristate driver and the 2nd portname is the internal output
1562 buffering the external signal.
1564 -widthparam <param_name>
1565 Use the specified parameter name to set the port width.
1567 -nameparam <param_name>
1568 Use the specified parameter to set the port name.
1571 create individual bit-wide buffers even for ports that
1572 are wider. (the default behavior is to create word-wide
1573 buffers using -widthparam to set the word size on the cell.)
1575 Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.
1578 \section{json -- write design in JSON format}
1580 \begin{lstlisting}[numbers=left,frame=single]
1581 json [options] [selection]
1583 Write a JSON netlist of all selected objects.
1586 write to the specified file.
1589 also include AIG models for the different gate types
1591 See 'help write_json' for a description of the JSON format used.
1594 \section{log -- print text and log files}
1596 \begin{lstlisting}[numbers=left,frame=single]
1599 Print the given string to the screen and/or the log file. This is useful for TCL
1600 scripts, because the TCL command "puts" only goes to stdout but not to
1604 Print the output to stdout too. This is useful when all Yosys is executed
1605 with a script and the -q (quiet operation) argument to notify the user.
1608 Print the output to stderr too.
1611 Don't use the internal log() command. Use either -stdout or -stderr,
1612 otherwise no output will be generated at all.
1615 do not append a newline
1618 \section{ls -- list modules or objects in modules}
1620 \begin{lstlisting}[numbers=left,frame=single]
1623 When no active module is selected, this prints a list of modules.
1625 When an active module is selected, this prints a list of objects in the module.
1628 \section{ltp -- print longest topological path}
1630 \begin{lstlisting}[numbers=left,frame=single]
1631 ltp [options] [selection]
1633 This command prints the longest topological path in the design. (Only considers
1634 paths within a single module, so the design must be flattened.)
1637 automatically exclude FF cell types
1640 \section{lut2mux -- convert \$lut to \$\_MUX\_}
1642 \begin{lstlisting}[numbers=left,frame=single]
1643 lut2mux [options] [selection]
1645 This pass converts $lut cells to $_MUX_ gates.
1648 \section{maccmap -- mapping macc cells}
1650 \begin{lstlisting}[numbers=left,frame=single]
1651 maccmap [-unmap] [selection]
1653 This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
1654 is used then the $macc cell is mapped to $add, $sub, etc. cells instead.
1657 \section{memory -- translate memories to basic cells}
1659 \begin{lstlisting}[numbers=left,frame=single]
1660 memory [-nomap] [-nordff] [-memx] [-bram <bram_rules>] [selection]
1662 This pass calls all the other memory_* passes in a useful order:
1664 memory_dff [-nordff] (-memx implies -nordff)
1668 memory_memx (when called with -memx)
1670 memory_bram -rules <bram_rules> (when called with -bram)
1671 memory_map (skipped if called with -nomap)
1673 This converts memories to word-wide DFFs and address decoders
1674 or multiport memory blocks if called with the -nomap option.
1677 \section{memory\_bram -- map memories to block rams}
1678 \label{cmd:memory_bram}
1679 \begin{lstlisting}[numbers=left,frame=single]
1680 memory_bram -rules <rule_file> [selection]
1682 This pass converts the multi-port $mem memory cells into block ram instances.
1683 The given rules file describes the available resources and how they should be
1686 The rules file contains a set of block ram description and a sequence of match
1687 rules. A block ram description looks like this:
1689 bram RAMB1024X32 # name of BRAM cell
1690 init 1 # set to '1' if BRAM can be initialized
1691 abits 10 # number of address bits
1692 dbits 32 # number of data bits
1693 groups 2 # number of port groups
1694 ports 1 1 # number of ports in each group
1695 wrmode 1 0 # set to '1' if this groups is write ports
1696 enable 4 1 # number of enable bits
1697 transp 0 2 # transparent (for read ports)
1698 clocks 1 2 # clock configuration
1699 clkpol 2 2 # clock polarity configuration
1702 For the option 'transp' the value 0 means non-transparent, 1 means transparent
1703 and a value greater than 1 means configurable. All groups with the same
1704 value greater than 1 share the same configuration bit.
1706 For the option 'clocks' the value 0 means non-clocked, and a value greater
1707 than 0 means clocked. All groups with the same value share the same clock
1710 For the option 'clkpol' the value 0 means negative edge, 1 means positive edge
1711 and a value greater than 1 means configurable. All groups with the same value
1712 greater than 1 share the same configuration bit.
1714 Using the same bram name in different bram blocks will create different variants
1715 of the bram. Verilog configuration parameters for the bram are created as needed.
1717 It is also possible to create variants by repeating statements in the bram block
1718 and appending '@<label>' to the individual statements.
1720 A match rule looks like this:
1723 max waste 16384 # only use this bram if <= 16k ram bits are unused
1724 min efficiency 80 # only use this bram if efficiency is at least 80%
1727 It is possible to match against the following values with min/max rules:
1729 words ........ number of words in memory in design
1730 abits ........ number of address bits on memory in design
1731 dbits ........ number of data bits on memory in design
1732 wports ....... number of write ports on memory in design
1733 rports ....... number of read ports on memory in design
1734 ports ........ number of ports on memory in design
1735 bits ......... number of bits in memory in design
1736 dups .......... number of duplications for more read ports
1738 awaste ....... number of unused address slots for this match
1739 dwaste ....... number of unused data bits for this match
1740 bwaste ....... number of unused bram bits for this match
1741 waste ........ total number of unused bram bits (bwaste*dups)
1742 efficiency ... total percentage of used and non-duplicated bits
1744 acells ....... number of cells in 'address-direction'
1745 dcells ....... number of cells in 'data-direction'
1746 cells ........ total number of cells (acells*dcells*dups)
1748 The interface for the created bram instances is derived from the bram
1749 description. Use 'techmap' to convert the created bram instances into
1750 instances of the actual bram cells of your target architecture.
1752 A match containing the command 'or_next_if_better' is only used if it
1753 has a higher efficiency than the next match (and the one after that if
1754 the next also has 'or_next_if_better' set, and so forth).
1756 A match containing the command 'make_transp' will add external circuitry
1757 to simulate 'transparent read', if necessary.
1759 A match containing the command 'make_outreg' will add external flip-flops
1760 to implement synchronous read ports, if necessary.
1762 A match containing the command 'shuffle_enable A' will re-organize
1763 the data bits to accommodate the enable pattern of port A.
1766 \section{memory\_collect -- creating multi-port memory cells}
1767 \label{cmd:memory_collect}
1768 \begin{lstlisting}[numbers=left,frame=single]
1769 memory_collect [selection]
1771 This pass collects memories and memory ports and creates generic multiport
1775 \section{memory\_dff -- merge input/output DFFs into memories}
1776 \label{cmd:memory_dff}
1777 \begin{lstlisting}[numbers=left,frame=single]
1778 memory_dff [options] [selection]
1780 This pass detects DFFs at memory ports and merges them into the memory port.
1781 I.e. it consumes an asynchronous memory port and the flip-flops at its
1782 interface and yields a synchronous memory port.
1785 do not merge registers on read ports
1788 \section{memory\_map -- translate multiport memories to basic cells}
1789 \label{cmd:memory_map}
1790 \begin{lstlisting}[numbers=left,frame=single]
1791 memory_map [selection]
1793 This pass converts multiport memory cells as generated by the memory_collect
1794 pass to word-wide DFFs and address decoders.
1797 \section{memory\_memx -- emulate vlog sim behavior for mem ports}
1798 \label{cmd:memory_memx}
1799 \begin{lstlisting}[numbers=left,frame=single]
1800 memory_memx [selection]
1802 This pass adds additional circuitry that emulates the Verilog simulation
1803 behavior for out-of-bounds memory reads and writes.
1806 \section{memory\_nordff -- extract read port FFs from memories}
1807 \label{cmd:memory_nordff}
1808 \begin{lstlisting}[numbers=left,frame=single]
1809 memory_nordff [options] [selection]
1811 This pass extracts FFs from memory read ports. This results in a netlist
1812 similar to what one would get from calling memory_dff with -nordff.
1815 \section{memory\_share -- consolidate memory ports}
1816 \label{cmd:memory_share}
1817 \begin{lstlisting}[numbers=left,frame=single]
1818 memory_share [selection]
1820 This pass merges share-able memory ports into single memory ports.
1822 The following methods are used to consolidate the number of memory ports:
1824 - When write ports are connected to async read ports accessing the same
1825 address, then this feedback path is converted to a write port with
1826 byte/part enable signals.
1828 - When multiple write ports access the same address then this is converted
1829 to a single write port with a more complex data and/or enable logic path.
1831 - When multiple write ports are never accessed at the same time (a SAT
1832 solver is used to determine this), then the ports are merged into a single
1835 Note that in addition to the algorithms implemented in this pass, the $memrd
1836 and $memwr cells are also subject to generic resource sharing passes (and other
1837 optimizations) such as "share" and "opt_merge".
1840 \section{memory\_unpack -- unpack multi-port memory cells}
1841 \label{cmd:memory_unpack}
1842 \begin{lstlisting}[numbers=left,frame=single]
1843 memory_unpack [selection]
1845 This pass converts the multi-port $mem memory cells into individual $memrd and
1846 $memwr cells. It is the counterpart to the memory_collect pass.
1849 \section{miter -- automatically create a miter circuit}
1851 \begin{lstlisting}[numbers=left,frame=single]
1852 miter -equiv [options] gold_name gate_name miter_name
1854 Creates a miter circuit for equivalence checking. The gold- and gate- modules
1855 must have the same interfaces. The miter circuit will have all inputs of the
1856 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
1857 output that goes high if an output mismatch between the two source modules is
1861 a undef (x) bit in the gold module output will match any value in
1862 the gate module output.
1865 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
1866 on the miter circuit.
1869 also create a cmp_* output for each gold/gate output pair.
1872 also create an 'assert' cell that checks if trigger is always low.
1875 call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.
1878 miter -assert [options] module [miter_name]
1880 Creates a miter circuit for property checking. All input ports are kept,
1881 output ports are discarded. An additional output 'trigger' is created that
1882 goes high when an assert is violated. Without a miter_name, the existing
1886 keep module output ports.
1889 call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.
1892 \section{muxcover -- cover trees of MUX cells with wider MUXes}
1893 \label{cmd:muxcover}
1894 \begin{lstlisting}[numbers=left,frame=single]
1895 muxcover [options] [selection]
1897 Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells
1899 -mux4, -mux8, -mux16
1900 Use the specified types of MUXes. If none of those options are used,
1901 the effect is the same as if all of them where used.
1904 Do not insert decoder logic. This reduces the number of possible
1905 substitutions, but guarantees that the resulting circuit is not
1906 less efficient than the original circuit.
1909 \section{nlutmap -- map to LUTs of different sizes}
1911 \begin{lstlisting}[numbers=left,frame=single]
1912 nlutmap [options] [selection]
1914 This pass uses successive calls to 'abc' to map to an architecture. That
1915 provides a small number of differently sized LUTs.
1917 -luts N_1,N_2,N_3,...
1918 The number of LUTs with 1, 2, 3, ... inputs that are
1919 available in the target architecture.
1922 Create an error if not all logic can be mapped
1924 Excess logic that does not fit into the specified LUTs is mapped back
1925 to generic logic gates ($_AND_, etc.).
1928 \section{opt -- perform simple optimizations}
1930 \begin{lstlisting}[numbers=left,frame=single]
1931 opt [options] [selection]
1933 This pass calls all the other opt_* passes in a useful order. This performs
1934 a series of trivial optimizations and cleanups. This pass executes the other
1935 passes in the following order:
1937 opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1938 opt_merge [-share_all] -nomux
1942 opt_reduce [-fine] [-full]
1943 opt_merge [-share_all]
1946 opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1947 while <changed design>
1949 When called with -fast the following script is used instead:
1952 opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1953 opt_merge [-share_all]
1956 while <changed design in opt_rmdff>
1958 Note: Options in square brackets (such as [-keepdc]) are passed through to
1959 the opt_* commands when given to 'opt'.
1962 \section{opt\_clean -- remove unused cells and wires}
1963 \label{cmd:opt_clean}
1964 \begin{lstlisting}[numbers=left,frame=single]
1965 opt_clean [options] [selection]
1967 This pass identifies wires and cells that are unused and removes them. Other
1968 passes often remove cells but leave the wires in the design or reconnect the
1969 wires but leave the old cells in the design. This pass can be used to clean up
1970 after the passes that do the actual work.
1972 This pass only operates on completely selected modules without processes.
1975 also remove internal nets if they have a public name
1978 \section{opt\_demorgan -- Optimize reductions with DeMorgan equivalents}
1979 \label{cmd:opt_demorgan}
1980 \begin{lstlisting}[numbers=left,frame=single]
1981 opt_demorgan [selection]
1983 This pass pushes inverters through $reduce_* cells if this will reduce the
1984 overall gate count of the circuit
1987 \section{opt\_expr -- perform const folding and simple expression rewriting}
1988 \label{cmd:opt_expr}
1989 \begin{lstlisting}[numbers=left,frame=single]
1990 opt_expr [options] [selection]
1992 This pass performs const folding on internal cell types with constant inputs.
1993 It also performs some simple expression rewritring.
1996 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
1999 replace $mux cells with inverters or buffers when possible
2002 replace undriven nets with undef (x) constants
2005 optimize clock inverters by changing FF types
2008 perform fine-grain optimizations
2011 alias for -mux_undef -mux_bool -undriven -fine
2014 some optimizations change the behavior of the circuit with respect to
2015 don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
2016 all result bits to be set to x. this behavior changes when 'a+0' is
2017 replaced by 'a'. the -keepdc option disables all such optimizations.
2020 \section{opt\_merge -- consolidate identical cells}
2021 \label{cmd:opt_merge}
2022 \begin{lstlisting}[numbers=left,frame=single]
2023 opt_merge [options] [selection]
2025 This pass identifies cells with identical type and input signals. Such cells
2026 are then merged to one cell.
2029 Do not merge MUX cells.
2032 Operate on all cell types, not just built-in types.
2035 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
2036 \label{cmd:opt_muxtree}
2037 \begin{lstlisting}[numbers=left,frame=single]
2038 opt_muxtree [selection]
2040 This pass analyzes the control signals for the multiplexer trees in the design
2041 and identifies inputs that can never be active. It then removes this dead
2042 branches from the multiplexer trees.
2044 This pass only operates on completely selected modules without processes.
2047 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
2048 \label{cmd:opt_reduce}
2049 \begin{lstlisting}[numbers=left,frame=single]
2050 opt_reduce [options] [selection]
2052 This pass performs two interlinked optimizations:
2054 1. it consolidates trees of large AND gates or OR gates and eliminates
2057 2. it identifies duplicated inputs to MUXes and replaces them with a single
2058 input with the original control signals OR'ed together.
2061 perform fine-grain optimizations
2067 \section{opt\_rmdff -- remove DFFs with constant inputs}
2068 \label{cmd:opt_rmdff}
2069 \begin{lstlisting}[numbers=left,frame=single]
2070 opt_rmdff [-keepdc] [selection]
2072 This pass identifies flip-flops with constant inputs and replaces them with
2076 \section{plugin -- load and list loaded plugins}
2078 \begin{lstlisting}[numbers=left,frame=single]
2081 Load and list loaded plugins.
2083 -i <plugin_filename>
2084 Load (install) the specified plugin.
2087 Register the specified alias name for the loaded plugin
2093 \section{pmuxtree -- transform \$pmux cells to trees of \$mux cells}
2094 \label{cmd:pmuxtree}
2095 \begin{lstlisting}[numbers=left,frame=single]
2096 pmuxtree [options] [selection]
2098 This pass transforms $pmux cells to a trees of $mux cells.
2101 \section{prep -- generic synthesis script}
2103 \begin{lstlisting}[numbers=left,frame=single]
2106 This command runs a conservative RTL synthesis. A typical application for this
2107 is the preparation stage of a verification flow. This command does not operate
2108 on partly selected designs.
2111 use the specified module as top module (default='top')
2114 automatically determine the top of the design hierarchy
2117 flatten the design before synthesis. this will pass '-auto-top' to
2118 'hierarchy' if no top module is specified.
2121 passed to 'proc'. uses verilog simulation behavior for verilog if/case
2122 undef handling. this also prevents 'wreduce' from being run.
2125 simulate verilog simulation behavior for out-of-bounds memory accesses
2126 using the 'memory_memx' pass.
2129 do not run any of the memory_* passes
2132 do not pass -nordff to 'memory_dff'. This enables merging of FFs into
2136 do not call opt_* with -keepdc
2138 -run <from_label>[:<to_label>]
2139 only run the commands between the labels (see below). an empty
2140 from label is synonymous to 'begin', and empty to label is
2141 synonymous to the end of the command list.
2144 The following commands are executed by this synthesis command:
2147 hierarchy -check [-top <top> | -auto-top]
2151 flatten (if -flatten)
2157 memory_dff [-nordff]
2158 memory_memx (if -memx)
2168 \section{proc -- translate processes to netlists}
2170 \begin{lstlisting}[numbers=left,frame=single]
2171 proc [options] [selection]
2173 This pass calls all the other proc_* passes in the most common order.
2184 This replaces the processes in the design with multiplexers,
2185 flip-flops and latches.
2187 The following options are supported:
2189 -global_arst [!]<netname>
2190 This option is passed through to proc_arst.
2193 This option is passed through to proc_mux. proc_rmdead is not
2194 executed in -ifx mode.
2197 \section{proc\_arst -- detect asynchronous resets}
2198 \label{cmd:proc_arst}
2199 \begin{lstlisting}[numbers=left,frame=single]
2200 proc_arst [-global_arst [!]<netname>] [selection]
2202 This pass identifies asynchronous resets in the processes and converts them
2203 to a different internal representation that is suitable for generating
2204 flip-flop cells with asynchronous resets.
2206 -global_arst [!]<netname>
2207 In modules that have a net with the given name, use this net as async
2208 reset for registers that have been assign initial values in their
2209 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
2210 active low reset signals. Note: the frontend stores the default value
2211 in the 'init' attribute on the net.
2214 \section{proc\_clean -- remove empty parts of processes}
2215 \label{cmd:proc_clean}
2216 \begin{lstlisting}[numbers=left,frame=single]
2217 proc_clean [selection]
2219 This pass removes empty parts of processes and ultimately removes a process
2220 if it contains only empty structures.
2223 \section{proc\_dff -- extract flip-flops from processes}
2224 \label{cmd:proc_dff}
2225 \begin{lstlisting}[numbers=left,frame=single]
2226 proc_dff [selection]
2228 This pass identifies flip-flops in the processes and converts them to
2229 d-type flip-flop cells.
2232 \section{proc\_dlatch -- extract latches from processes}
2233 \label{cmd:proc_dlatch}
2234 \begin{lstlisting}[numbers=left,frame=single]
2235 proc_dlatch [selection]
2237 This pass identifies latches in the processes and converts them to
2241 \section{proc\_init -- convert initial block to init attributes}
2242 \label{cmd:proc_init}
2243 \begin{lstlisting}[numbers=left,frame=single]
2244 proc_init [selection]
2246 This pass extracts the 'init' actions from processes (generated from Verilog
2247 'initial' blocks) and sets the initial value to the 'init' attribute on the
2251 \section{proc\_mux -- convert decision trees to multiplexers}
2252 \label{cmd:proc_mux}
2253 \begin{lstlisting}[numbers=left,frame=single]
2254 proc_mux [options] [selection]
2256 This pass converts the decision trees in processes (originating from if-else
2257 and case statements) to trees of multiplexer cells.
2260 Use Verilog simulation behavior with respect to undef values in
2261 'case' expressions and 'if' conditions.
2264 \section{proc\_rmdead -- eliminate dead trees in decision trees}
2265 \label{cmd:proc_rmdead}
2266 \begin{lstlisting}[numbers=left,frame=single]
2267 proc_rmdead [selection]
2269 This pass identifies unreachable branches in decision trees and removes them.
2272 \section{qwp -- quadratic wirelength placer}
2274 \begin{lstlisting}[numbers=left,frame=single]
2275 qwp [options] [selection]
2277 This command runs quadratic wirelength placement on the selected modules and
2278 annotates the cells in the design with 'qwp_position' attributes.
2281 Add left-to-right constraints: constrain all inputs on the left border
2282 outputs to the right border.
2285 Add constraints for inputs/outputs to be placed in alphanumerical
2286 order along the y-axis (top-to-bottom).
2289 Number of grid divisions in x- and y-direction. (default=16)
2291 -dump <html_file_name>
2292 Dump a protocol of the placement algorithm to the html file.
2295 Verbose solver output for profiling or debugging
2297 Note: This implementation of a quadratic wirelength placer uses exact
2298 dense matrix operations. It is only a toy-placer for small circuits.
2301 \section{read -- load HDL designs}
2303 \begin{lstlisting}[numbers=left,frame=single]
2304 read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..
2306 Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support
2307 is only available via Verific.)
2309 Additional -D<macro>[=<value>] options may be added after the option indicating
2310 the language version (and before file names) to set additional verilog defines.
2313 read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
2315 Load the specified VHDL files. (Requires Verific.)
2318 read -define <macro>[=<value>]..
2320 Set global Verilog/SystemVerilog defines.
2323 read -undef <macro>..
2325 Unset global Verilog/SystemVerilog defines.
2328 read -incdir <directory>
2330 Add directory to global Verilog/SystemVerilog include directories.
2333 \section{read\_blif -- read BLIF file}
2334 \label{cmd:read_blif}
2335 \begin{lstlisting}[numbers=left,frame=single]
2336 read_blif [filename]
2338 Load modules from a BLIF file into the current design.
2341 Create $sop cells instead of $lut cells
2344 Merge ports that match the pattern 'name[int]' into a single
2345 multi-bit port 'name'.
2348 \section{read\_ilang -- read modules from ilang file}
2349 \label{cmd:read_ilang}
2350 \begin{lstlisting}[numbers=left,frame=single]
2351 read_ilang [filename]
2353 Load modules from an ilang file to the current design. (ilang is a text
2354 representation of a design in yosys's internal format.)
2357 \section{read\_json -- read JSON file}
2358 \label{cmd:read_json}
2359 \begin{lstlisting}[numbers=left,frame=single]
2360 read_json [filename]
2362 Load modules from a JSON file into the current design See "help write_json"
2363 for a description of the file format.
2366 \section{read\_liberty -- read cells from liberty file}
2367 \label{cmd:read_liberty}
2368 \begin{lstlisting}[numbers=left,frame=single]
2369 read_liberty [filename]
2371 Read cells from liberty file as modules into current design.
2374 only create empty blackbox modules
2377 ignore re-definitions of modules. (the default behavior is to
2378 create an error message if the existing module is not a blackbox
2379 module, and overwrite the existing module if it is a blackbox module.)
2382 overwrite existing modules with the same name
2385 ignore cells with missing function specification of outputs
2388 ignore cells with a missing or invalid direction
2389 specification on a pin
2391 -ignore_miss_data_latch
2392 ignore latches with missing data and/or enable pins
2394 -setattr <attribute_name>
2395 set the specified attribute (to the value 1) on all loaded modules
2398 \section{read\_verilog -- read modules from Verilog file}
2399 \label{cmd:read_verilog}
2400 \begin{lstlisting}[numbers=left,frame=single]
2401 read_verilog [options] [filename]
2403 Load modules from a Verilog file to the current design. A large subset of
2404 Verilog-2005 is supported.
2407 enable support for SystemVerilog features. (only a small subset
2408 of SystemVerilog is supported)
2411 enable support for SystemVerilog assertions and some Yosys extensions
2412 replace the implicit -D SYNTHESIS with -D FORMAL
2415 ignore restrict() assertions
2418 treat all assert() statements like assume() statements
2421 dump abstract syntax tree (before simplification)
2424 dump abstract syntax tree (after simplification)
2427 do not include hex memory addresses in dump (easier to diff dumps)
2430 dump ast as Verilog code (after simplification)
2433 dump generated RTLIL netlist
2436 enable parser debug output
2439 usually latches are synthesized into logic loops
2440 this option prohibits this and sets the output to 'x'
2441 in what would be the latches hold condition
2443 this behavior can also be achieved by setting the
2444 'nolatches' attribute on the respective module or
2448 under certain conditions memories are converted to registers
2449 early during simplification to ensure correct handling of
2450 complex corner cases. this option disables this behavior.
2452 this can also be achieved by setting the 'nomem2reg'
2453 attribute on the respective module or register.
2455 This is potentially dangerous. Usually the front-end has good
2456 reasons for converting an array to a list of registers.
2457 Prohibiting this step will likely result in incorrect synthesis
2461 always convert memories to registers. this can also be
2462 achieved by setting the 'mem2reg' attribute on the respective
2466 do not infer $meminit cells and instead convert initialized
2467 memories to registers directly in the front-end.
2470 dump Verilog code after pre-processor
2473 do not run the pre-processor
2476 disable DPI-C support
2479 only create empty blackbox modules. This implies -DBLACKBOX.
2482 don't perform basic optimizations (such as const folding) in the
2483 high-level front-end.
2486 interpret cell types starting with '$' as internal cell types
2489 ignore re-definitions of modules. (the default behavior is to
2490 create an error message if the existing module is not a black box
2491 module, and overwrite the existing module otherwise.)
2494 overwrite existing modules with the same name
2497 only read the abstract syntax tree and defer actual compilation
2498 to a later 'hierarchy' command. Useful in cases where the default
2499 parameters of modules yield invalid or not synthesizable code.
2502 make the default of `default_nettype be "none" instead of "wire".
2504 -setattr <attribute_name>
2505 set the specified attribute (to the value 1) on all loaded modules
2508 define the preprocessor symbol 'name' and set its optional value
2512 add 'dir' to the directories which are used when searching include
2515 The command 'verilog_defaults' can be used to register default options for
2516 subsequent calls to 'read_verilog'.
2518 Note that the Verilog frontend does a pretty good job of processing valid
2519 verilog input, but has not very good error reporting. It generally is
2520 recommended to use a simulator (for example Icarus Verilog) for checking
2521 the syntax of the code, rather than to rely on read_verilog for that.
2523 Depending on if read_verilog is run in -formal mode, either the macro
2524 SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog
2525 always defines the macro YOSYS.
2527 See the Yosys README file for a list of non-standard Verilog features
2528 supported by the Yosys Verilog front-end.
2531 \section{rename -- rename object in the design}
2533 \begin{lstlisting}[numbers=left,frame=single]
2534 rename old_name new_name
2536 Rename the specified object. Note that selection patterns are not supported
2540 rename -enumerate [-pattern <pattern>] [selection]
2542 Assign short auto-generated names to all selected wires and cells with private
2543 names. The -pattern option can be used to set the pattern for the new names.
2544 The character % in the pattern is replaced with a integer number. The default
2547 rename -hide [selection]
2549 Assign private names (the ones with $-prefix) to all selected wires and cells
2550 with public names. This ignores all selected ports.
2552 rename -top new_name
2557 \section{rmports -- remove module ports with no connections}
2559 \begin{lstlisting}[numbers=left,frame=single]
2562 This pass identifies ports in the selected modules which are not used or
2563 driven and removes them.
2566 \section{sat -- solve a SAT problem in the circuit}
2568 \begin{lstlisting}[numbers=left,frame=single]
2569 sat [options] [selection]
2571 This command solves a SAT problem defined over the currently selected circuit
2572 and additional constraints passed as parameters.
2575 show all solutions to the problem (this can grow exponentially, use
2576 -max <N> instead to get <N> solutions)
2579 like -all, but limit number of solutions to <N>
2582 enable modeling of undef value (aka 'x-bits')
2583 this option is implied by -set-def, -set-undef et. cetera
2586 maximize the number of undef bits in solutions, giving a better
2587 picture of which input bits are actually vital to the solution.
2589 -set <signal> <value>
2590 set the specified signal to the specified value.
2593 add a constraint that all bits of the given signal must be defined
2595 -set-any-undef <signal>
2596 add a constraint that at least one bit of the given signal is undefined
2598 -set-all-undef <signal>
2599 add a constraint that all bits of the given signal are undefined
2602 add -set-def constraints for all module inputs
2605 show the model for the specified signal. if no -show option is
2606 passed then a set of signals to be shown is automatically selected.
2608 -show-inputs, -show-outputs, -show-ports
2609 add all module (input/output) ports to the list of shown signals
2611 -show-regs, -show-public, -show-all
2612 show all registers, show signals with 'public' names, show all signals
2615 ignore all solutions that involve a division by zero
2617 -ignore_unknown_cells
2618 ignore all cells that can not be matched to a SAT model
2620 The following options can be used to set up a sequential problem:
2623 set up a sequential problem with <N> time steps. The steps will
2624 be numbered from 1 to N.
2626 note: for large <N> it can be significantly faster to use
2627 -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.
2629 -set-at <N> <signal> <value>
2630 -unset-at <N> <signal>
2631 set or unset the specified signal to the specified value in the
2632 given timestep. this has priority over a -set for the same signal.
2635 set all assumptions provided via $assume cells
2637 -set-def-at <N> <signal>
2638 -set-any-undef-at <N> <signal>
2639 -set-all-undef-at <N> <signal>
2640 add undef constraints in the given timestep.
2642 -set-init <signal> <value>
2643 set the initial value for the register driving the signal to the value
2646 set all initial states (not set using -set-init) to undef
2649 do not force a value for the initial state but do not allow undef
2652 set all initial states (not set using -set-init) to zero
2654 -dump_vcd <vcd-file-name>
2655 dump SAT model (counter example in proof) to VCD file
2657 -dump_json <json-file-name>
2658 dump SAT model (counter example in proof) to a WaveJSON file.
2660 -dump_cnf <cnf-file-name>
2661 dump CNF of SAT problem (in DIMACS format). in temporal induction
2662 proofs this is the CNF of the first induction step.
2664 The following additional options can be used to set up a proof. If also -seq
2665 is passed, a temporal induction proof is performed.
2668 Perform a temporal induction proof. In a temporal induction proof it is
2669 proven that the condition holds forever after the number of time steps
2670 specified using -seq.
2673 Perform a temporal induction proof. Assume an initial state with all
2674 registers set to defined values for the induction step.
2676 -tempinduct-baseonly
2677 Run only the basecase half of temporal induction (requires -maxsteps)
2679 -tempinduct-inductonly
2680 Run only the induction half of temporal induction
2682 -tempinduct-skip <N>
2683 Skip the first <N> steps of the induction proof.
2685 note: this will assume that the base case holds for <N> steps.
2686 this must be proven independently with "-tempinduct-baseonly
2687 -maxsteps <N>". Use -initsteps if you just want to set a
2688 minimal induction length.
2690 -prove <signal> <value>
2691 Attempt to proof that <signal> is always <value>.
2693 -prove-x <signal> <value>
2694 Like -prove, but an undef (x) bit in the lhs matches any value on
2695 the right hand side. Useful for equivalence checking.
2698 Prove that all asserts in the design hold.
2701 Do not enforce the prove-condition for the first <N> time steps.
2704 Set a maximum length for the induction.
2707 Set initial length for the induction.
2708 This will speed up the search of the right induction length
2709 for deep induction proofs.
2712 Increase the size of the induction proof in steps of <N>.
2713 This will speed up the search of the right induction length
2714 for deep induction proofs.
2717 Maximum number of seconds a single SAT instance may take.
2720 Return an error and stop the synthesis script if the proof fails.
2723 Like -verify but do not return an error for timeouts.
2726 Return an error and stop the synthesis script if the proof succeeds.
2729 Like -falsify but do not return an error for timeouts.
2732 \section{scatter -- add additional intermediate nets}
2734 \begin{lstlisting}[numbers=left,frame=single]
2737 This command adds additional intermediate nets on all cell ports. This is used
2738 for testing the correct use of the SigMap helper in passes. If you don't know
2739 what this means: don't worry -- you only need this pass when testing your own
2740 extensions to Yosys.
2742 Use the opt_clean command to get rid of the additional nets.
2745 \section{scc -- detect strongly connected components (logic loops)}
2747 \begin{lstlisting}[numbers=left,frame=single]
2748 scc [options] [selection]
2750 This command identifies strongly connected components (aka logic loops) in the
2754 expect to find exactly <num> SSCs. A different number of SSCs will
2758 limit to loops not longer than the specified number of cells. This
2759 can e.g. be useful in identifying small local loops in a module that
2760 implements one large SCC.
2763 do not count cells that have their output fed back into one of their
2764 inputs as single-cell scc.
2767 Usually this command only considers internal non-memory cells. With
2768 this option set, all cells are considered. For unknown cells all ports
2769 are assumed to be bidirectional 'inout' ports.
2771 -set_attr <name> <value>
2772 set the specified attribute on all cells that are part of a logic
2773 loop. the special token {} in the value is replaced with a unique
2774 identifier for the logic loop.
2777 replace the current selection with a selection of all cells and wires
2778 that are part of a found logic loop
2781 \section{script -- execute commands from script file}
2783 \begin{lstlisting}[numbers=left,frame=single]
2784 script <filename> [<from_label>:<to_label>]
2786 This command executes the yosys commands in the specified file.
2788 The 2nd argument can be used to only execute the section of the
2789 file between the specified labels. An empty from label is synonymous
2790 for the beginning of the file and an empty to label is synonymous
2791 for the end of the file.
2793 If only one label is specified (without ':') then only the block
2794 marked with that label (until the next label) is executed.
2797 \section{select -- modify and view the list of selected objects}
2799 \begin{lstlisting}[numbers=left,frame=single]
2800 select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
2801 select [ <assert_option> ] {-read <filename> | <selection>}
2802 select [ -list | -write <filename> | -count | -clear ]
2803 select -module <modname>
2805 Most commands use the list of currently selected objects to determine which part
2806 of the design to operate on. This command can be used to modify and view this
2807 list of selected objects.
2809 Note that many commands support an optional [selection] argument that can be
2810 used to YS_OVERRIDE the global selection for the command. The syntax of this
2811 optional argument is identical to the syntax of the <selection> argument
2815 add or remove the given objects to the current selection.
2816 without this options the current selection is replaced.
2819 do not modify the current selection. instead save the new selection
2820 under the given name (see @<name> below). to save the current selection,
2821 use "select -set <name> %"
2824 do not modify the current selection. instead assert that the given
2825 selection is empty. i.e. produce an error if any object matching the
2829 do not modify the current selection. instead assert that the given
2830 selection is non-empty. i.e. produce an error if no object matching
2831 the selection is found.
2834 do not modify the current selection. instead assert that the given
2835 selection contains exactly N objects.
2838 do not modify the current selection. instead assert that the given
2839 selection contains less than or exactly N objects.
2842 do not modify the current selection. instead assert that the given
2843 selection contains at least N objects.
2846 list all objects in the current selection
2849 like -list but write the output to the specified file
2852 read the specified file (written by -write)
2855 count all objects in the current selection
2858 clear the current selection. this effectively selects the whole
2859 design. it also resets the selected module (see -module). use the
2860 command 'select *' to select everything but stay in the current module.
2863 create an empty selection. the current module is unchanged.
2866 limit the current scope to the specified module.
2867 the difference between this and simply selecting the module
2868 is that all object names are interpreted relative to this
2869 module after this command until the selection is cleared again.
2871 When this command is called without an argument, the current selection
2872 is displayed in a compact form (i.e. only the module name when a whole module
2875 The <selection> argument itself is a series of commands for a simple stack
2876 machine. Each element on the stack represents a set of selected objects.
2877 After this commands have been executed, the union of all remaining sets
2878 on the stack is computed and used as selection for the command.
2880 Pushing (selecting) object when not in -module mode:
2883 select the specified module(s)
2885 <mod_pattern>/<obj_pattern>
2886 select the specified object(s) from the module(s)
2888 Pushing (selecting) object when in -module mode:
2891 select the specified object(s) from the current module
2893 A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
2894 matching module names, or one of the following:
2896 A:<pattern>, A:<pattern>=<pattern>
2897 all modules with an attribute matching the given pattern
2898 in addition to = also <, <=, >=, and > are supported
2900 An <obj_pattern> can be an object name, wildcard expression, or one of
2904 all wires with a name matching the given wildcard pattern
2906 i:<pattern>, o:<pattern>, x:<pattern>
2907 all inputs (i:), outputs (o:) or any ports (x:) with matching names
2909 s:<size>, s:<min>:<max>
2910 all wires with a matching width
2913 all memories with a name matching the given pattern
2916 all cells with a name matching the given pattern
2919 all cells with a type matching the given pattern
2922 all processes with a name matching the given pattern
2925 all objects with an attribute name matching the given pattern
2927 a:<pattern>=<pattern>
2928 all objects with a matching attribute name-value-pair.
2929 in addition to = also <, <=, >=, and > are supported
2931 r:<pattern>, r:<pattern>=<pattern>
2932 cells with matching parameters. also with <, <=, >= and >.
2935 all objects with a name matching the given pattern
2936 (i.e. 'n:' is optional as it is the default matching rule)
2939 push the selection saved prior with 'select -set <name> ...'
2941 The following actions can be performed on the top sets on the stack:
2944 push a copy of the current selection to the stack
2947 replace the stack with a union of all elements on it
2950 replace top set with its invert
2953 replace the two top sets on the stack with their union
2956 replace the two top sets on the stack with their intersection
2959 pop the top set from the stack and subtract it from the new top
2962 like %d but swap the roles of two top sets on the stack
2965 create a copy of the top set from the stack and push it
2967 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2968 expand top set <num1> num times according to the specified rules.
2969 (i.e. select all cells connected to selected wires and select all
2970 wires connected to selected cells) The rules specify which cell
2971 ports to use for this. the syntax for a rule is a '-' for exclusion
2972 and a '+' for inclusion, followed by an optional comma separated
2973 list of cell types followed by an optional comma separated list of
2974 cell ports in square brackets. a rule can also be just a cell or wire
2975 name that limits the expansion (is included but does not go beyond).
2976 select at most <num2> objects. a warning message is printed when this
2977 limit is reached. When '*' is used instead of <num1> then the process
2978 is repeated until no further object are selected.
2980 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2981 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2982 similar to %x, but only select input (%ci) or output cones (%co)
2984 %xe[...] %cie[...] %coe
2985 like %x, %ci, and %co but only consider combinatorial cells
2988 expand top set by selecting all wires that are (at least in part)
2989 aliases for selected wires.
2992 expand top set by adding all modules that implement cells in selected
2996 expand top set by selecting all modules that contain selected objects
2999 select modules that implement selected cells
3002 select cells that implement selected modules
3005 select <num> random objects from top selection (default 1)
3007 Example: the following command selects all wires that are connected to a
3008 'GATE' input of a 'SWITCH' cell:
3010 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
3013 \section{setattr -- set/unset attributes on objects}
3015 \begin{lstlisting}[numbers=left,frame=single]
3016 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
3018 Set/unset the given attributes on the selected objects. String values must be
3019 passed in double quotes (").
3021 When called with -mod, this command will set and unset attributes on modules
3022 instead of objects within modules.
3025 \section{setparam -- set/unset parameters on objects}
3026 \label{cmd:setparam}
3027 \begin{lstlisting}[numbers=left,frame=single]
3028 setparam [ -type cell_type ] [ -set name value | -unset name ]... [selection]
3030 Set/unset the given parameters on the selected cells. String values must be
3031 passed in double quotes (").
3033 The -type option can be used to change the cell type of the selected cells.
3036 \section{setundef -- replace undef values with defined constants}
3037 \label{cmd:setundef}
3038 \begin{lstlisting}[numbers=left,frame=single]
3039 setundef [options] [selection]
3041 This command replaces undef (x) constants with defined (0/1) constants.
3044 also set undriven nets to constant values
3047 also expose undriven nets as inputs (use with -undriven)
3050 replace with bits cleared (0)
3053 replace with bits set (1)
3056 replace with undef (x) bits, may be used with -undriven
3059 replace with $anyseq drivers (for formal)
3062 replace with $anyconst drivers (for formal)
3065 replace with random bits using the specified integer als seed
3066 value for the random number generator.
3069 also create/update init values for flip-flops
3072 \section{share -- perform sat-based resource sharing}
3074 \begin{lstlisting}[numbers=left,frame=single]
3075 share [options] [selection]
3077 This pass merges shareable resources into a single resource. A SAT solver
3078 is used to determine if two resources are share-able.
3081 Per default the selection of cells that is considered for sharing is
3082 narrowed using a list of cell types. With this option all selected
3083 cells are considered for resource sharing.
3085 IMPORTANT NOTE: If the -all option is used then no cells with internal
3086 state must be selected!
3089 Per default some heuristics are used to reduce the number of cells
3090 considered for resource sharing to only large resources. This options
3091 turns this heuristics off, resulting in much more cells being considered
3092 for resource sharing.
3095 Only consider the simple part of the control logic in SAT solving, resulting
3096 in much easier SAT problems at the cost of maybe missing some opportunities
3097 for resource sharing.
3100 Only perform the first N merges, then stop. This is useful for debugging.
3103 \section{shell -- enter interactive command mode}
3105 \begin{lstlisting}[numbers=left,frame=single]
3108 This command enters the interactive command mode. This can be useful
3109 in a script to interrupt the script at a certain point and allow for
3110 interactive inspection or manual synthesis of the design at this point.
3112 The command prompt of the interactive shell indicates the current
3113 selection (see 'help select'):
3116 the entire design is selected
3119 only part of the design is selected
3122 the entire module 'modname' is selected using 'select -module modname'
3125 only part of current module 'modname' is selected
3127 When in interactive shell, some errors (e.g. invalid command arguments)
3128 do not terminate yosys but return to the command prompt.
3130 This command is the default action if nothing else has been specified
3131 on the command line.
3133 Press Ctrl-D or type 'exit' to leave the interactive shell.
3136 \section{show -- generate schematics using graphviz}
3138 \begin{lstlisting}[numbers=left,frame=single]
3139 show [options] [selection]
3141 Create a graphviz DOT file for the selected part of the design and compile it
3142 to a graphics file (usually SVG or PostScript).
3145 Run the specified command with the graphics file as parameter.
3146 On Windows, this pauses yosys until the viewer exits.
3149 Generate a graphics file in the specified format. Use 'dot' to just
3150 generate a .dot file, or other <format> strings such as 'svg' or 'ps'
3151 to generate files in other formats (this calls the 'dot' command).
3153 -lib <verilog_or_ilang_file>
3154 Use the specified library file for determining whether cell ports are
3155 inputs or outputs. This option can be used multiple times to specify
3156 more than one library.
3158 note: in most cases it is better to load the library before calling
3159 show with 'read_verilog -lib <filename>'. it is also possible to
3160 load liberty files with 'read_liberty -lib <filename>'.
3163 generate <prefix>.* instead of ~/.yosys_show.*
3165 -color <color> <object>
3166 assign the specified color to the specified object. The object can be
3167 a single selection wildcard expressions or a saved set of objects in
3168 the @<name> syntax (see "help select" for details).
3170 -label <text> <object>
3171 assign the specified label text to the specified object. The object can
3172 be a single selection wildcard expressions or a saved set of objects in
3173 the @<name> syntax (see "help select" for details).
3176 Randomly assign colors to the wires. The integer argument is the seed
3177 for the random number generator. Change the seed value if the colored
3178 graph still is ambiguous. A seed of zero deactivates the coloring.
3180 -colorattr <attribute_name>
3181 Use the specified attribute to assign colors. A unique color is
3182 assigned to each unique value of this attribute.
3185 annotate busses with a label indicating the width of the bus.
3188 mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
3189 cell parameter) with an asterisk next to the port name.
3192 stretch the graph so all inputs are on the left side and all outputs
3193 (including inout ports) are on the right side.
3196 wait for the use to press enter to before returning
3199 enumerate objects with internal ($-prefixed) names
3202 do not abbreviate objects with internal ($-prefixed) names
3205 do not add the module name as graph title to the dot file
3207 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
3208 specified, 'xdot' is used to display the schematic (POSIX systems only).
3210 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
3211 unless another prefix is specified using -prefix <prefix>.
3213 Yosys on Windows and YosysJS use different defaults: The output is written
3214 to 'show.dot' in the current directory and new viewer is launched each time
3215 the 'show' command is executed.
3218 \section{shregmap -- map shift registers}
3219 \label{cmd:shregmap}
3220 \begin{lstlisting}[numbers=left,frame=single]
3221 shregmap [options] [selection]
3223 This pass converts chains of $_DFF_[NP]_ gates to target specific shift register
3224 primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and
3225 will use the same interface as the original $_DFF_*_ cells. The cell parameter
3226 'DEPTH' will contain the depth of the shift register. Use a target-specific
3227 'techmap' map file to convert those cells to the actual target cells.
3230 minimum length of shift register (default = 2)
3231 (this is the length after -keep_before and -keep_after)
3234 maximum length of shift register (default = no limit)
3235 larger chains will be mapped to multiple shift register instances
3238 number of DFFs to keep before the shift register (default = 0)
3241 number of DFFs to keep after the shift register (default = 0)
3244 limit match to only positive or negative edge clocks. (default = any)
3246 -enpol pos|neg|none|any_or_none|any
3247 limit match to FFs with the specified enable polarity. (default = none)
3249 -match <cell_type>[:<d_port_name>:<q_port_name>]
3250 match the specified cells instead of $_DFF_N_ and $_DFF_P_. If
3251 ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used
3252 by default. E.g. the option '-clkpol pos' is just an alias for
3253 '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.
3256 instead of encoding the clock and enable polarity in the cell name by
3257 deriving from the original cell name, simply name all generated cells
3258 $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is
3259 used to denote cells without enable input. The ENPOL parameter is
3260 omitted when '-enpol none' (or no -enpol option) is passed.
3263 assume the shift register is automatically zero-initialized, so it
3264 becomes legal to merge zero initialized FFs into the shift register.
3267 map initialized registers to the shift reg, add an INIT parameter to
3268 generated cells with the initialization value. (first bit to shift out
3272 map to greenpak4 shift registers.
3275 \section{sim -- simulate the circuit}
3277 \begin{lstlisting}[numbers=left,frame=single]
3278 sim [options] [top-level]
3280 This command simulates the circuit using the given top-level module.
3283 write the simulation results to the given VCD file
3286 name of top-level clock input
3289 name of top-level clock input (inverse polarity)
3292 name of top-level reset input (active high)
3295 name of top-level inverted reset input (active low)
3298 number of cycles reset should stay active (default: 1)
3301 zero-initialize all uninitialized regs and memories
3304 number of cycles to simulate (default: 20)
3307 include all nets in VCD output, not just those with public names
3310 writeback mode: use final simulation state as new init state
3316 \section{simplemap -- mapping simple coarse-grain cells}
3317 \label{cmd:simplemap}
3318 \begin{lstlisting}[numbers=left,frame=single]
3319 simplemap [selection]
3321 This pass maps a small selection of simple coarse-grain cells to yosys gate
3322 primitives. The following internal cell types are mapped by this pass:
3324 $not, $pos, $and, $or, $xor, $xnor
3325 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
3326 $logic_not, $logic_and, $logic_or, $mux, $tribuf
3327 $sr, $ff, $dff, $dffsr, $adff, $dlatch
3330 \section{splice -- create explicit splicing cells}
3332 \begin{lstlisting}[numbers=left,frame=single]
3333 splice [options] [selection]
3335 This command adds $slice and $concat cells to the design to make the splicing
3336 of multi-bit signals explicit. This for example is useful for coarse grain
3337 synthesis, where dedicated hardware is needed to splice signals.
3340 only select the cell ports to rewire by the cell. if the selection
3341 contains a cell, than all cell inputs are rewired, if necessary.
3344 only select the cell ports to rewire by the wire. if the selection
3345 contains a wire, than all cell ports driven by this wire are wired,
3349 it is sufficient if the driver of any bit of a cell port is selected.
3350 by default all bits must be selected.
3353 also add $slice and $concat cells to drive otherwise unused wires.
3356 do not rewire selected module outputs.
3359 only rewire cell ports with the specified name. can be used multiple
3360 times. implies -no_output.
3363 do not rewire cell ports with the specified name. can be used multiple
3364 times. can not be combined with -port <name>.
3366 By default selected output wires and all cell ports of selected cells driven
3367 by selected wires are rewired.
3370 \section{splitnets -- split up multi-bit nets}
3371 \label{cmd:splitnets}
3372 \begin{lstlisting}[numbers=left,frame=single]
3373 splitnets [options] [selection]
3375 This command splits multi-bit nets into single-bit nets.
3377 -format char1[char2[char3]]
3378 the first char is inserted between the net name and the bit index, the
3379 second char is appended to the netname. e.g. -format () creates net
3380 names like 'mysignal(42)'. the 3rd character is the range separation
3381 character when creating multi-bit wires. the default is '[]:'.
3384 also split module ports. per default only internal signals are split.
3387 don't blindly split nets in individual bits. instead look at the driver
3388 and split nets so that no driver drives only part of a net.
3391 \section{stat -- print some statistics}
3393 \begin{lstlisting}[numbers=left,frame=single]
3394 stat [options] [selection]
3396 Print some statistics (number of objects) on the selected portion of the
3400 print design hierarchy with this module as top. if the design is fully
3401 selected and a module has the 'top' attribute set, this module is used
3402 default value for this option.
3404 -liberty <liberty_file>
3405 use cell area information from the provided liberty file
3408 annotate internal cell types with their word width.
3409 e.g. $add_8 for an 8 bit wide $add cell.
3412 \section{submod -- moving part of a module to a new submodule}
3414 \begin{lstlisting}[numbers=left,frame=single]
3415 submod [-copy] [selection]
3417 This pass identifies all cells with the 'submod' attribute and moves them to
3418 a newly created module. The value of the attribute is used as name for the
3419 cell that replaces the group of cells with the same attribute value.
3421 This pass can be used to create a design hierarchy in flat design. This can
3422 be useful for analyzing or reverse-engineering a design.
3424 This pass only operates on completely selected modules with no processes
3428 submod -name <name> [-copy] [selection]
3430 As above, but don't use the 'submod' attribute but instead use the selection.
3431 Only objects from one module might be selected. The value of the -name option
3432 is used as the value of the 'submod' attribute above.
3434 By default the cells are 'moved' from the source module and the source module
3435 will use an instance of the new module after this command is finished. Call
3436 with -copy to not modify the source module.
3439 \section{synth -- generic synthesis script}
3441 \begin{lstlisting}[numbers=left,frame=single]
3444 This command runs the default synthesis script. This command does not operate
3445 on partly selected designs.
3448 use the specified module as top module (default='top')
3451 automatically determine the top of the design hierarchy
3454 flatten the design before synthesis. this will pass '-auto-top' to
3455 'hierarchy' if no top module is specified.
3458 passed to 'fsm_recode' via 'fsm'
3461 do not run FSM optimization
3464 do not run abc (as if yosys was compiled without ABC support)
3467 do not run 'alumacc' pass. i.e. keep arithmetic operators in
3468 their direct form ($add, $sub, etc.).
3471 passed to 'memory'. prohibits merging of FFs into memory read ports
3474 do not run SAT-based resource sharing
3476 -run <from_label>[:<to_label>]
3477 only run the commands between the labels (see below). an empty
3478 from label is synonymous to 'begin', and empty to label is
3479 synonymous to the end of the command list.
3482 The following commands are executed by this synthesis command:
3485 hierarchy -check [-top <top> | -auto-top]
3489 flatten (if -flatten)
3518 \section{synth\_achronix -- synthesis for Acrhonix Speedster22i FPGAs.}
3519 \label{cmd:synth_achronix}
3520 \begin{lstlisting}[numbers=left,frame=single]
3521 synth_achronix [options]
3523 This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.
3526 use the specified module as top module (default='top')
3529 write the design to the specified Verilog netlist file. writing of an
3530 output file is omitted if this parameter is not specified.
3532 -run <from_label>:<to_label>
3533 only run the commands between the labels (see below). an empty
3534 from label is synonymous to 'begin', and empty to label is
3535 synonymous to the end of the command list.
3538 do not flatten design before synthesis
3541 run 'abc' with -dff option
3544 The following commands are executed by this synthesis command:
3547 read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v
3548 hierarchy -check -top <top>
3550 flatten: (unless -noflatten)
3560 opt -fast -mux_undef -undriven -fine -full
3564 dff2dffe -direct-match $_DFF_*
3566 techmap -map +/techmap.v
3569 setundef -undriven -zero
3570 abc -markgroups -dff (only if -retime)
3577 iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I
3578 techmap -map +/achronix/speedster22i/cells_map.v
3587 write_verilog -nodec -attr2comment -defparam -renameprefix syn_ <file-name>
3590 \section{synth\_coolrunner2 -- synthesis for Xilinx Coolrunner-II CPLDs}
3591 \label{cmd:synth_coolrunner2}
3592 \begin{lstlisting}[numbers=left,frame=single]
3593 synth_coolrunner2 [options]
3595 This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.
3596 It is intended to be used with https://github.com/azonenberg/openfpga as the
3600 use the specified module as top module (default='top')
3603 write the design to the specified JSON file. writing of an output file
3604 is omitted if this parameter is not specified.
3606 -run <from_label>:<to_label>
3607 only run the commands between the labels (see below). an empty
3608 from label is synonymous to 'begin', and empty to label is
3609 synonymous to the end of the command list.
3612 do not flatten design before synthesis
3615 run 'abc' with -dff option
3618 The following commands are executed by this synthesis command:
3621 read_verilog -lib +/coolrunner2/cells_sim.v
3622 hierarchy -check -top <top>
3624 flatten: (unless -noflatten)
3635 techmap -map +/coolrunner2/cells_latch.v
3636 dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib
3641 extract -map +/coolrunner2/tff_extract.v
3644 abc -sop -I 40 -P 56
3648 dfflibmap -liberty +/coolrunner2/xc2_dff.lib
3649 dffinit -ff FDCP Q INIT
3650 dffinit -ff FDCP_N Q INIT
3651 dffinit -ff FTCP Q INIT
3652 dffinit -ff FTCP_N Q INIT
3653 dffinit -ff LDCP Q INIT
3654 dffinit -ff LDCP_N Q INIT
3656 iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO
3657 attrmvcp -attr src -attr LOC t:IOBUFE n:*
3658 attrmvcp -attr src -attr LOC -driven t:IBUF n:*
3668 write_json <file-name>
3671 \section{synth\_easic -- synthesis for eASIC platform}
3672 \label{cmd:synth_easic}
3673 \begin{lstlisting}[numbers=left,frame=single]
3674 synth_easic [options]
3676 This command runs synthesis for eASIC platform.
3679 use the specified module as top module
3682 write the design to the specified structural Verilog file. writing of
3683 an output file is omitted if this parameter is not specified.
3686 set path to the eTools installation. (default=/opt/eTools)
3688 -run <from_label>:<to_label>
3689 only run the commands between the labels (see below). an empty
3690 from label is synonymous to 'begin', and empty to label is
3691 synonymous to the end of the command list.
3694 do not flatten design before synthesis
3697 run 'abc' with -dff option
3700 The following commands are executed by this synthesis command:
3703 read_liberty -lib <etools_phys_clk_lib>
3704 read_liberty -lib <etools_logic_lut_lib>
3705 hierarchy -check -top <top>
3707 flatten: (unless -noflatten)
3715 opt -fast -mux_undef -undriven -fine
3720 abc -dff (only if -retime)
3721 opt_clean (only if -retime)
3724 dfflibmap -liberty <etools_phys_clk_lib>
3725 abc -liberty <etools_logic_lut_lib>
3734 write_verilog -noexpr -attr2comment <file-name>
3737 \section{synth\_ecp5 -- synthesis for ECP5 FPGAs}
3738 \label{cmd:synth_ecp5}
3739 \begin{lstlisting}[numbers=left,frame=single]
3740 synth_ecp5 [options]
3742 This command runs synthesis for ECP5 FPGAs.
3745 use the specified module as top module
3748 write the design to the specified BLIF file. writing of an output file
3749 is omitted if this parameter is not specified.
3752 write the design to the specified EDIF file. writing of an output file
3753 is omitted if this parameter is not specified.
3756 write the design to the specified JSON file. writing of an output file
3757 is omitted if this parameter is not specified.
3759 -run <from_label>:<to_label>
3760 only run the commands between the labels (see below). an empty
3761 from label is synonymous to 'begin', and empty to label is
3762 synonymous to the end of the command list.
3765 do not flatten design before synthesis
3768 run 'abc' with -dff option
3771 do not use CCU2 cells in output netlist
3774 do not use flipflops with CE in output netlist
3777 do not use BRAM cells in output netlist
3780 do not use distributed RAM cells in output netlist
3783 do not use PFU muxes to implement LUTs larger than LUT4s
3786 run two passes of 'abc' for slightly improved logic density
3789 generate an output netlist (and BLIF file) suitable for VPR
3790 (this feature is experimental and incomplete)
3793 The following commands are executed by this synthesis command:
3796 read_verilog -lib +/ecp5/cells_sim.v
3797 hierarchy -check -top <top>
3799 flatten: (unless -noflatten)
3808 bram: (skip if -nobram)
3810 dram: (skip if -nodram)
3811 memory_bram -rules +/ecp5/dram.txt
3812 techmap -map +/ecp5/drams_map.v
3815 opt -fast -mux_undef -undriven -fine
3818 techmap -map +/techmap.v -map +/ecp5/arith_map.v
3819 abc -dff (only if -retime)
3825 dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
3826 techmap -D NO_LUT -map +/ecp5/cells_map.v
3836 techmap -map +/ecp5/cells_map.v (with -D NO_LUT in vpr mode)
3845 opt_clean -purge (vpr mode)
3846 write_blif -attr -cname -conn -param <file-name> (vpr mode)
3847 write_blif -gates -attr -param <file-name> (non-vpr mode)
3850 write_edif <file-name>
3853 write_json <file-name>
3856 \section{synth\_gowin -- synthesis for Gowin FPGAs}
3857 \label{cmd:synth_gowin}
3858 \begin{lstlisting}[numbers=left,frame=single]
3859 synth_gowin [options]
3861 This command runs synthesis for Gowin FPGAs. This work is experimental.
3864 use the specified module as top module (default='top')
3867 write the design to the specified Verilog netlist file. writing of an
3868 output file is omitted if this parameter is not specified.
3870 -run <from_label>:<to_label>
3871 only run the commands between the labels (see below). an empty
3872 from label is synonymous to 'begin', and empty to label is
3873 synonymous to the end of the command list.
3876 run 'abc' with -dff option
3879 The following commands are executed by this synthesis command:
3882 read_verilog -lib +/gowin/cells_sim.v
3883 hierarchy -check -top <top>
3895 opt -fast -mux_undef -undriven -fine
3901 setundef -undriven -zero
3902 abc -dff (only if -retime)
3909 techmap -map +/gowin/cells_map.v
3910 hilomap -hicell VCC V -locell GND G
3911 iopadmap -inpad IBUF O:I -outpad OBUF I:O
3920 write_verilog -nodec -attr2comment -defparam -renameprefix gen <file-name>
3923 \section{synth\_greenpak4 -- synthesis for GreenPAK4 FPGAs}
3924 \label{cmd:synth_greenpak4}
3925 \begin{lstlisting}[numbers=left,frame=single]
3926 synth_greenpak4 [options]
3928 This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
3929 It is intended to be used with https://github.com/azonenberg/openfpga as the
3933 use the specified module as top module (default='top')
3936 synthesize for the specified part. Valid values are SLG46140V,
3937 SLG46620V, and SLG46621V (default).
3940 write the design to the specified JSON file. writing of an output file
3941 is omitted if this parameter is not specified.
3943 -run <from_label>:<to_label>
3944 only run the commands between the labels (see below). an empty
3945 from label is synonymous to 'begin', and empty to label is
3946 synonymous to the end of the command list.
3949 do not flatten design before synthesis
3952 run 'abc' with -dff option
3955 The following commands are executed by this synthesis command:
3958 read_verilog -lib +/greenpak4/cells_sim.v
3959 hierarchy -check -top <top>
3961 flatten: (unless -noflatten)
3970 extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14
3972 opt -fast -mux_undef -undriven -fine
3976 techmap -map +/greenpak4/cells_latch.v
3977 dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
3979 abc -dff (only if -retime)
3982 nlutmap -assert -luts 0,6,8,2 (for -part SLG46140V)
3983 nlutmap -assert -luts 2,8,16,2 (for -part SLG46620V)
3984 nlutmap -assert -luts 2,8,16,2 (for -part SLG46621V)
3988 shregmap -tech greenpak4
3989 dfflibmap -liberty +/greenpak4/gp_dff.lib
3990 dffinit -ff GP_DFF Q INIT
3991 dffinit -ff GP_DFFR Q INIT
3992 dffinit -ff GP_DFFS Q INIT
3993 dffinit -ff GP_DFFSR Q INIT
3994 iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO
3995 attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*
3996 attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*
3997 techmap -map +/greenpak4/cells_map.v
4007 write_json <file-name>
4010 \section{synth\_ice40 -- synthesis for iCE40 FPGAs}
4011 \label{cmd:synth_ice40}
4012 \begin{lstlisting}[numbers=left,frame=single]
4013 synth_ice40 [options]
4015 This command runs synthesis for iCE40 FPGAs.
4018 use the specified module as top module
4021 write the design to the specified BLIF file. writing of an output file
4022 is omitted if this parameter is not specified.
4025 write the design to the specified EDIF file. writing of an output file
4026 is omitted if this parameter is not specified.
4029 write the design to the specified JSON file. writing of an output file
4030 is omitted if this parameter is not specified.
4032 -run <from_label>:<to_label>
4033 only run the commands between the labels (see below). an empty
4034 from label is synonymous to 'begin', and empty to label is
4035 synonymous to the end of the command list.
4038 do not flatten design before synthesis
4041 run 'abc' with -dff option
4044 do not use SB_CARRY cells in output netlist
4047 do not use SB_DFFE* cells in output netlist
4050 do not use SB_RAM40_4K* cells in output netlist
4053 run two passes of 'abc' for slightly improved logic density
4056 generate an output netlist (and BLIF file) suitable for VPR
4057 (this feature is experimental and incomplete)
4060 The following commands are executed by this synthesis command:
4063 read_verilog -lib +/ice40/cells_sim.v
4064 hierarchy -check -top <top>
4066 flatten: (unless -noflatten)
4075 bram: (skip if -nobram)
4076 memory_bram -rules +/ice40/brams.txt
4077 techmap -map +/ice40/brams_map.v
4080 opt -fast -mux_undef -undriven -fine
4083 techmap -map +/techmap.v -map +/ice40/arith_map.v
4084 abc -dff (only if -retime)
4089 dff2dffe -direct-match $_DFF_*
4090 techmap -D NO_LUT -map +/ice40/cells_map.v
4099 ice40_opt (only if -abc2)
4100 techmap -map +/ice40/latches_map.v
4105 techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode)
4114 opt_clean -purge (vpr mode)
4115 write_blif -attr -cname -conn -param <file-name> (vpr mode)
4116 write_blif -gates -attr -param <file-name> (non-vpr mode)
4119 write_edif <file-name>
4122 write_json <file-name>
4125 \section{synth\_intel -- synthesis for Intel (Altera) FPGAs.}
4126 \label{cmd:synth_intel}
4127 \begin{lstlisting}[numbers=left,frame=single]
4128 synth_intel [options]
4130 This command runs synthesis for Intel FPGAs.
4132 -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>
4133 generate the synthesis netlist for the specified family.
4134 MAX10 is the default target if not family argument specified.
4135 For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.
4136 Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.
4139 use the specified module as top module (default='top')
4142 write the design to the specified Verilog Quartus Mapping File. Writing of an
4143 output file is omitted if this parameter is not specified.
4146 write BLIF files for VPR flow experiments. The synthesized BLIF output file is not
4147 compatible with the Quartus flow. Writing of an
4148 output file is omitted if this parameter is not specified.
4150 -run <from_label>:<to_label>
4151 only run the commands between the labels (see below). an empty
4152 from label is synonymous to 'begin', and empty to label is
4153 synonymous to the end of the command list.
4156 do not use altsyncram cells in output netlist
4159 do not use altsyncram cells in output netlist
4162 do not flatten design before synthesis
4165 run 'abc' with -dff option
4167 The following commands are executed by this synthesis command:
4172 read_verilog -sv -lib +/intel/max10/cells_sim.v
4173 read_verilog -sv -lib +/intel/common/m9k_bb.v
4174 read_verilog -sv -lib +/intel/common/altpll_bb.v
4175 hierarchy -check -top <top>
4177 flatten: (unless -noflatten)
4186 bram: (skip if -nobram)
4187 memory_bram -rules +/intel/common/brams.txt
4188 techmap -map +/intel/common/brams_map.v
4191 opt -fast -mux_undef -undriven -fine -full
4195 dff2dffe -direct-match $_DFF_*
4197 techmap -map +/techmap.v
4200 setundef -undriven -zero
4201 abc -markgroups -dff (only if -retime)
4208 iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I (unless -noiopads)
4209 techmap -map +/intel/max10/cells_map.v
4210 dffinit -highlow -ff dffeas q power_up
4219 write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ <file-name>
4223 write_blif <file-name>
4226 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
4227 \label{cmd:synth_xilinx}
4228 \begin{lstlisting}[numbers=left,frame=single]
4229 synth_xilinx [options]
4231 This command runs synthesis for Xilinx FPGAs. This command does not operate on
4232 partly selected designs. At the moment this command creates netlists that are
4233 compatible with 7-Series Xilinx devices.
4236 use the specified module as top module
4239 write the design to the specified edif file. writing of an output file
4240 is omitted if this parameter is not specified.
4243 write the design to the specified BLIF file. writing of an output file
4244 is omitted if this parameter is not specified.
4247 generate an output netlist (and BLIF file) suitable for VPR
4248 (this feature is experimental and incomplete)
4250 -run <from_label>:<to_label>
4251 only run the commands between the labels (see below). an empty
4252 from label is synonymous to 'begin', and empty to label is
4253 synonymous to the end of the command list.
4256 flatten design before synthesis
4259 run 'abc' with -dff option
4262 The following commands are executed by this synthesis command:
4265 read_verilog -lib +/xilinx/cells_sim.v
4266 read_verilog -lib +/xilinx/cells_xtra.v
4267 read_verilog -lib +/xilinx/brams_bb.v
4268 hierarchy -check -top <top>
4270 flatten: (only if -flatten)
4278 memory_bram -rules +/xilinx/brams.txt
4279 techmap -map +/xilinx/brams_map.v
4282 memory_bram -rules +/xilinx/drams.txt
4283 techmap -map +/xilinx/drams_map.v
4291 techmap -map +/techmap.v -map +/xilinx/arith_map.v
4295 abc -luts 2:2,3,6:5,10,20 [-dff]
4299 techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
4300 dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
4308 edif: (only if -edif)
4309 write_edif <file-name>
4311 blif: (only if -blif)
4312 write_blif <file-name>
4315 \section{tcl -- execute a TCL script file}
4317 \begin{lstlisting}[numbers=left,frame=single]
4320 This command executes the tcl commands in the specified file.
4321 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
4323 The tcl command 'yosys -import' can be used to import all yosys
4324 commands directly as tcl commands to the tcl shell. Yosys commands
4325 'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'
4326 in order to avoid a name collision with the built in commands.
4329 \section{techmap -- generic technology mapper}
4331 \begin{lstlisting}[numbers=left,frame=single]
4332 techmap [-map filename] [selection]
4334 This pass implements a very simple technology mapper that replaces cells in
4335 the design with implementations given in form of a Verilog or ilang source
4339 the library of cell implementations to be used.
4340 without this parameter a builtin library is used that
4341 transforms the internal RTL cells to the internal gate
4345 like -map above, but with an in-memory design instead of a file.
4348 load the cell implementations as separate modules into the design
4349 instead of inlining them.
4352 only run the specified number of iterations.
4355 instead of the iterative breadth-first algorithm use a recursive
4356 depth-first algorithm. both methods should yield equivalent results,
4357 but may differ in performance.
4360 Automatically call "proc" on implementations that contain processes.
4363 this option will cause techmap to exit with an error if it can't map
4364 a selected cell. only cell types that end on an underscore are accepted
4365 as final cell types by this mode.
4367 -D <define>, -I <incdir>
4368 this options are passed as-is to the Verilog frontend for loading the
4369 map file. Note that the Verilog frontend is also called with the
4370 '-nooverwrite' option set.
4372 When a module in the map file has the 'techmap_celltype' attribute set, it will
4373 match cells with a type that match the text value of this attribute. Otherwise
4374 the module name will be used to match the cell.
4376 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
4377 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
4379 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
4380 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
4382 When a module in the map file has the 'techmap_wrap' attribute set, techmap
4383 will create a wrapper for the cell and then run the command string that the
4384 attribute is set to on the wrapper module.
4386 All wires in the modules from the map file matching the pattern _TECHMAP_*
4387 or *._TECHMAP_* are special wires that are used to pass instructions from
4388 the mapping module to the techmap command. At the moment the following special
4389 wires are supported:
4392 When this wire is set to a non-zero constant value, techmap will not
4393 use this module and instead try the next module with a matching
4394 'techmap_celltype' attribute.
4396 When such a wire exists but does not have a constant value after all
4397 _TECHMAP_DO_* commands have been executed, an error is generated.
4400 This wires are evaluated in alphabetical order. The constant text value
4401 of this wire is a yosys command (or sequence of commands) that is run
4402 by techmap on the module. A common use case is to run 'proc' on modules
4403 that are written using always-statements.
4405 When such a wire has a non-constant value at the time it is to be
4406 evaluated, an error is produced. That means it is possible for such a
4407 wire to start out as non-constant and evaluate to a constant value
4408 during processing of other _TECHMAP_DO_* commands.
4410 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
4411 in this case techmap will create a copy for each distinct configuration
4412 of constant inputs and shorted inputs at this point and import the
4413 constant and connected bits into the map module. All further commands
4414 are executed in this copy. This is a very convenient way of creating
4415 optimized specializations of techmap modules without using the special
4416 parameters described below.
4418 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
4419 then techmap will recursively replace the cells in the module with their
4420 implementation. This is not affected by the -max_iter option.
4422 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
4424 In addition to this special wires, techmap also supports special parameters in
4425 modules in the map file:
4428 When a parameter with this name exists, it will be set to the type name
4429 of the cell that matches the module.
4431 _TECHMAP_CONSTMSK_<port-name>_
4432 _TECHMAP_CONSTVAL_<port-name>_
4433 When this pair of parameters is available in a module for a port, then
4434 former has a 1-bit for each constant input bit and the latter has the
4435 value for this bit. The unused bits of the latter are set to undef (x).
4437 _TECHMAP_BITS_CONNMAP_
4438 _TECHMAP_CONNMAP_<port-name>_
4439 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
4440 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
4441 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
4442 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
4443 This can be used to detect shorted inputs.
4445 When a module in the map file has a parameter where the according cell in the
4446 design has a port, the module from the map file is only used if the port in
4447 the design is connected to a constant value. The parameter is then set to the
4450 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
4451 and attributes of the cell that is being replaced.
4453 See 'help extract' for a pass that does the opposite thing.
4455 See 'help flatten' for a pass that does flatten the design (which is
4456 essentially techmap but using the design itself as map library).
4459 \section{tee -- redirect command output to file}
4461 \begin{lstlisting}[numbers=left,frame=single]
4462 tee [-q] [-o logfile|-a logfile] cmd
4464 Execute the specified command, optionally writing the commands output to the
4465 specified logfile(s).
4468 Do not print output to the normal destination (console and/or log file)
4471 Write output to this file, truncate if exists.
4474 Write output to this file, append if exists.
4477 Add/subract INT from the -v setting for this command.
4480 \section{test\_abcloop -- automatically test handling of loops in abc command}
4481 \label{cmd:test_abcloop}
4482 \begin{lstlisting}[numbers=left,frame=single]
4483 test_abcloop [options]
4485 Test handling of logic loops in ABC.
4488 create this number of circuits and test them (default = 100).
4490 -s {positive_integer}
4491 use this value as rng seed value (default = unix time).
4494 \section{test\_autotb -- generate simple test benches}
4495 \label{cmd:test_autotb}
4496 \begin{lstlisting}[numbers=left,frame=single]
4497 test_autotb [options] [filename]
4499 Automatically create primitive Verilog test benches for all modules in the
4500 design. The generated testbenches toggle the input pins of the module in
4501 a semi-random manner and dumps the resulting output signals.
4503 This can be used to check the synthesis results for simple circuits by
4504 comparing the testbench output for the input files and the synthesis results.
4506 The backend automatically detects clock signals. Additionally a signal can
4507 be forced to be interpreted as clock signal by setting the attribute
4508 'gentb_clock' on the signal.
4510 The attribute 'gentb_constant' can be used to force a signal to a constant
4511 value after initialization. This can e.g. be used to force a reset signal
4512 low in order to explore more inner states in a state machine.
4515 number of iterations the test bench should run (default = 1000)
4518 \section{test\_cell -- automatically test the implementation of a cell type}
4519 \label{cmd:test_cell}
4520 \begin{lstlisting}[numbers=left,frame=single]
4521 test_cell [options] {cell-types}
4523 Tests the internal implementation of the given cell type (for example '$add')
4524 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
4526 Run with 'all' instead of a cell type to run the test on all supported
4527 cell types. Use for example 'all /$add' for all cell types except $add.
4530 create this number of cell instances and test them (default = 100).
4532 -s {positive_integer}
4533 use this value as rng seed value (default = unix time).
4536 don't generate circuits. instead load the specified ilang file.
4538 -w {filename_prefix}
4539 don't test anything. just generate the circuits and write them
4540 to ilang files with the specified prefix
4543 pass this option to techmap.
4546 use "techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc"
4549 instead of calling "techmap", call "aigmap"
4552 when creating test benches with dividers, create an additional mux
4553 to mask out the division-by-zero case
4555 -script {script_file}
4556 instead of calling "techmap", call "script {script_file}".
4559 set some input bits to random constant values
4562 do not check SAT model or run SAT equivalence checking
4565 do not check const-eval models
4568 test cell edges db creator against sat-based implementation
4571 print additional debug information to the console
4574 create a Verilog test bench to test simlib and write_verilog
4577 \section{torder -- print cells in topological order}
4579 \begin{lstlisting}[numbers=left,frame=single]
4580 torder [options] [selection]
4582 This command prints the selected cells in topological order.
4584 -stop <cell_type> <cell_port>
4585 do not use the specified cell port in topological sorting
4588 by default Q outputs of internal FF cells and memory read port outputs
4589 are not used in topological sorting. this option deactivates that.
4592 \section{trace -- redirect command output to file}
4594 \begin{lstlisting}[numbers=left,frame=single]
4597 Execute the specified command, logging all changes the command performs on
4598 the design in real time.
4601 \section{tribuf -- infer tri-state buffers}
4603 \begin{lstlisting}[numbers=left,frame=single]
4604 tribuf [options] [selection]
4606 This pass transforms $mux cells with 'z' inputs to tristate buffers.
4609 merge multiple tri-state buffers driving the same net
4610 into a single buffer.
4613 convert tri-state buffers that do not drive output ports
4614 to non-tristate logic. this option implies -merge.
4617 \section{uniquify -- create unique copies of modules}
4618 \label{cmd:uniquify}
4619 \begin{lstlisting}[numbers=left,frame=single]
4620 uniquify [selection]
4622 By default, a module that is instantiated by several other modules is only
4623 kept once in the design. This preserves the original modularity of the design
4624 and reduces the overall size of the design in memory. But it prevents certain
4625 optimizations and other operations on the design. This pass creates unique
4626 modules for all selected cells. The created modules are marked with the
4629 This commands only operates on modules that by themself have the 'unique'
4630 attribute set (the 'top' module is unique implicitly).
4633 \section{verific -- load Verilog and VHDL designs using Verific}
4635 \begin{lstlisting}[numbers=left,frame=single]
4636 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..
4638 Load the specified Verilog/SystemVerilog files into Verific.
4640 All files specified in one call to this command are one compilation unit.
4641 Files passed to different calls to this command are treated as belonging to
4642 different compilation units.
4644 Additional -D<macro>[=<value>] options may be added after the option indicating
4645 the language version (and before file names) to set additional verilog defines.
4646 The macros SYNTHESIS and VERIFIC are defined implicitly.
4649 verific -formal <verilog-file>..
4651 Like -sv, but define FORMAL instead of SYNTHESIS.
4654 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
4656 Load the specified VHDL files into Verific.
4659 verific -work <libname> {-sv|-vhdl|...} <hdl-file>
4661 Load the specified Verilog/SystemVerilog/VHDL file into the specified library.
4662 (default library when -work is not present: "work")
4665 verific -vlog-incdir <directory>..
4667 Add Verilog include directories.
4670 verific -vlog-libdir <directory>..
4672 Add Verilog library directories. Verific will search in this directories to
4673 find undefined modules.
4676 verific -vlog-define <macro>[=<value>]..
4678 Add Verilog defines.
4681 verific -vlog-undef <macro>..
4683 Remove Verilog defines previously set with -vlog-define.
4686 verific -set-error <msg_id>..
4687 verific -set-warning <msg_id>..
4688 verific -set-info <msg_id>..
4689 verific -set-ignore <msg_id>..
4691 Set message severity. <msg_id> is the string in square brackets when a message
4692 is printed, such as VERI-1209.
4695 verific -import [options] <top-module>..
4697 Elaborate the design for the specified top modules, import to Yosys and
4698 reset the internal state of Verific.
4703 Elaborate all modules, not just the hierarchy below the given top
4704 modules. With this option the list of modules to import is optional.
4707 Create a gate-level netlist.
4710 Flatten the design in Verific before importing.
4713 Resolve references to external nets by adding module ports as needed.
4716 Generate automatic cover statements for all asserts
4719 Verbose log messages. (-vv is even more verbose than -v.)
4721 The following additional import options are useful for debugging the Verific
4722 bindings (for Yosys and/or Verific developers):
4725 Keep going after an unsupported verific primitive is found. The
4726 unsupported primitive is added as blockbox module to the design.
4727 This will also add all SVA related cells to the design parallel to
4728 the checker logic inferred by it.
4731 Import Verific netlist as-is without translating to Yosys cell types.
4734 Ignore SVA properties, do not infer checker logic.
4737 Maximum number of ctrl bits for SVA checker FSMs (default=16).
4740 Keep all Verific names on instances and nets. By default only
4741 user-declared names are preserved.
4744 Dump the Verific netlist as a verilog file.
4746 Visit http://verific.com/ for more information on Verific.
4749 \section{verilog\_defaults -- set default options for read\_verilog}
4750 \label{cmd:verilog_defaults}
4751 \begin{lstlisting}[numbers=left,frame=single]
4752 verilog_defaults -add [options]
4754 Add the specified options to the list of default options to read_verilog.
4757 verilog_defaults -clear
4759 Clear the list of Verilog default options.
4762 verilog_defaults -push
4763 verilog_defaults -pop
4765 Push or pop the list of default options to a stack. Note that -push does
4769 \section{verilog\_defines -- define and undefine verilog defines}
4770 \label{cmd:verilog_defines}
4771 \begin{lstlisting}[numbers=left,frame=single]
4772 verilog_defines [options]
4774 Define and undefine verilog preprocessor macros.
4777 define the preprocessor symbol 'name' and set its optional value
4781 undefine the preprocessor symbol 'name'
4784 \section{wreduce -- reduce the word size of operations if possible}
4786 \begin{lstlisting}[numbers=left,frame=single]
4787 wreduce [options] [selection]
4789 This command reduces the word size of operations. For example it will replace
4790 the 32 bit adders in the following code with adders of more appropriate widths:
4792 module test(input [3:0] a, b, c, output [7:0] y);
4793 assign y = a + b + c + 1;
4799 Do not change the width of memory address ports. Use this options in
4800 flows that use the 'memory_memx' pass.
4803 \section{write\_aiger -- write design to AIGER file}
4804 \label{cmd:write_aiger}
4805 \begin{lstlisting}[numbers=left,frame=single]
4806 write_aiger [options] [filename]
4808 Write the current design to an AIGER file. The design must be flattened and
4809 must not contain any cell types except $_AND_, $_NOT_, simple FF types,
4810 $assert and $assume cells, and $initstate cells.
4812 $assert and $assume cells are converted to AIGER bad state properties and
4813 invariant constraints.
4816 write ASCII version of AGIER format
4819 convert FFs to zero-initialized FFs, adding additional inputs for
4823 design outputs are AIGER bad state properties
4826 include a symbol table in the generated AIGER file
4829 write an extra file with port and latch symbols
4832 like -map, but more verbose
4835 \section{write\_blif -- write design to BLIF file}
4836 \label{cmd:write_blif}
4837 \begin{lstlisting}[numbers=left,frame=single]
4838 write_blif [options] [filename]
4840 Write the current design to an BLIF file.
4843 set the specified module as design top module
4845 -buf <cell-type> <in-port> <out-port>
4846 use cells of type <cell-type> with the specified port names for buffers
4848 -unbuf <cell-type> <in-port> <out-port>
4849 replace buffer cells with the specified name and port names with
4850 a .names statement that models a buffer
4852 -true <cell-type> <out-port>
4853 -false <cell-type> <out-port>
4854 -undef <cell-type> <out-port>
4855 use the specified cell types to drive nets that are constant 1, 0, or
4856 undefined. when '-' is used as <cell-type>, then <out-port> specifies
4857 the wire name to be used for the constant signal and no cell driving
4858 that wire is generated. when '+' is used as <cell-type>, then <out-port>
4859 specifies the wire name to be used for the constant signal and a .names
4860 statement is generated to drive the wire.
4863 if a net name is aliasing another net name, then by default a net
4864 without fanout is created that is driven by the other net. This option
4865 suppresses the generation of this nets without fanout.
4867 The following options can be useful when the generated file is not going to be
4868 read by a BLIF parser but a custom tool. It is recommended to not name the output
4869 file *.blif when any of this options is used.
4872 do not translate Yosys's internal gates to generic BLIF logic
4873 functions. Instead create .subckt or .gate lines for all cells.
4876 print .gate instead of .subckt lines for all cells that are not
4877 instantiations of other modules from this design.
4880 do not generate buffers for connected wires. instead use the
4881 non-standard .conn statement.
4884 use the non-standard .attr statement to write cell attributes
4887 use the non-standard .param statement to write cell parameters
4890 use the non-standard .cname statement to write cell names
4893 enable -cname and -attr functionality for .names statements
4894 (the .cname and .attr statements will be included in the BLIF
4895 output after the truth table for the .names statement)
4898 write blackbox cells with .blackbox statement.
4901 do not write definitions for the $true, $false and $undef wires.
4904 \section{write\_btor -- write design to BTOR file}
4905 \label{cmd:write_btor}
4906 \begin{lstlisting}[numbers=left,frame=single]
4907 write_btor [options] [filename]
4909 Write a BTOR description of the current design.
4912 Add comments and indentation to BTOR output file
4915 Output only a single bad property for all asserts
4918 \section{write\_edif -- write design to EDIF netlist file}
4919 \label{cmd:write_edif}
4920 \begin{lstlisting}[numbers=left,frame=single]
4921 write_edif [options] [filename]
4923 Write the current design to an EDIF netlist file.
4926 set the specified module as design top module
4929 do not create "GND" and "VCC" cells. (this will produce an error
4930 if the design contains constant nets. use "hilomap" to map to custom
4931 constant drivers first)
4933 -pvector {par|bra|ang}
4934 sets the delimiting character for module port rename clauses to
4935 parentheses, square brackets, or angle brackets.
4937 Unfortunately there are different "flavors" of the EDIF file format. This
4938 command generates EDIF files for the Xilinx place&route tools. It might be
4939 necessary to make small modifications to this command when a different tool
4943 \section{write\_file -- write a text to a file}
4944 \label{cmd:write_file}
4945 \begin{lstlisting}[numbers=left,frame=single]
4946 write_file [options] output_file [input_file]
4948 Write the text from the input file to the output file.
4951 Append to output file (instead of overwriting)
4954 Inside a script the input file can also can a here-document:
4956 write_file hello.txt <<EOT
4961 \section{write\_firrtl -- write design to a FIRRTL file}
4962 \label{cmd:write_firrtl}
4963 \begin{lstlisting}[numbers=left,frame=single]
4964 write_firrtl [options] [filename]
4966 Write a FIRRTL netlist of the current design.
4969 \section{write\_ilang -- write design to ilang file}
4970 \label{cmd:write_ilang}
4971 \begin{lstlisting}[numbers=left,frame=single]
4972 write_ilang [filename]
4974 Write the current design to an 'ilang' file. (ilang is a text representation
4975 of a design in yosys's internal format.)
4978 only write selected parts of the design.
4981 \section{write\_intersynth -- write design to InterSynth netlist file}
4982 \label{cmd:write_intersynth}
4983 \begin{lstlisting}[numbers=left,frame=single]
4984 write_intersynth [options] [filename]
4986 Write the current design to an 'intersynth' netlist file. InterSynth is
4987 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
4990 do not generate celltypes and conntypes commands. i.e. just output
4991 the netlists. this is used for postsilicon synthesis.
4993 -lib <verilog_or_ilang_file>
4994 Use the specified library file for determining whether cell ports are
4995 inputs or outputs. This option can be used multiple times to specify
4996 more than one library.
4999 only write selected modules. modules must be selected entirely or
5002 http://www.clifford.at/intersynth/
5005 \section{write\_json -- write design to a JSON file}
5006 \label{cmd:write_json}
5007 \begin{lstlisting}[numbers=left,frame=single]
5008 write_json [options] [filename]
5010 Write a JSON netlist of the current design.
5013 include AIG models for the different gate types
5016 The general syntax of the JSON output created by this command is as follows:
5022 <port_name>: <port_details>,
5026 <cell_name>: <cell_details>,
5030 <net_name>: <net_details>,
5040 Where <port_details> is:
5043 "direction": <"input" | "output" | "inout">,
5044 "bits": <bit_vector>
5047 And <cell_details> is:
5050 "hide_name": <1 | 0>,
5051 "type": <cell_type>,
5053 <parameter_name>: <parameter_value>,
5057 <attribute_name>: <attribute_value>,
5060 "port_directions": {
5061 <port_name>: <"input" | "output" | "inout">,
5065 <port_name>: <bit_vector>,
5070 And <net_details> is:
5073 "hide_name": <1 | 0>,
5074 "bits": <bit_vector>
5077 The "hide_name" fields are set to 1 when the name of this cell or net is
5078 automatically created and is likely not of interest for a regular user.
5080 The "port_directions" section is only included for cells for which the
5083 Module and cell ports and nets can be single bit wide or vectors of multiple
5084 bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
5085 values referenced above are vectors of this integers. Signal bits that are
5086 connected to a constant driver are denoted as string "0" or "1" instead of
5089 Numeric parameter and attribute values up to 32 bits are written as decimal
5090 values. Numbers larger than that are written as string holding the binary
5091 representation of the value.
5093 For example the following Verilog code:
5095 module test(input x, y);
5096 (* keep *) foo #(.P(
42), .Q(
1337))
5097 foo_inst (.A(
{x, y
}), .B(
{y, x
}), .C(
{4'd10,
{4{x
}}}));
5100 Translates to the following JSON output:
5107 "direction": "input",
5111 "direction": "input",
5128 "C":
[ 2,
2,
2,
2, "
0", "
1", "
0", "
1"
],
5154 The models are given as And-Inverter-Graphs (AIGs) in the following form:
5158 /*
0 */
[ <node-spec>
],
5159 /*
1 */
[ <node-spec>
],
5160 /*
2 */
[ <node-spec>
],
5166 The following node-types may be used:
5168 [ "port", <portname>, <bitindex>, <out-list>
]
5169 - the value of the specified input port bit
5171 [ "nport", <portname>, <bitindex>, <out-list>
]
5172 - the inverted value of the specified input port bit
5174 [ "and", <node-index>, <node-index>, <out-list>
]
5175 - the ANDed value of the specified nodes
5177 [ "nand", <node-index>, <node-index>, <out-list>
]
5178 - the inverted ANDed value of the specified nodes
5180 [ "true", <out-list>
]
5181 - the constant value
1
5183 [ "false", <out-list>
]
5184 - the constant value
0
5186 All nodes appear in topological order. I.e. only nodes with smaller indices
5187 are referenced by "and" and "nand" nodes.
5189 The optional <out-list> at the end of a node specification is a list of
5190 output portname and bitindex pairs, specifying the outputs driven by this node.
5192 For example, the following is the model for a
3-input
3-output $reduce_and cell
5193 inferred by the following code:
5195 module test(input
[2:
0] in, output
[2:
0] out);
5199 "$reduce_and:
3U:
3":
[
5200 /*
0 */
[ "port", "A",
0 ],
5201 /*
1 */
[ "port", "A",
1 ],
5202 /*
2 */
[ "and",
0,
1 ],
5203 /*
3 */
[ "port", "A",
2 ],
5204 /*
4 */
[ "and",
2,
3, "Y",
0 ],
5205 /*
5 */
[ "false", "Y",
1, "Y",
2 ]
5208 Future version of Yosys might add support for additional fields in the JSON
5209 format. A program processing this format must ignore all unknown fields.
5212 \section{write
\_simplec -- convert design to simple C code
}
5213 \label{cmd:write_simplec
}
5214 \begin{lstlisting
}[numbers=left,frame=single
]
5215 write_simplec
[options
] [filename
]
5217 Write simple C code for simulating the design. The C code writen can be used to
5218 simulate the design in a C environment, but the purpose of this command is to
5219 generate code that works well with C-based formal verification.
5222 this will print the recursive walk used to export the modules.
5224 -i8, -i16, -i32, -i64
5225 set the maximum integer bit width to use in the generated code.
5227 THIS COMMAND IS UNDER CONSTRUCTION
5230 \section{write
\_smt2 -- write design to SMT-LIBv2 file
}
5231 \label{cmd:write_smt2
}
5232 \begin{lstlisting
}[numbers=left,frame=single
]
5233 write_smt2
[options
] [filename
]
5235 Write a SMT-LIBv2
[1] description of the current design. For a module with name
5236 '<mod>' this will declare the sort '<mod>_s' (state of the module) and will
5237 define and declare functions operating on that state.
5239 The following SMT2 functions are generated for a module with name '<mod>'.
5240 Some declarations/definitions are printed with a special comment. A prover
5241 using the SMT2 files can use those comments to collect all relevant metadata
5244 ; yosys-smt2-module <mod>
5245 (declare-sort |<mod>_s|
0)
5246 The sort representing a state of module <mod>.
5248 (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))
5249 This function must be asserted for each state to establish the
5252 ; yosys-smt2-input <wirename> <width>
5253 ; yosys-smt2-output <wirename> <width>
5254 ; yosys-smt2-register <wirename> <width>
5255 ; yosys-smt2-wire <wirename> <width>
5256 (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))
5257 (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)
5258 For each port, register, and wire with the 'keep' attribute set an
5259 accessor function is generated. Single-bit wires are returned as Bool,
5260 multi-bit wires as BitVec.
5262 ; yosys-smt2-cell <submod> <instancename>
5263 (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)
5264 There is a function like that for each hierarchical instance. It
5265 returns the sort that represents the state of the sub-module that
5266 implements the instance.
5268 (declare-fun |<mod>_is| (|<mod>_s|) Bool)
5269 This function must be asserted 'true' for initial states, and 'false'
5272 (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))
5273 This function must be asserted 'true' for initial states. For
5274 non-initial states it must be left unconstrained.
5276 (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))
5277 This function evaluates to 'true' if the states 'state' and
5278 'next_state' form a valid state transition.
5280 (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))
5281 This function evaluates to 'true' if all assertions hold in the state.
5283 (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))
5284 This function evaluates to 'true' if all assumptions hold in the state.
5286 ; yosys-smt2-assert <id> <filename:linenum>
5287 (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))
5288 Each $assert cell is converted into one of this functions. The function
5289 evaluates to 'true' if the assert statement holds in the state.
5291 ; yosys-smt2-assume <id> <filename:linenum>
5292 (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))
5293 Each $assume cell is converted into one of this functions. The function
5294 evaluates to 'true' if the assume statement holds in the state.
5296 ; yosys-smt2-cover <id> <filename:linenum>
5297 (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))
5298 Each $cover cell is converted into one of this functions. The function
5299 evaluates to 'true' if the cover statement is activated in the state.
5304 this will print the recursive walk used to export the modules.
5307 Use a BitVec sort to represent a state instead of an uninterpreted
5308 sort. As a side-effect this will prevent use of arrays to model
5312 Use SMT-LIB
2.6 style datatypes to represent a state instead of an
5316 disable support for BitVec (FixedSizeBitVectors theory). without this
5317 option multi-bit wires are represented using the BitVec sort and
5318 support for coarse grain cells (incl. arithmetic) is enabled.
5321 disable support for memories (via ArraysEx theory). this option is
5322 implied by -nobv. only $mem cells without merged registers in
5323 read ports are supported. call "memory" with -nordff to make sure
5324 that no registers are merged into $mem read ports. '<mod>_m' functions
5325 will be generated for accessing the arrays that are used to represent
5329 create '<mod>_n' functions for all public wires. by default only ports,
5330 registers, and wires with the 'keep' attribute are exported.
5332 -tpl <template_file>
5333 use the given template file. the line containing only the token '
%%'
5334 is replaced with the regular output of this command.
5336 [1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
5337 R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
5339 ---------------------------------------------------------------------------
5343 Consider the following module (test.v). We want to prove that the output can
5344 never transition from a non-zero value to a zero value.
5346 module test(input clk, output reg
[3:
0] y);
5347 always @(posedge clk)
5351 For this proof we create the following template (test.tpl).
5353 ; we need QF_UFBV for this poof
5356 ; insert the auto-generated code here
5359 ; declare two state variables s1 and s2
5360 (declare-fun s1 () test_s)
5361 (declare-fun s2 () test_s)
5363 ; state s2 is the successor of state s1
5364 (assert (test_t s1 s2))
5366 ; we are looking for a model with y non-zero in s1
5367 (assert (distinct (|test_n y| s1) #b0000))
5369 ; we are looking for a model with y zero in s2
5370 (assert (= (|test_n y| s2) #b0000))
5372 ; is there such a model?
5375 The following yosys script will create a 'test.smt2' file for our proof:
5378 hierarchy -check; proc; opt; check -assert
5379 write_smt2 -bv -tpl test.tpl test.smt2
5381 Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
5382 from non-zero to zero in the test design.
5385 \section{write
\_smv -- write design to SMV file
}
5386 \label{cmd:write_smv
}
5387 \begin{lstlisting
}[numbers=left,frame=single
]
5388 write_smv
[options
] [filename
]
5390 Write an SMV description of the current design.
5393 this will print the recursive walk used to export the modules.
5395 -tpl <template_file>
5396 use the given template file. the line containing only the token '
%%'
5397 is replaced with the regular output of this command.
5399 THIS COMMAND IS UNDER CONSTRUCTION
5402 \section{write
\_spice -- write design to SPICE netlist file
}
5403 \label{cmd:write_spice
}
5404 \begin{lstlisting
}[numbers=left,frame=single
]
5405 write_spice
[options
] [filename
]
5407 Write the current design to an SPICE netlist file.
5410 generate multi-bit ports in MSB first order
5411 (default is LSB first)
5414 set the net name for constant
0 (default: Vss)
5417 set the net name for constant
1 (default: Vdd)
5420 prefix for not-connected nets (default: _NC)
5423 include names of internal ($-prefixed) nets in outputs
5424 (default is to use net numbers instead)
5427 set the specified module as design top module
5430 \section{write
\_table -- write design as connectivity table
}
5431 \label{cmd:write_table
}
5432 \begin{lstlisting
}[numbers=left,frame=single
]
5433 write_table
[options
] [filename
]
5435 Write the current design as connectivity table. The output is a tab-separated
5436 ASCII table with the following columns:
5445 module inputs and outputs are output using cell type and port '-' and with
5446 'pi' (primary input) or 'po' (primary output) or 'pio' as direction.
5449 \section{write
\_verilog -- write design to Verilog file
}
5450 \label{cmd:write_verilog
}
5451 \begin{lstlisting
}[numbers=left,frame=single
]
5452 write_verilog
[options
] [filename
]
5454 Write the current design to a Verilog file.
5457 without this option all internal object names (the ones with a dollar
5458 instead of a backslash prefix) are changed to short names in the
5459 format '_<number>_'.
5461 -renameprefix <prefix>
5462 insert this prefix in front of auto-generated instance names
5465 with this option no attributes are included in the output
5468 with this option attributes are included as comments in the output
5471 without this option all internal cells are converted to Verilog
5475 32-bit constant values are by default dumped as decimal numbers,
5476 not bit pattern. This option deactivates this feature and instead
5477 will write out all constants in binary.
5480 dump
32-bit constants in decimal and without size and radix
5483 constant values that are compatible with hex output are usually
5484 dumped as hex values. This option deactivates this feature and
5485 instead will write out all constants in binary.
5488 Parameters and attributes that are specified as strings in the
5489 original input will be output as strings by this back-end. This
5490 deactivates this feature and instead will write string constants
5494 Use 'defparam' statements instead of the Verilog-
2001 syntax for
5498 usually modules with the 'blackbox' attribute are ignored. with
5499 this option set only the modules with the 'blackbox' attribute
5500 are written to the output file.
5503 only write selected modules. modules must be selected entirely or
5507 verbose output (print new names of all renamed wires and cells)
5509 Note that RTLIL processes can't always be mapped directly to Verilog
5510 always blocks. This frontend should only be used to export an RTLIL
5511 netlist, i.e. after the "proc" pass has been used to convert all
5512 processes to logic networks and registers. A warning is generated when
5513 this command is called on a design with RTLIL processes.
5516 \section{zinit -- add inverters so all FF are zero-initialized
}
5518 \begin{lstlisting
}[numbers=left,frame=single
]
5519 zinit
[options
] [selection
]
5521 Add inverters as needed to make all FFs zero-initialized.
5524 also add zero initialization to uninitialized FFs
projects / yosys.git / blob