1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command name instead of "yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interpreted as the command string to be passed to ABC. The
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
}
28 for -liberty with -constr:
29 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
};
30 buffer; upsize
{D
}; dnsize
{D
}; stime -p
33 strash; scorr; ifraig; retime; strash; dch -f; if
36 strash; scorr; ifraig; retime; strash; dch -f; map
39 use different default scripts that are slightly faster (at the cost
42 for -liberty without -constr:
45 for -liberty with -constr:
46 retime
{D
}; map
{D
}; buffer; upsize
{D
}; dnsize
{D
}; stime -p
55 generate netlists for the specified cell library (using the liberty
59 pass this file with timing constraints to ABC. use with -liberty.
61 a constr file contains two lines:
62 set_driving_cell <cell_name>
63 set_load <floating_point_number>
65 the set_driving_cell statement defines which cell type is assumed to
66 drive the primary inputs and the set_load statement sets the load in
67 femtofarads for each primary output.
70 set delay target. the string
{D
} in the default scripts above is
71 replaced by this option when used, and an empty string otherwise.
74 generate netlist using luts of (max) the specified width.
77 generate netlist using luts of (max) the specified width <w2>. All
78 luts with width <= <w1> have constant cost. for luts larger than <w1>
79 the area cost doubles with each additional input bit. the delay cost
80 is still constant for all lut widths.
83 also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
84 clock domains are automatically partitioned in clock domains and each
85 domain is passed through ABC independently.
87 -clk
[!
]<clock-signal-name>
[,
[!
]<enable-signal-name>
]
88 use only the specified clock domain. this is like -dff, but only FF
89 cells that belong to the specified clock domain are used.
92 set the "keep" attribute on flip-flop output wires. (and thus preserve
93 them, for example for equivalence checking.)
96 when this option is used, the temporary files created by this pass
97 are not removed. this is useful for debugging.
100 print the temp dir name in log. usually this is suppressed so that the
101 command output is identical across runs.
104 set a 'abcgroup' attribute on all objects created by ABC. The value of
105 this attribute is a unique integer for each ABC process started. This
106 is useful for debugging the partitioning of clock domains.
108 When neither -liberty nor -lut is used, the Yosys standard cell library is
109 loaded into ABC before the ABC script is executed.
111 This pass does not operate on modules with unprocessed processes in it.
112 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
114 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
117 \section{add -- add objects to the design
}
119 \begin{lstlisting
}[numbers=left,frame=single
]
120 add <command>
[selection
]
122 This command adds objects to the design. It operates on all fully selected
123 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
126 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
128 Add a wire (input, inout, output port) with the given name and width. The
129 command will fail if the object exists already and has different properties
130 than the object to be created.
133 add -global_input <name> <width>
[selection
]
135 Like 'add -input', but also connect the signal between instances of the
139 \section{aigmap -- map logic to and-inverter-graph circuit
}
141 \begin{lstlisting
}[numbers=left,frame=single
]
142 aigmap
[options
] [selection
]
144 Replace all logic cells with circuits made of only $_AND_ and
148 Enable creation of $_NAND_ cells
151 \section{alumacc -- extract ALU and MACC cells
}
153 \begin{lstlisting
}[numbers=left,frame=single
]
156 This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
160 \section{cd -- a shortcut for 'select -module <name>'
}
162 \begin{lstlisting
}[numbers=left,frame=single
]
165 This is just a shortcut for 'select -module <modname>'.
170 When no module with the specified name is found, but there is a cell
171 with the specified name in the current module, then this is equivalent
176 This is just a shortcut for 'select -clear'.
179 \section{check -- check for obvious problems in the design
}
181 \begin{lstlisting
}[numbers=left,frame=single
]
182 check
[options
] [selection
]
184 This pass identifies the following problems in the current design:
186 - combinatorial loops
188 - two or more conflicting drivers for one wire
190 - used wires that do not have a driver
192 When called with -noinit then this command also checks for wires which have
193 the 'init' attribute set.
195 When called with -assert then the command will produce an error if any
196 problems are found in the current design.
199 \section{chparam -- re-evaluate modules with new parameters
}
201 \begin{lstlisting
}[numbers=left,frame=single
]
202 chparam
[ -set name value
]...
[selection
]
204 Re-evaluate the selected modules with new parameters. String values must be
205 passed in double quotes (").
208 chparam -list
[selection
]
210 List the available parameters of the selected modules.
213 \section{clean -- remove unused cells and wires
}
215 \begin{lstlisting
}[numbers=left,frame=single
]
216 clean
[options
] [selection
]
218 This is identical to 'opt_clean', but less verbose.
220 When commands are separated using the ';;' token, this command will be executed
221 between the commands.
223 When commands are separated using the ';;;' token, this command will be executed
224 in -purge mode between the commands.
227 \section{connect -- create or remove connections
}
229 \begin{lstlisting
}[numbers=left,frame=single
]
230 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
232 Create a connection. This is equivalent to adding the statement 'assign
233 <lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
234 drivers for <lhs-expr> are unconnected. This can be overwritten by using
238 connect
[-nomap
] -unset <expr>
240 Unconnect all existing drivers for the specified expression.
243 connect
[-nomap
] -port <cell> <port> <expr>
245 Connect the specified cell port to the specified cell port.
248 Per default signal alias names are resolved and all signal names are mapped
249 the the signal name of the primary driver. Using the -nomap option deactivates
252 The connect command operates in one module only. Either only one module must
253 be selected or an active module must be set using the 'cd' command.
255 This command does not operate on module with processes.
258 \section{connwrappers -- replace undef values with defined constants
}
259 \label{cmd:connwrappers
}
260 \begin{lstlisting
}[numbers=left,frame=single
]
261 connwrappers
[options
] [selection
]
263 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
264 in wrapper cells with a (larger) constant port size. I.e. the upper bits
265 of the wrapper output are signed/unsigned bit extended. This command uses this
266 knowledge to rewire the inputs of the driven cells to match the output of
269 -signed <cell_type> <port_name> <width_param>
270 -unsigned <cell_type> <port_name> <width_param>
271 consider the specified signed/unsigned wrapper output
273 -port <cell_type> <port_name> <width_param> <sign_param>
274 use the specified parameter to decide if signed or unsigned
276 The options -signed, -unsigned, and -port can be specified multiple times.
279 \section{copy -- copy modules in the design
}
281 \begin{lstlisting
}[numbers=left,frame=single
]
282 copy old_name new_name
284 Copy the specified module. Note that selection patterns are not supported
288 \section{cover -- print code coverage counters
}
290 \begin{lstlisting
}[numbers=left,frame=single
]
291 cover
[options
] [pattern
]
293 Print the code coverage counters collected using the cover() macro in the Yosys
294 C++ code. This is useful to figure out what parts of Yosys are utilized by a
298 Do not print output to the normal destination (console and/or log file)
301 Write output to this file, truncate if exists.
304 Write output to this file, append if exists.
307 Write output to a newly created file in the specified directory.
309 When one or more pattern (shell wildcards) are specified, then only counters
310 matching at least one pattern are printed.
313 It is also possible to instruct Yosys to print the coverage counters on program
314 exit to a file using environment variables:
316 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
318 This will create a file (with an auto-generated name) in this
319 directory and write the coverage counters to it.
321 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
323 This will append the coverage counters to the specified file.
326 Hint: Use the following AWK command to consolidate Yosys coverage files:
328 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
329 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
332 Coverage counters are only available in Yosys for Linux.
335 \section{delete -- delete objects in the design
}
337 \begin{lstlisting
}[numbers=left,frame=single
]
340 Deletes the selected objects. This will also remove entire modules, if the
341 whole module is selected.
344 delete
{-input|-output|-port
} [selection
]
346 Does not delete any object but removes the input and/or output flag on the
347 selected wires, thus 'deleting' module ports.
350 \section{design -- save, restore and reset current design
}
352 \begin{lstlisting
}[numbers=left,frame=single
]
355 Clear the current design.
360 Save the current design under the given name.
365 Save the current design under the given name and then clear the current design.
370 Push the current design to the stack and then clear the current design.
375 Reset the current design and pop the last design from the stack.
380 Reset the current design and load the design previously saved under the given
384 design -copy-from <name>
[-as <new_mod_name>
] <selection>
386 Copy modules from the specified design into the current one. The selection is
387 evaluated in the other design.
390 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
392 Copy modules from the current design into the specified one.
395 \section{dff2dffe -- transform \$dff cells to \$dffe cells
}
397 \begin{lstlisting
}[numbers=left,frame=single
]
398 dff2dffe
[options
] [selection
]
400 This pass transforms $dff cells driven by a tree of multiplexers with one or
401 more feedback paths to $dffe cells. It also works on gate-level cells such as
402 $_DFF_P_, $_DFF_N_ and $_MUX_.
405 operate in the opposite direction: replace $dffe cells with combinations
406 of $dff and $mux cells. the options below are ignore in unmap mode.
408 -direct <internal_gate_type> <external_gate_type>
409 map directly to external gate type. <internal_gate_type> can
410 be any internal gate-level FF cell (except $_DFFE_??_). the
411 <external_gate_type> is the cell type name for a cell with an
412 identical interface to the <internal_gate_type>, except it
413 also has an high-active enable port 'E'.
414 Usually <external_gate_type> is an intermediate cell type
415 that is then translated to the final type using 'techmap'.
417 -direct-match <pattern>
418 like -direct for all DFF cell types matching the expression.
419 this will use $__DFFE_* as <external_gate_type> matching the
420 internal gate type $_DFF_*_, except for $_DFF_
[NP
]_, which is
421 converted to $_DFFE_
[NP
]_.
424 \section{dffinit -- set INIT param on FF cells
}
426 \begin{lstlisting
}[numbers=left,frame=single
]
427 dffinit
[options
] [selection
]
429 This pass sets an FF cell parameter to the the initial value of the net it
430 drives. (This is primarily used in FPGA flows.)
432 -ff <cell_name> <output_port> <init_param>
433 operate on the specified cell type. this option can be used
437 \section{dfflibmap -- technology mapping of flip-flops
}
438 \label{cmd:dfflibmap
}
439 \begin{lstlisting
}[numbers=left,frame=single
]
440 dfflibmap
[-prepare
] -liberty <file>
[selection
]
442 Map internal flip-flop cells to the flip-flop cells in the technology
443 library specified in the given liberty file.
445 This pass may add inverters as needed. Therefore it is recommended to
446 first run this pass and then map the logic paths to the target technology.
448 When called with -prepare, this command will convert the internal FF cells
449 to the internal cell types that best match the cells found in the given
453 \section{dump -- print parts of the design in ilang format
}
455 \begin{lstlisting
}[numbers=left,frame=single
]
456 dump
[options
] [selection
]
458 Write the selected parts of the design to the console or specified file in
462 also dump the module headers, even if only parts of a single
466 only dump the module headers if the entire module is selected
469 write to the specified file.
472 like -outfile but append instead of overwrite
475 \section{echo -- turning echoing back of commands on and off
}
477 \begin{lstlisting
}[numbers=left,frame=single
]
480 Print all commands to log before executing them.
485 Do not print all commands to log before executing them. (default)
488 \section{equiv
\_add -- add a \$equiv cell
}
489 \label{cmd:equiv_add
}
490 \begin{lstlisting
}[numbers=left,frame=single
]
491 equiv_add gold_sig gate_sig
493 This command adds an $equiv cell for the specified signals.
496 \section{equiv
\_induct -- proving \$equiv cells using temporal induction
}
497 \label{cmd:equiv_induct
}
498 \begin{lstlisting
}[numbers=left,frame=single
]
499 equiv_induct
[options
] [selection
]
501 Uses a version of temporal induction to prove $equiv cells.
503 Only selected $equiv cells are proven and only selected cells are used to
507 enable modelling of undef states
510 the max. number of time steps to be considered (default =
4)
512 This command is very effective in proving complex sequential circuits, when
513 the internal state of the circuit quickly propagates to $equiv cells.
515 However, this command uses a weak definition of 'equivalence': This command
516 proves that the two circuits will not diverge after they produce equal
517 outputs (observable points via $equiv) for at least <N> cycles (the <N>
520 Combined with simulation this is very powerful because simulation can give
521 you confidence that the circuits start out synced for at least <N> cycles
525 \section{equiv
\_make -- prepare a circuit for equivalence checking
}
526 \label{cmd:equiv_make
}
527 \begin{lstlisting
}[numbers=left,frame=single
]
528 equiv_make
[options
] gold_module gate_module equiv_module
530 This creates a module annotated with $equiv cells from two presumably
531 equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
532 to work with the created equivalent checking module.
535 Also match cells and wires with $... names.
538 Do not match cells or signals that match the names in the file.
541 Match FSM encodings using the description from the file.
542 See 'help fsm_recode' for details.
544 Note: The circuit created by this command is not a miter (with something like
545 a trigger output), but instead uses $equiv cells to encode the equivalence
546 checking problem. Use 'miter -equiv' if you want to create a miter circuit.
549 \section{equiv
\_miter -- extract miter from equiv circuit
}
550 \label{cmd:equiv_miter
}
551 \begin{lstlisting
}[numbers=left,frame=single
]
552 equiv_miter
[options
] miter_module
[selection
]
554 This creates a miter module for further analysis of the selected $equiv cells.
557 Create a trigger output
560 Create cmp_* outputs for individual unproven $equiv cells
563 Create a $assert cell for each unproven $equiv cell
566 Create compare logic that handles undefs correctly
569 \section{equiv
\_remove -- remove \$equiv cells
}
570 \label{cmd:equiv_remove
}
571 \begin{lstlisting
}[numbers=left,frame=single
]
572 equiv_remove
[options
] [selection
]
574 This command removes the selected $equiv cells. If neither -gold nor -gate is
575 used then only proven cells are removed.
584 \section{equiv
\_simple -- try proving simple \$equiv instances
}
585 \label{cmd:equiv_simple
}
586 \begin{lstlisting
}[numbers=left,frame=single
]
587 equiv_simple
[options
] [selection
]
589 This command tries to prove $equiv cells using a simple direct SAT approach.
595 enable modelling of undef states
598 disabling grouping of $equiv cells by output wire
601 the max. number of time steps to be considered (default =
1)
604 \section{equiv
\_status -- print status of equivalent checking module
}
605 \label{cmd:equiv_status
}
606 \begin{lstlisting
}[numbers=left,frame=single
]
607 equiv_status
[options
] [selection
]
609 This command prints status information for all selected $equiv cells.
612 produce an error if any unproven $equiv cell is found
615 \section{eval -- evaluate the circuit given an input
}
617 \begin{lstlisting
}[numbers=left,frame=single
]
618 eval
[options
] [selection
]
620 This command evaluates the value of a signal given the value of all required
623 -set <signal> <value>
624 set the specified signal to the specified value.
627 set all unspecified source signals to undef (x)
630 create a truth table using the specified input signals
633 show the value for the specified signal. if no -show option is passed
634 then all output ports of the current module are used.
637 \section{expose -- convert internal signals to module ports
}
639 \begin{lstlisting
}[numbers=left,frame=single
]
640 expose
[options
] [selection
]
642 This command exposes all selected internal signals of a module as additional
646 only consider wires that are directly driven by register cell.
649 when exposing a wire, create an input/output pair and cut the internal
650 signal path at that wire.
653 only expose those signals that are shared among the selected modules.
654 this is useful for preparing modules for equivalence checking.
657 also turn connections to instances of other modules to additional
658 inputs and outputs and remove the module instances.
661 turn flip-flops to sets of inputs and outputs.
664 when creating new wire/port names, the original object name is suffixed
665 with this separator (default: '.') and the port name or a type
666 designator for the exposed signal.
669 \section{extract -- find subcircuits and replace them with cells
}
671 \begin{lstlisting
}[numbers=left,frame=single
]
672 extract -map <map_file>
[options
] [selection
]
673 extract -mine <out_file>
[options
] [selection
]
675 This pass looks for subcircuits that are isomorphic to any of the modules
676 in the given map file and replaces them with instances of this modules. The
677 map file can be a Verilog source file
(*.v) or an ilang file (*.il).
680 use the modules in this file as reference. This option can be used
684 use the modules in this in-memory design as reference. This option can
685 be used multiple times.
688 print debug output while analyzing
691 also find instances with constant drivers. this may be much
692 slower than the normal operation.
695 normally builtin port swapping rules for internal cells are used per
696 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
697 when this option is used.
699 -compat <needle_type> <haystack_type>
700 Per default, the cells in the map file (needle) must have the
701 type as the cells in the active design (haystack). This option
702 can be used to register additional pairs of types that should
703 match. This option can be used multiple times.
705 -swap <needle_type> <port1>,<port2>[,...]
706 Register a set of swappable ports for a needle cell type.
707 This option can be used multiple times.
709 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
710 Register a valid permutation of swappable ports for a needle
711 cell type. This option can be used multiple times.
713 -cell_attr <attribute_name>
714 Attributes on cells with the given name must match.
716 -wire_attr <attribute_name>
717 Attributes on wires with the given name must match.
720 Do not use parameters when matching cells.
722 -ignore_param <cell_type> <parameter_name>
723 Do not use this parameter when matching cells.
725 This pass does not operate on modules with unprocessed processes in it.
726 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
728 This pass can also be used for mining for frequent subcircuits. In this mode
729 the following options are to be used instead of the -map option.
732 mine for frequent subcircuits and write them to the given ilang file
734 -mine_cells_span <min> <max>
735 only mine for subcircuits with the specified number of cells
739 only mine for subcircuits with at least the specified number of matches
742 -mine_limit_matches_per_module <num>
743 when calculating the number of matches for a subcircuit, don't count
744 more than the specified number of matches per module
746 -mine_max_fanout <num>
747 don't consider internal signals with more than <num> connections
749 The modules in the map file may have the attribute 'extract_order' set to an
750 integer value. Then this value is used to determine the order in which the pass
751 tries to map the modules to the design (ascending, default value is 0).
753 See 'help techmap' for a pass that does the opposite thing.
756 \section{flatten -- flatten design}
758 \begin{lstlisting}[numbers=left,frame=single]
761 This pass flattens the design by replacing cells by their implementation. This
762 pass is very similar to the 'techmap' pass. The only difference is that this
763 pass is using the current design as mapping library.
765 Cells and/or modules with the 'keep_hierarchy' attribute set will not be
766 flattened by this command.
769 \section{freduce -- perform functional reduction}
771 \begin{lstlisting}[numbers=left,frame=single]
772 freduce [options] [selection]
774 This pass performs functional reduction in the circuit. I.e. if two nodes are
775 equivalent, they are merged to one node and one of the redundant drivers is
776 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
779 enable verbose or very verbose output
782 enable explicit handling of inverted signals
785 stop after <n> reduction operations. this is mostly used for
786 debugging the freduce command itself.
789 dump the design to <prefix>_<module>_<num>.il after each reduction
790 operation. this is mostly used for debugging the freduce command.
792 This pass is undef-aware, i.e. it considers don't-care values for detecting
795 All selected wires are considered for rewiring. The selected cells cover the
796 circuit that is analyzed.
799 \section{fsm -- extract and optimize finite state machines}
801 \begin{lstlisting}[numbers=left,frame=single]
802 fsm [options] [selection]
804 This pass calls all the other fsm_* passes in a useful order. This performs
805 FSM extraction and optimization. It also calls opt_clean as needed:
807 fsm_detect unless got option -nodetect
814 fsm_expand if got option -expand
815 opt_clean if got option -expand
816 fsm_opt if got option -expand
818 fsm_recode unless got option -norecode
822 fsm_export if got option -export
823 fsm_map unless got option -nomap
827 -expand, -norecode, -export, -nomap
828 enable or disable passes as indicated above
831 -fm_set_fsm_file file
833 passed through to fsm_recode pass
836 \section{fsm\_detect -- finding FSMs in design}
837 \label{cmd:fsm_detect}
838 \begin{lstlisting}[numbers=left,frame=single]
839 fsm_detect [selection]
841 This pass detects finite state machines by identifying the state signal.
842 The state signal is then marked by setting the attribute 'fsm_encoding'
843 on the state signal to "auto".
845 Existing 'fsm_encoding' attributes are not changed by this pass.
847 Signals can be protected from being detected by this pass by setting the
848 'fsm_encoding' attribute to "none".
851 \section{fsm\_expand -- expand FSM cells by merging logic into it}
852 \label{cmd:fsm_expand}
853 \begin{lstlisting}[numbers=left,frame=single]
854 fsm_expand [selection]
856 The fsm_extract pass is conservative about the cells that belong to a finite
857 state machine. This pass can be used to merge additional auxiliary gates into
858 the finite state machine.
861 \section{fsm\_export -- exporting FSMs to KISS2 files}
862 \label{cmd:fsm_export}
863 \begin{lstlisting}[numbers=left,frame=single]
864 fsm_export [-noauto] [-o filename] [-origenc] [selection]
866 This pass creates a KISS2 file for every selected FSM. For FSMs with the
867 'fsm_export' attribute set, the attribute value is used as filename, otherwise
868 the module and cell name is used as filename. If the parameter '-o' is given,
869 the first exported FSM is written to the specified filename. This overwrites
870 the setting as specified with the 'fsm_export' attribute. All other FSMs are
871 exported to the default name as mentioned above.
874 only export FSMs that have the 'fsm_export' attribute set
877 filename of the first exported FSM
880 use binary state encoding as state names instead of s0, s1, ...
883 \section{fsm\_extract -- extracting FSMs in design}
884 \label{cmd:fsm_extract}
885 \begin{lstlisting}[numbers=left,frame=single]
886 fsm_extract [selection]
888 This pass operates on all signals marked as FSM state signals using the
889 'fsm_encoding' attribute. It consumes the logic that creates the state signal
890 and uses the state signal to generate control signal and replaces it with an
893 The generated FSM cell still generates the original state signal with its
894 original encoding. The 'fsm_opt' pass can be used in combination with the
895 'opt_clean' pass to eliminate this signal.
898 \section{fsm\_info -- print information on finite state machines}
900 \begin{lstlisting}[numbers=left,frame=single]
903 This pass dumps all internal information on FSM cells. It can be useful for
904 analyzing the synthesis process and is called automatically by the 'fsm'
905 pass so that this information is included in the synthesis log file.
908 \section{fsm\_map -- mapping FSMs to basic logic}
910 \begin{lstlisting}[numbers=left,frame=single]
913 This pass translates FSM cells to flip-flops and logic.
916 \section{fsm\_opt -- optimize finite state machines}
918 \begin{lstlisting}[numbers=left,frame=single]
921 This pass optimizes FSM cells. It detects which output signals are actually
922 not used and removes them from the FSM. This pass is usually used in
923 combination with the 'opt_clean' pass (see also 'help fsm').
926 \section{fsm\_recode -- recoding finite state machines}
927 \label{cmd:fsm_recode}
928 \begin{lstlisting}[numbers=left,frame=single]
929 fsm_recode [options] [selection]
931 This pass reassign the state encodings for FSM cells. At the moment only
932 one-hot encoding and binary encoding is supported.
934 specify the encoding scheme used for FSMs without the
935 'fsm_encoding' attribute or with the attribute set to `auto'.
937 -fm_set_fsm_file <file>
938 generate a file containing the mapping from old to new FSM encoding
939 in form of Synopsys Formality set_fsm_* commands.
942 write the mappings from old to new FSM encoding to a file in the
945 .fsm <module_name> <state_signal>
946 .map <old_bitpattern> <new_bitpattern>
949 \section{help -- display help messages}
951 \begin{lstlisting}[numbers=left,frame=single]
952 help ............. list all commands
953 help <command> ... print help message for given command
954 help -all ........ print complete command reference
957 \section{hierarchy -- check, expand and clean up design hierarchy}
958 \label{cmd:hierarchy}
959 \begin{lstlisting}[numbers=left,frame=single]
960 hierarchy [-check] [-top <module>]
961 hierarchy -generate <cell-types> <port-decls>
963 In parametric designs, a module might exists in several variations with
964 different parameter values. This pass looks at all modules in the current
965 design an re-runs the language frontends for the parametric modules as
969 also check the design hierarchy. this generates an error when
970 an unknown module is used as cell type.
973 by default the hierarchy command will not remove library (blackbox)
974 modules. use this option to also remove unused blackbox modules.
977 search for files named <module_name>.v in the specified directory
978 for unknown modules and automatically run read_verilog for each
982 per default this pass also converts positional arguments in cells
983 to arguments using port names. this option disables this behavior.
986 per default this pass sets the "keep" attribute on all modules
987 that directly or indirectly contain one or more $assert cells. this
988 option disables this behavior.
991 use the specified top module to built a design hierarchy. modules
992 outside this tree (unused modules) are removed.
994 when the -top option is used, the 'top' attribute will be set on the
995 specified top module. otherwise a module with the 'top' attribute set
996 will implicitly be used as top module, if such a module exists.
999 automatically determine the top of the design hierarchy and mark it.
1001 In -generate mode this pass generates blackbox modules for the given cell
1002 types (wildcards supported). For this the design is searched for cells that
1003 match the given types and then the given port declarations are used to
1004 determine the direction of the ports. The syntax for a port declaration is:
1006 {i|o|io}[@<num>]:<portname>
1008 Input ports are specified with the 'i' prefix, output ports with the 'o'
1009 prefix and inout ports with the 'io' prefix. The optional <num> specifies
1010 the position of the port in the parameter list (needed when instantiated
1011 using positional arguments). When <num> is not specified, the <portname> can
1012 also contain wildcard characters.
1014 This pass ignores the current selection and always operates on all modules
1015 in the current design.
1018 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers}
1020 \begin{lstlisting}[numbers=left,frame=single]
1021 hilomap [options] [selection]
1023 Map constants to 'tielo' and 'tiehi' driver cells.
1025 -hicell <celltype> <portname>
1026 Replace constant hi bits with this cell.
1028 -locell <celltype> <portname>
1029 Replace constant lo bits with this cell.
1032 Create only one hi/lo cell and connect all constant bits
1033 to that cell. Per default a separate cell is created for
1037 \section{history -- show last interactive commands}
1039 \begin{lstlisting}[numbers=left,frame=single]
1042 This command prints all commands in the shell history buffer. This are
1043 all commands executed in an interactive session, but not the commands
1044 from executed scripts.
1047 \section{ice40\_ffssr -- iCE40: merge synchronous set/reset into FF cells}
1048 \label{cmd:ice40_ffssr}
1049 \begin{lstlisting}[numbers=left,frame=single]
1050 ice40_ffssr [options] [selection]
1052 Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.
1055 \section{ice40\_opt -- iCE40: perform simple optimizations}
1056 \label{cmd:ice40_opt}
1057 \begin{lstlisting}[numbers=left,frame=single]
1058 ice40_opt [options] [selection]
1060 This command executes the following script:
1063 <ice40 specific optimizations>
1064 opt_const -mux_undef -undriven [-full]
1068 while <changed design>
1071 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
1072 \label{cmd:iopadmap}
1073 \begin{lstlisting}[numbers=left,frame=single]
1074 iopadmap [options] [selection]
1076 Map module inputs/outputs to PAD cells from a library. This pass
1077 can only map to very simple PAD cells. Use 'techmap' to further map
1078 the resulting cells to more sophisticated PAD cells.
1080 -inpad <celltype> <portname>[:<portname>]
1081 Map module input ports to the given cell type with
1082 the given port name. if a 2nd portname is given, the
1083 signal is passed through the pad call, using the 2nd
1086 -outpad <celltype> <portname>[:<portname>]
1087 -inoutpad <celltype> <portname>[:<portname>]
1088 Similar to -inpad, but for output and inout ports.
1090 -widthparam <param_name>
1091 Use the specified parameter name to set the port width.
1093 -nameparam <param_name>
1094 Use the specified parameter to set the port name.
1097 create individual bit-wide buffers even for ports that
1098 are wider. (the default behavior is to create word-wide
1099 buffers using -widthparam to set the word size on the cell.)
1102 \section{json -- write design in JSON format}
1104 \begin{lstlisting}[numbers=left,frame=single]
1105 json [options] [selection]
1107 Write a JSON netlist of all selected objects.
1110 write to the specified file.
1113 also include AIG models for the different gate types
1115 See 'help write_json' for a description of the JSON format used.
1118 \section{log -- print text and log files}
1120 \begin{lstlisting}[numbers=left,frame=single]
1123 Print the given string to the screen and/or the log file. This is useful for TCL
1124 scripts, because the TCL command "puts" only goes to stdout but not to
1128 Print the output to stdout too. This is useful when all Yosys is executed
1129 with a script and the -q (quiet operation) argument to notify the user.
1132 Print the output to stderr too.
1135 Don't use the internal log() command. Use either -stdout or -stderr,
1136 otherwise no output will be generated at all.
1139 do not append a newline
1142 \section{ls -- list modules or objects in modules}
1144 \begin{lstlisting}[numbers=left,frame=single]
1147 When no active module is selected, this prints a list of modules.
1149 When an active module is selected, this prints a list of objects in the module.
1152 \section{maccmap -- mapping macc cells}
1154 \begin{lstlisting}[numbers=left,frame=single]
1155 maccmap [-unmap] [selection]
1157 This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
1158 is used then the $macc cell is mapped to $add, $sub, etc. cells instead.
1161 \section{memory -- translate memories to basic cells}
1163 \begin{lstlisting}[numbers=left,frame=single]
1164 memory [-nomap] [-nordff] [-bram <bram_rules>] [selection]
1166 This pass calls all the other memory_* passes in a useful order:
1168 memory_dff [-nordff]
1173 memory_bram -rules <bram_rules> (when called with -bram)
1174 memory_map (skipped if called with -nomap)
1176 This converts memories to word-wide DFFs and address decoders
1177 or multiport memory blocks if called with the -nomap option.
1180 \section{memory\_bram -- map memories to block rams}
1181 \label{cmd:memory_bram}
1182 \begin{lstlisting}[numbers=left,frame=single]
1183 memory_bram -rules <rule_file> [selection]
1185 This pass converts the multi-port $mem memory cells into block ram instances.
1186 The given rules file describes the available resources and how they should be
1189 The rules file contains a set of block ram description and a sequence of match
1190 rules. A block ram description looks like this:
1192 bram RAMB1024X32 # name of BRAM cell
1193 init 1 # set to '1' if BRAM can be initialized
1194 abits 10 # number of address bits
1195 dbits 32 # number of data bits
1196 groups 2 # number of port groups
1197 ports 1 1 # number of ports in each group
1198 wrmode 1 0 # set to '1' if this groups is write ports
1199 enable 4 0 # number of enable bits (for write ports)
1200 transp 0 2 # transparent (for read ports)
1201 clocks 1 2 # clock configuration
1202 clkpol 2 2 # clock polarity configuration
1205 For the option 'transp' the value 0 means non-transparent, 1 means transparent
1206 and a value greater than 1 means configurable. All groups with the same
1207 value greater than 1 share the same configuration bit.
1209 For the option 'clocks' the value 0 means non-clocked, and a value greater
1210 than 0 means clocked. All groups with the same value share the same clock
1213 For the option 'clkpol' the value 0 means negative edge, 1 means positive edge
1214 and a value greater than 1 means configurable. All groups with the same value
1215 greater than 1 share the same configuration bit.
1217 Using the same bram name in different bram blocks will create different variants
1218 of the bram. Verilog configuration parameters for the bram are created as needed.
1220 It is also possible to create variants by repeating statements in the bram block
1221 and appending '@<label>' to the individual statements.
1223 A match rule looks like this:
1226 max waste 16384 # only use this bram if <= 16k ram bits are unused
1227 min efficiency 80 # only use this bram if efficiency is at least 80%
1230 It is possible to match against the following values with min/max rules:
1232 words ........ number of words in memory in design
1233 abits ........ number of address bits on memory in design
1234 dbits ........ number of data bits on memory in design
1235 wports ....... number of write ports on memory in design
1236 rports ....... number of read ports on memory in design
1237 ports ........ number of ports on memory in design
1238 bits ......... number of bits in memory in design
1239 dups .......... number of duplications for more read ports
1241 awaste ....... number of unused address slots for this match
1242 dwaste ....... number of unused data bits for this match
1243 bwaste ....... number of unused bram bits for this match
1244 waste ........ total number of unused bram bits (bwaste*dups)
1245 efficiency ... total percentage of used and non-duplicated bits
1247 acells ....... number of cells in 'address-direction'
1248 dcells ....... number of cells in 'data-direction'
1249 cells ........ total number of cells (acells*dcells*dups)
1251 The interface for the created bram instances is derived from the bram
1252 description. Use 'techmap' to convert the created bram instances into
1253 instances of the actual bram cells of your target architecture.
1255 A match containing the command 'or_next_if_better' is only used if it
1256 has a higher efficiency than the next match (and the one after that if
1257 the next also has 'or_next_if_better' set, and so forth).
1259 A match containing the command 'make_transp' will add external circuitry
1260 to simulate 'transparent read', if necessary.
1262 A match containing the command 'make_outreg' will add external flip-flops
1263 to implement synchronous read ports, if necessary.
1265 A match containing the command 'shuffle_enable A' will re-organize
1266 the data bits to accommodate the enable pattern of port A.
1269 \section{memory\_collect -- creating multi-port memory cells}
1270 \label{cmd:memory_collect}
1271 \begin{lstlisting}[numbers=left,frame=single]
1272 memory_collect [selection]
1274 This pass collects memories and memory ports and creates generic multiport
1278 \section{memory\_dff -- merge input/output DFFs into memories}
1279 \label{cmd:memory_dff}
1280 \begin{lstlisting}[numbers=left,frame=single]
1281 memory_dff [options] [selection]
1283 This pass detects DFFs at memory ports and merges them into the memory port.
1284 I.e. it consumes an asynchronous memory port and the flip-flops at its
1285 interface and yields a synchronous memory port.
1288 do not merge registers on read ports
1291 \section{memory\_map -- translate multiport memories to basic cells}
1292 \label{cmd:memory_map}
1293 \begin{lstlisting}[numbers=left,frame=single]
1294 memory_map [selection]
1296 This pass converts multiport memory cells as generated by the memory_collect
1297 pass to word-wide DFFs and address decoders.
1300 \section{memory\_share -- consolidate memory ports}
1301 \label{cmd:memory_share}
1302 \begin{lstlisting}[numbers=left,frame=single]
1303 memory_share [selection]
1305 This pass merges share-able memory ports into single memory ports.
1307 The following methods are used to consolidate the number of memory ports:
1309 - When write ports are connected to async read ports accessing the same
1310 address, then this feedback path is converted to a write port with
1311 byte/part enable signals.
1313 - When multiple write ports access the same address then this is converted
1314 to a single write port with a more complex data and/or enable logic path.
1316 - When multiple write ports are never accessed at the same time (a SAT
1317 solver is used to determine this), then the ports are merged into a single
1320 Note that in addition to the algorithms implemented in this pass, the $memrd
1321 and $memwr cells are also subject to generic resource sharing passes (and other
1322 optimizations) such as opt_share.
1325 \section{memory\_unpack -- unpack multi-port memory cells}
1326 \label{cmd:memory_unpack}
1327 \begin{lstlisting}[numbers=left,frame=single]
1328 memory_unpack [selection]
1330 This pass converts the multi-port $mem memory cells into individual $memrd and
1331 $memwr cells. It is the counterpart to the memory_collect pass.
1334 \section{miter -- automatically create a miter circuit}
1336 \begin{lstlisting}[numbers=left,frame=single]
1337 miter -equiv [options] gold_name gate_name miter_name
1339 Creates a miter circuit for equivalence checking. The gold- and gate- modules
1340 must have the same interfaces. The miter circuit will have all inputs of the
1341 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
1342 output that goes high if an output mismatch between the two source modules is
1346 a undef (x) bit in the gold module output will match any value in
1347 the gate module output.
1350 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
1351 on the miter circuit.
1354 also create a cmp_* output for each gold/gate output pair.
1357 also create an 'assert' cell that checks if trigger is always low.
1360 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
1363 miter -assert [options] module [miter_name]
1365 Creates a miter circuit for property checking. All input ports are kept,
1366 output ports are discarded. An additional output 'trigger' is created that
1367 goes high when an assert is violated. Without a miter_name, the existing
1371 keep module output ports.
1374 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
1377 \section{muxcover -- cover trees of MUX cells with wider MUXes}
1378 \label{cmd:muxcover}
1379 \begin{lstlisting}[numbers=left,frame=single]
1380 muxcover [options] [selection]
1382 Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells
1384 -mux4, -mux8, -mux16
1385 Use the specified types of MUXes. If none of those options are used,
1386 the effect is the same as if all of them where used.
1389 Do not insert decoder logic. This reduces the number of possible
1390 substitutions, but guarantees that the resulting circuit is not
1391 less efficient than the original circuit.
1394 \section{opt -- perform simple optimizations}
1396 \begin{lstlisting}[numbers=left,frame=single]
1397 opt [options] [selection]
1399 This pass calls all the other opt_* passes in a useful order. This performs
1400 a series of trivial optimizations and cleanups. This pass executes the other
1401 passes in the following order:
1403 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1404 opt_share [-share_all] -nomux
1408 opt_reduce [-fine] [-full]
1409 opt_share [-share_all]
1412 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1413 while <changed design>
1415 When called with -fast the following script is used instead:
1418 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1419 opt_share [-share_all]
1422 while <changed design in opt_rmdff>
1424 Note: Options in square brackets (such as [-keepdc]) are passed through to
1425 the opt_* commands when given to 'opt'.
1428 \section{opt\_clean -- remove unused cells and wires}
1429 \label{cmd:opt_clean}
1430 \begin{lstlisting}[numbers=left,frame=single]
1431 opt_clean [options] [selection]
1433 This pass identifies wires and cells that are unused and removes them. Other
1434 passes often remove cells but leave the wires in the design or reconnect the
1435 wires but leave the old cells in the design. This pass can be used to clean up
1436 after the passes that do the actual work.
1438 This pass only operates on completely selected modules without processes.
1441 also remove internal nets if they have a public name
1444 \section{opt\_const -- perform const folding}
1445 \label{cmd:opt_const}
1446 \begin{lstlisting}[numbers=left,frame=single]
1447 opt_const [options] [selection]
1449 This pass performs const folding on internal cell types with constant inputs.
1452 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
1455 replace $mux cells with inverters or buffers when possible
1458 replace undriven nets with undef (x) constants
1461 optimize clock inverters by changing FF types
1464 perform fine-grain optimizations
1467 alias for -mux_undef -mux_bool -undriven -fine
1470 some optimizations change the behavior of the circuit with respect to
1471 don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
1472 all result bits to be set to x. this behavior changes when 'a+0' is
1473 replaced by 'a'. the -keepdc option disables all such optimizations.
1476 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
1477 \label{cmd:opt_muxtree}
1478 \begin{lstlisting}[numbers=left,frame=single]
1479 opt_muxtree [selection]
1481 This pass analyzes the control signals for the multiplexer trees in the design
1482 and identifies inputs that can never be active. It then removes this dead
1483 branches from the multiplexer trees.
1485 This pass only operates on completely selected modules without processes.
1488 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
1489 \label{cmd:opt_reduce}
1490 \begin{lstlisting}[numbers=left,frame=single]
1491 opt_reduce [options] [selection]
1493 This pass performs two interlinked optimizations:
1495 1. it consolidates trees of large AND gates or OR gates and eliminates
1498 2. it identifies duplicated inputs to MUXes and replaces them with a single
1499 input with the original control signals OR'ed together.
1502 perform fine-grain optimizations
1508 \section{opt\_rmdff -- remove DFFs with constant inputs}
1509 \label{cmd:opt_rmdff}
1510 \begin{lstlisting}[numbers=left,frame=single]
1511 opt_rmdff [selection]
1513 This pass identifies flip-flops with constant inputs and replaces them with
1517 \section{opt\_share -- consolidate identical cells}
1518 \label{cmd:opt_share}
1519 \begin{lstlisting}[numbers=left,frame=single]
1520 opt_share [options] [selection]
1522 This pass identifies cells with identical type and input signals. Such cells
1523 are then merged to one cell.
1526 Do not merge MUX cells.
1529 Operate on all cell types, not just built-in types.
1532 \section{plugin -- load and list loaded plugins}
1534 \begin{lstlisting}[numbers=left,frame=single]
1537 Load and list loaded plugins.
1539 -i <plugin_filename>
1540 Load (install) the specified plugin.
1543 Register the specified alias name for the loaded plugin
1549 \section{pmuxtree -- transform \$pmux cells to trees of \$mux cells}
1550 \label{cmd:pmuxtree}
1551 \begin{lstlisting}[numbers=left,frame=single]
1552 pmuxtree [options] [selection]
1554 This pass transforms $pmux cells to a trees of $mux cells.
1557 \section{proc -- translate processes to netlists}
1559 \begin{lstlisting}[numbers=left,frame=single]
1560 proc [options] [selection]
1562 This pass calls all the other proc_* passes in the most common order.
1573 This replaces the processes in the design with multiplexers,
1574 flip-flops and latches.
1576 The following options are supported:
1578 -global_arst [!]<netname>
1579 This option is passed through to proc_arst.
1582 \section{proc\_arst -- detect asynchronous resets}
1583 \label{cmd:proc_arst}
1584 \begin{lstlisting}[numbers=left,frame=single]
1585 proc_arst [-global_arst [!]<netname>] [selection]
1587 This pass identifies asynchronous resets in the processes and converts them
1588 to a different internal representation that is suitable for generating
1589 flip-flop cells with asynchronous resets.
1591 -global_arst [!]<netname>
1592 In modules that have a net with the given name, use this net as async
1593 reset for registers that have been assign initial values in their
1594 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
1595 active low reset signals. Note: the frontend stores the default value
1596 in the 'init' attribute on the net.
1599 \section{proc\_clean -- remove empty parts of processes}
1600 \label{cmd:proc_clean}
1601 \begin{lstlisting}[numbers=left,frame=single]
1602 proc_clean [selection]
1604 This pass removes empty parts of processes and ultimately removes a process
1605 if it contains only empty structures.
1608 \section{proc\_dff -- extract flip-flops from processes}
1609 \label{cmd:proc_dff}
1610 \begin{lstlisting}[numbers=left,frame=single]
1611 proc_dff [selection]
1613 This pass identifies flip-flops in the processes and converts them to
1614 d-type flip-flop cells.
1617 \section{proc\_dlatch -- extract latches from processes}
1618 \label{cmd:proc_dlatch}
1619 \begin{lstlisting}[numbers=left,frame=single]
1620 proc_dlatch [selection]
1622 This pass identifies latches in the processes and converts them to
1626 \section{proc\_init -- convert initial block to init attributes}
1627 \label{cmd:proc_init}
1628 \begin{lstlisting}[numbers=left,frame=single]
1629 proc_init [selection]
1631 This pass extracts the 'init' actions from processes (generated from Verilog
1632 'initial' blocks) and sets the initial value to the 'init' attribute on the
1636 \section{proc\_mux -- convert decision trees to multiplexers}
1637 \label{cmd:proc_mux}
1638 \begin{lstlisting}[numbers=left,frame=single]
1639 proc_mux [selection]
1641 This pass converts the decision trees in processes (originating from if-else
1642 and case statements) to trees of multiplexer cells.
1645 \section{proc\_rmdead -- eliminate dead trees in decision trees}
1646 \label{cmd:proc_rmdead}
1647 \begin{lstlisting}[numbers=left,frame=single]
1648 proc_rmdead [selection]
1650 This pass identifies unreachable branches in decision trees and removes them.
1653 \section{read\_blif -- read BLIF file}
1654 \label{cmd:read_blif}
1655 \begin{lstlisting}[numbers=left,frame=single]
1656 read_blif [filename]
1658 Load modules from a BLIF file into the current design.
1661 \section{read\_ilang -- read modules from ilang file}
1662 \label{cmd:read_ilang}
1663 \begin{lstlisting}[numbers=left,frame=single]
1664 read_ilang [filename]
1666 Load modules from an ilang file to the current design. (ilang is a text
1667 representation of a design in yosys's internal format.)
1670 \section{read\_liberty -- read cells from liberty file}
1671 \label{cmd:read_liberty}
1672 \begin{lstlisting}[numbers=left,frame=single]
1673 read_liberty [filename]
1675 Read cells from liberty file as modules into current design.
1678 only create empty blackbox modules
1681 ignore re-definitions of modules. (the default behavior is to
1682 create an error message.)
1685 ignore cells with missing function specification of outputs
1688 ignore cells with a missing or invalid direction
1689 specification on a pin
1691 -setattr <attribute_name>
1692 set the specified attribute (to the value 1) on all loaded modules
1695 \section{read\_verilog -- read modules from Verilog file}
1696 \label{cmd:read_verilog}
1697 \begin{lstlisting}[numbers=left,frame=single]
1698 read_verilog [options] [filename]
1700 Load modules from a Verilog file to the current design. A large subset of
1701 Verilog-2005 is supported.
1704 enable support for SystemVerilog features. (only a small subset
1705 of SystemVerilog is supported)
1708 enable support for assert() and assume() statements
1709 (assert support is also enabled with -sv)
1712 dump abstract syntax tree (before simplification)
1715 dump abstract syntax tree (after simplification)
1718 dump ast as Verilog code (after simplification)
1721 enable parser debug output
1724 usually latches are synthesized into logic loops
1725 this option prohibits this and sets the output to 'x'
1726 in what would be the latches hold condition
1728 this behavior can also be achieved by setting the
1729 'nolatches' attribute on the respective module or
1733 under certain conditions memories are converted to registers
1734 early during simplification to ensure correct handling of
1735 complex corner cases. this option disables this behavior.
1737 this can also be achieved by setting the 'nomem2reg'
1738 attribute on the respective module or register.
1740 This is potentially dangerous. Usually the front-end has good
1741 reasons for converting an array to a list of registers.
1742 Prohibiting this step will likely result in incorrect synthesis
1746 always convert memories to registers. this can also be
1747 achieved by setting the 'mem2reg' attribute on the respective
1751 do not infer $meminit cells and instead convert initialized
1752 memories to registers directly in the front-end.
1755 dump Verilog code after pre-processor
1758 do not run the pre-processor
1761 only create empty blackbox modules. This implies -DBLACKBOX.
1764 don't perform basic optimizations (such as const folding) in the
1765 high-level front-end.
1768 interpret cell types starting with '$' as internal cell types
1771 ignore re-definitions of modules. (the default behavior is to
1772 create an error message.)
1775 only read the abstract syntax tree and defer actual compilation
1776 to a later 'hierarchy' command. Useful in cases where the default
1777 parameters of modules yield invalid or not synthesizable code.
1780 make the default of `default_nettype be "none" instead of "wire".
1782 -setattr <attribute_name>
1783 set the specified attribute (to the value 1) on all loaded modules
1786 define the preprocessor symbol 'name' and set its optional value
1790 add 'dir' to the directories which are used when searching include
1793 The command 'verilog_defaults' can be used to register default options for
1794 subsequent calls to 'read_verilog'.
1796 Note that the Verilog frontend does a pretty good job of processing valid
1797 verilog input, but has not very good error reporting. It generally is
1798 recommended to use a simulator (for example Icarus Verilog) for checking
1799 the syntax of the code, rather than to rely on read_verilog for that.
1802 \section{rename -- rename object in the design}
1804 \begin{lstlisting}[numbers=left,frame=single]
1805 rename old_name new_name
1807 Rename the specified object. Note that selection patterns are not supported
1811 rename -enumerate [-pattern <pattern>] [selection]
1813 Assign short auto-generated names to all selected wires and cells with private
1814 names. The -pattern option can be used to set the pattern for the new names.
1815 The character % in the pattern is replaced with a integer number. The default
1818 rename -hide [selection]
1820 Assign private names (the ones with $-prefix) to all selected wires and cells
1821 with public names. This ignores all selected ports.
1823 rename -top new_name
1828 \section{sat -- solve a SAT problem in the circuit}
1830 \begin{lstlisting}[numbers=left,frame=single]
1831 sat [options] [selection]
1833 This command solves a SAT problem defined over the currently selected circuit
1834 and additional constraints passed as parameters.
1837 show all solutions to the problem (this can grow exponentially, use
1838 -max <N> instead to get <N> solutions)
1841 like -all, but limit number of solutions to <N>
1844 enable modeling of undef value (aka 'x-bits')
1845 this option is implied by -set-def, -set-undef et. cetera
1848 maximize the number of undef bits in solutions, giving a better
1849 picture of which input bits are actually vital to the solution.
1851 -set <signal> <value>
1852 set the specified signal to the specified value.
1855 add a constraint that all bits of the given signal must be defined
1857 -set-any-undef <signal>
1858 add a constraint that at least one bit of the given signal is undefined
1860 -set-all-undef <signal>
1861 add a constraint that all bits of the given signal are undefined
1864 add -set-def constraints for all module inputs
1867 show the model for the specified signal. if no -show option is
1868 passed then a set of signals to be shown is automatically selected.
1870 -show-inputs, -show-outputs, -show-ports
1871 add all module (input/output) ports to the list of shown signals
1874 ignore all solutions that involve a division by zero
1876 -ignore_unknown_cells
1877 ignore all cells that can not be matched to a SAT model
1879 The following options can be used to set up a sequential problem:
1882 set up a sequential problem with <N> time steps. The steps will
1883 be numbered from 1 to N.
1885 note: for large <N> it can be significantly faster to use
1886 -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.
1888 -set-at <N> <signal> <value>
1889 -unset-at <N> <signal>
1890 set or unset the specified signal to the specified value in the
1891 given timestep. this has priority over a -set for the same signal.
1894 set all assumptions provided via $assume cells
1896 -set-def-at <N> <signal>
1897 -set-any-undef-at <N> <signal>
1898 -set-all-undef-at <N> <signal>
1899 add undef constraints in the given timestep.
1901 -set-init <signal> <value>
1902 set the initial value for the register driving the signal to the value
1905 set all initial states (not set using -set-init) to undef
1908 do not force a value for the initial state but do not allow undef
1911 set all initial states (not set using -set-init) to zero
1913 -dump_vcd <vcd-file-name>
1914 dump SAT model (counter example in proof) to VCD file
1916 -dump_json <json-file-name>
1917 dump SAT model (counter example in proof) to a WaveJSON file.
1919 -dump_cnf <cnf-file-name>
1920 dump CNF of SAT problem (in DIMACS format). in temporal induction
1921 proofs this is the CNF of the first induction step.
1923 The following additional options can be used to set up a proof. If also -seq
1924 is passed, a temporal induction proof is performed.
1927 Perform a temporal induction proof. In a temporal induction proof it is
1928 proven that the condition holds forever after the number of time steps
1929 specified using -seq.
1932 Perform a temporal induction proof. Assume an initial state with all
1933 registers set to defined values for the induction step.
1935 -tempinduct-baseonly
1936 Run only the basecase half of temporal induction (requires -maxsteps)
1938 -tempinduct-inductonly
1939 Run only the induction half of temporal induction
1941 -tempinduct-skip <N>
1942 Skip the first <N> steps of the induction proof.
1944 note: this will assume that the base case holds for <N> steps.
1945 this must be proven independently with "-tempinduct-baseonly
1946 -maxsteps <N>". Use -initsteps if you just want to set a
1947 minimal induction length.
1949 -prove <signal> <value>
1950 Attempt to proof that <signal> is always <value>.
1952 -prove-x <signal> <value>
1953 Like -prove, but an undef (x) bit in the lhs matches any value on
1954 the right hand side. Useful for equivalence checking.
1957 Prove that all asserts in the design hold.
1960 Do not enforce the prove-condition for the first <N> time steps.
1963 Set a maximum length for the induction.
1966 Set initial length for the induction.
1967 This will speed up the search of the right induction length
1968 for deep induction proofs.
1971 Increase the size of the induction proof in steps of <N>.
1972 This will speed up the search of the right induction length
1973 for deep induction proofs.
1976 Maximum number of seconds a single SAT instance may take.
1979 Return an error and stop the synthesis script if the proof fails.
1982 Like -verify but do not return an error for timeouts.
1985 Return an error and stop the synthesis script if the proof succeeds.
1988 Like -falsify but do not return an error for timeouts.
1991 \section{scatter -- add additional intermediate nets}
1993 \begin{lstlisting}[numbers=left,frame=single]
1996 This command adds additional intermediate nets on all cell ports. This is used
1997 for testing the correct use of the SigMap helper in passes. If you don't know
1998 what this means: don't worry -- you only need this pass when testing your own
1999 extensions to Yosys.
2001 Use the opt_clean command to get rid of the additional nets.
2004 \section{scc -- detect strongly connected components (logic loops)}
2006 \begin{lstlisting}[numbers=left,frame=single]
2007 scc [options] [selection]
2009 This command identifies strongly connected components (aka logic loops) in the
2013 expect to find exactly <num> SSCs. A different number of SSCs will
2017 limit to loops not longer than the specified number of cells. This
2018 can e.g. be useful in identifying small local loops in a module that
2019 implements one large SCC.
2022 do not count cells that have their output fed back into one of their
2023 inputs as single-cell scc.
2026 Usually this command only considers internal non-memory cells. With
2027 this option set, all cells are considered. For unknown cells all ports
2028 are assumed to be bidirectional 'inout' ports.
2030 -set_attr <name> <value>
2031 -set_cell_attr <name> <value>
2032 -set_wire_attr <name> <value>
2033 set the specified attribute on all cells and/or wires that are part of
2034 a logic loop. the special token {} in the value is replaced with a
2035 unique identifier for the logic loop.
2038 replace the current selection with a selection of all cells and wires
2039 that are part of a found logic loop
2042 \section{script -- execute commands from script file}
2044 \begin{lstlisting}[numbers=left,frame=single]
2045 script <filename> [<from_label>:<to_label>]
2047 This command executes the yosys commands in the specified file.
2049 The 2nd argument can be used to only execute the section of the
2050 file between the specified labels. An empty from label is synonymous
2051 for the beginning of the file and an empty to label is synonymous
2052 for the end of the file.
2054 If only one label is specified (without ':') then only the block
2055 marked with that label (until the next label) is executed.
2058 \section{select -- modify and view the list of selected objects}
2060 \begin{lstlisting}[numbers=left,frame=single]
2061 select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
2062 select [ -assert-none | -assert-any ] {-read <filename> | <selection>}
2063 select [ -list | -write <filename> | -count | -clear ]
2064 select -module <modname>
2066 Most commands use the list of currently selected objects to determine which part
2067 of the design to operate on. This command can be used to modify and view this
2068 list of selected objects.
2070 Note that many commands support an optional [selection] argument that can be
2071 used to override the global selection for the command. The syntax of this
2072 optional argument is identical to the syntax of the <selection> argument
2076 add or remove the given objects to the current selection.
2077 without this options the current selection is replaced.
2080 do not modify the current selection. instead save the new selection
2081 under the given name (see @<name> below). to save the current selection,
2082 use "select -set <name> %"
2085 do not modify the current selection. instead assert that the given
2086 selection is empty. i.e. produce an error if any object matching the
2090 do not modify the current selection. instead assert that the given
2091 selection is non-empty. i.e. produce an error if no object matching
2092 the selection is found.
2095 do not modify the current selection. instead assert that the given
2096 selection contains exactly N objects.
2099 list all objects in the current selection
2102 like -list but write the output to the specified file
2105 read the specified file (written by -write)
2108 count all objects in the current selection
2111 clear the current selection. this effectively selects the whole
2112 design. it also resets the selected module (see -module). use the
2113 command 'select *' to select everything but stay in the current module.
2116 create an empty selection. the current module is unchanged.
2119 limit the current scope to the specified module.
2120 the difference between this and simply selecting the module
2121 is that all object names are interpreted relative to this
2122 module after this command until the selection is cleared again.
2124 When this command is called without an argument, the current selection
2125 is displayed in a compact form (i.e. only the module name when a whole module
2128 The <selection> argument itself is a series of commands for a simple stack
2129 machine. Each element on the stack represents a set of selected objects.
2130 After this commands have been executed, the union of all remaining sets
2131 on the stack is computed and used as selection for the command.
2133 Pushing (selecting) object when not in -module mode:
2136 select the specified module(s)
2138 <mod_pattern>/<obj_pattern>
2139 select the specified object(s) from the module(s)
2141 Pushing (selecting) object when in -module mode:
2144 select the specified object(s) from the current module
2146 A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
2147 matching module names, or one of the following:
2149 A:<pattern>, A:<pattern>=<pattern>
2150 all modules with an attribute matching the given pattern
2151 in addition to = also <, <=, >=, and > are supported
2153 An <obj_pattern> can be an object name, wildcard expression, or one of
2157 all wires with a name matching the given wildcard pattern
2159 i:<pattern>, o:<pattern>, x:<pattern>
2160 all inputs (i:), outputs (o:) or any ports (x:) with matching names
2162 s:<size>, s:<min>:<max>
2163 all wires with a matching width
2166 all memories with a name matching the given pattern
2169 all cells with a name matching the given pattern
2172 all cells with a type matching the given pattern
2175 all processes with a name matching the given pattern
2178 all objects with an attribute name matching the given pattern
2180 a:<pattern>=<pattern>
2181 all objects with a matching attribute name-value-pair.
2182 in addition to = also <, <=, >=, and > are supported
2184 r:<pattern>, r:<pattern>=<pattern>
2185 cells with matching parameters. also with <, <=, >= and >.
2188 all objects with a name matching the given pattern
2189 (i.e. 'n:' is optional as it is the default matching rule)
2192 push the selection saved prior with 'select -set <name> ...'
2194 The following actions can be performed on the top sets on the stack:
2197 push a copy of the current selection to the stack
2200 replace the stack with a union of all elements on it
2203 replace top set with its invert
2206 replace the two top sets on the stack with their union
2209 replace the two top sets on the stack with their intersection
2212 pop the top set from the stack and subtract it from the new top
2215 like %d but swap the roles of two top sets on the stack
2218 create a copy of the top set from the stack and push it
2220 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2221 expand top set <num1> num times according to the specified rules.
2222 (i.e. select all cells connected to selected wires and select all
2223 wires connected to selected cells) The rules specify which cell
2224 ports to use for this. the syntax for a rule is a '-' for exclusion
2225 and a '+' for inclusion, followed by an optional comma separated
2226 list of cell types followed by an optional comma separated list of
2227 cell ports in square brackets. a rule can also be just a cell or wire
2228 name that limits the expansion (is included but does not go beyond).
2229 select at most <num2> objects. a warning message is printed when this
2230 limit is reached. When '*' is used instead of <num1> then the process
2231 is repeated until no further object are selected.
2233 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2234 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2235 similar to %x, but only select input (%ci) or output cones (%co)
2237 %xe[...] %cie[...] %coe
2238 like %x, %ci, and %co but only consider combinatorial cells
2241 expand top set by selecting all wires that are (at least in part)
2242 aliases for selected wires.
2245 expand top set by adding all modules that implement cells in selected
2249 expand top set by selecting all modules that contain selected objects
2252 select modules that implement selected cells
2255 select cells that implement selected modules
2257 Example: the following command selects all wires that are connected to a
2258 'GATE' input of a 'SWITCH' cell:
2260 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
2263 \section{setattr -- set/unset attributes on objects}
2265 \begin{lstlisting}[numbers=left,frame=single]
2266 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
2268 Set/unset the given attributes on the selected objects. String values must be
2269 passed in double quotes (").
2271 When called with -mod, this command will set and unset attributes on modules
2272 instead of objects within modules.
2275 \section{setparam -- set/unset parameters on objects}
2276 \label{cmd:setparam}
2277 \begin{lstlisting}[numbers=left,frame=single]
2278 setparam [ -set name value | -unset name ]... [selection]
2280 Set/unset the given parameters on the selected cells. String values must be
2281 passed in double quotes (").
2284 \section{setundef -- replace undef values with defined constants}
2285 \label{cmd:setundef}
2286 \begin{lstlisting}[numbers=left,frame=single]
2287 setundef [options] [selection]
2289 This command replaced undef (x) constants with defined (0/1) constants.
2292 also set undriven nets to constant values
2295 replace with bits cleared (0)
2298 replace with bits set (1)
2301 replace with random bits using the specified integer als seed
2302 value for the random number generator.
2305 \section{share -- perform sat-based resource sharing}
2307 \begin{lstlisting}[numbers=left,frame=single]
2308 share [options] [selection]
2310 This pass merges shareable resources into a single resource. A SAT solver
2311 is used to determine if two resources are share-able.
2314 Per default the selection of cells that is considered for sharing is
2315 narrowed using a list of cell types. With this option all selected
2316 cells are considered for resource sharing.
2318 IMPORTANT NOTE: If the -all option is used then no cells with internal
2319 state must be selected!
2322 Per default some heuristics are used to reduce the number of cells
2323 considered for resource sharing to only large resources. This options
2324 turns this heuristics off, resulting in much more cells being considered
2325 for resource sharing.
2328 Only consider the simple part of the control logic in SAT solving, resulting
2329 in much easier SAT problems at the cost of maybe missing some opportunities
2330 for resource sharing.
2333 Only perform the first N merges, then stop. This is useful for debugging.
2336 \section{shell -- enter interactive command mode}
2338 \begin{lstlisting}[numbers=left,frame=single]
2341 This command enters the interactive command mode. This can be useful
2342 in a script to interrupt the script at a certain point and allow for
2343 interactive inspection or manual synthesis of the design at this point.
2345 The command prompt of the interactive shell indicates the current
2346 selection (see 'help select'):
2349 the entire design is selected
2352 only part of the design is selected
2355 the entire module 'modname' is selected using 'select -module modname'
2358 only part of current module 'modname' is selected
2360 When in interactive shell, some errors (e.g. invalid command arguments)
2361 do not terminate yosys but return to the command prompt.
2363 This command is the default action if nothing else has been specified
2364 on the command line.
2366 Press Ctrl-D or type 'exit' to leave the interactive shell.
2369 \section{show -- generate schematics using graphviz}
2371 \begin{lstlisting}[numbers=left,frame=single]
2372 show [options] [selection]
2374 Create a graphviz DOT file for the selected part of the design and compile it
2375 to a graphics file (usually SVG or PostScript).
2378 Run the specified command with the graphics file as parameter.
2381 Generate a graphics file in the specified format.
2382 Usually <format> is 'svg' or 'ps'.
2384 -lib <verilog_or_ilang_file>
2385 Use the specified library file for determining whether cell ports are
2386 inputs or outputs. This option can be used multiple times to specify
2387 more than one library.
2389 note: in most cases it is better to load the library before calling
2390 show with 'read_verilog -lib <filename>'. it is also possible to
2391 load liberty files with 'read_liberty -lib <filename>'.
2394 generate <prefix>.* instead of ~/.yosys_show.*
2396 -color <color> <object>
2397 assign the specified color to the specified object. The object can be
2398 a single selection wildcard expressions or a saved set of objects in
2399 the @<name> syntax (see "help select" for details).
2401 -label <text> <object>
2402 assign the specified label text to the specified object. The object can
2403 be a single selection wildcard expressions or a saved set of objects in
2404 the @<name> syntax (see "help select" for details).
2407 Randomly assign colors to the wires. The integer argument is the seed
2408 for the random number generator. Change the seed value if the colored
2409 graph still is ambiguous. A seed of zero deactivates the coloring.
2411 -colorattr <attribute_name>
2412 Use the specified attribute to assign colors. A unique color is
2413 assigned to each unique value of this attribute.
2416 annotate busses with a label indicating the width of the bus.
2419 mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
2420 cell parameter) with an asterisk next to the port name.
2423 stretch the graph so all inputs are on the left side and all outputs
2424 (including inout ports) are on the right side.
2427 wait for the use to press enter to before returning
2430 enumerate objects with internal ($-prefixed) names
2433 do not abbreviate objects with internal ($-prefixed) names
2436 do not add the module name as graph title to the dot file
2438 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
2439 specified, 'xdot' is used to display the schematic.
2441 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
2442 unless another prefix is specified using -prefix <prefix>.
2444 Yosys on Windows and YosysJS use different defaults: The output is written
2445 to 'show.dot' in the current directory and new viewer is launched.
2448 \section{simplemap -- mapping simple coarse-grain cells}
2449 \label{cmd:simplemap}
2450 \begin{lstlisting}[numbers=left,frame=single]
2451 simplemap [selection]
2453 This pass maps a small selection of simple coarse-grain cells to yosys gate
2454 primitives. The following internal cell types are mapped by this pass:
2456 $not, $pos, $and, $or, $xor, $xnor
2457 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
2458 $logic_not, $logic_and, $logic_or, $mux
2459 $sr, $dff, $dffsr, $adff, $dlatch
2462 \section{splice -- create explicit splicing cells}
2464 \begin{lstlisting}[numbers=left,frame=single]
2465 splice [options] [selection]
2467 This command adds $slice and $concat cells to the design to make the splicing
2468 of multi-bit signals explicit. This for example is useful for coarse grain
2469 synthesis, where dedicated hardware is needed to splice signals.
2472 only select the cell ports to rewire by the cell. if the selection
2473 contains a cell, than all cell inputs are rewired, if necessary.
2476 only select the cell ports to rewire by the wire. if the selection
2477 contains a wire, than all cell ports driven by this wire are wired,
2481 it is sufficient if the driver of any bit of a cell port is selected.
2482 by default all bits must be selected.
2485 also add $slice and $concat cells to drive otherwise unused wires.
2488 do not rewire selected module outputs.
2491 only rewire cell ports with the specified name. can be used multiple
2492 times. implies -no_output.
2495 do not rewire cell ports with the specified name. can be used multiple
2496 times. can not be combined with -port <name>.
2498 By default selected output wires and all cell ports of selected cells driven
2499 by selected wires are rewired.
2502 \section{splitnets -- split up multi-bit nets}
2503 \label{cmd:splitnets}
2504 \begin{lstlisting}[numbers=left,frame=single]
2505 splitnets [options] [selection]
2507 This command splits multi-bit nets into single-bit nets.
2509 -format char1[char2[char3]]
2510 the first char is inserted between the net name and the bit index, the
2511 second char is appended to the netname. e.g. -format () creates net
2512 names like 'mysignal(42)'. the 3rd character is the range separation
2513 character when creating multi-bit wires. the default is '[]:'.
2516 also split module ports. per default only internal signals are split.
2519 don't blindly split nets in individual bits. instead look at the driver
2520 and split nets so that no driver drives only part of a net.
2523 \section{stat -- print some statistics}
2525 \begin{lstlisting}[numbers=left,frame=single]
2526 stat [options] [selection]
2528 Print some statistics (number of objects) on the selected portion of the
2532 print design hierarchy with this module as top. if the design is fully
2533 selected and a module has the 'top' attribute set, this module is used
2534 default value for this option.
2537 annotate internal cell types with their word width.
2538 e.g. $add_8 for an 8 bit wide $add cell.
2541 \section{submod -- moving part of a module to a new submodule}
2543 \begin{lstlisting}[numbers=left,frame=single]
2546 This pass identifies all cells with the 'submod' attribute and moves them to
2547 a newly created module. The value of the attribute is used as name for the
2548 cell that replaces the group of cells with the same attribute value.
2550 This pass can be used to create a design hierarchy in flat design. This can
2551 be useful for analyzing or reverse-engineering a design.
2553 This pass only operates on completely selected modules with no processes
2557 submod -name <name> [selection]
2559 As above, but don't use the 'submod' attribute but instead use the selection.
2560 Only objects from one module might be selected. The value of the -name option
2561 is used as the value of the 'submod' attribute above.
2564 \section{synth -- generic synthesis script}
2566 \begin{lstlisting}[numbers=left,frame=single]
2569 This command runs the default synthesis script. This command does not operate
2570 on partly selected designs.
2573 use the specified module as top module (default='top')
2576 passed to 'fsm_recode' via 'fsm'
2579 do not run FSM optimization
2582 do not run abc (as if yosys was compiled without ABC support)
2585 do not run 'alumacc' pass. i.e. keep arithmetic operators in
2586 their direct form ($add, $sub, etc.).
2589 passed to 'memory'. prohibits merging of FFs into memory read ports
2591 -run <from_label>[:<to_label>]
2592 only run the commands between the labels (see below). an empty
2593 from label is synonymous to 'begin', and empty to label is
2594 synonymous to the end of the command list.
2597 The following commands are executed by this synthesis command:
2600 hierarchy -check [-top <top>]
2631 \section{synth\_ice40 -- synthesis for iCE40 FPGAs}
2632 \label{cmd:synth_ice40}
2633 \begin{lstlisting}[numbers=left,frame=single]
2634 synth_ice40 [options]
2636 This command runs synthesis for iCE40 FPGAs. This work is experimental.
2639 use the specified module as top module (default='top')
2642 write the design to the specified BLIF file. writing of an output file
2643 is omitted if this parameter is not specified.
2646 write the design to the specified edif file. writing of an output file
2647 is omitted if this parameter is not specified.
2649 -run <from_label>:<to_label>
2650 only run the commands between the labels (see below). an empty
2651 from label is synonymous to 'begin', and empty to label is
2652 synonymous to the end of the command list.
2655 do not flatten design before synthesis
2658 run 'abc' with -dff option
2661 do not use SB_CARRY cells in output netlist
2664 do not use SB_RAM40_4K* cells in output netlist
2667 The following commands are executed by this synthesis command:
2670 read_verilog -lib +/ice40/cells_sim.v
2671 hierarchy -check -top <top>
2673 flatten: (unless -noflatten)
2680 bram: (skip if -nobram)
2681 memory_bram -rules +/ice40/brams.txt
2682 techmap -map +/ice40/brams_map.v
2685 opt -fast -mux_undef -undriven -fine
2688 techmap -map +/techmap.v [-map +/ice40/arith_map.v]
2689 abc -dff (only if -retime)
2693 dff2dffe -direct-match $_DFF_*
2694 techmap -map +/ice40/cells_map.v
2695 opt_const -mux_undef
2705 techmap -map +/ice40/cells_map.v
2714 write_blif -gates -attr -param <file-name>
2717 write_edif <file-name>
2720 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
2721 \label{cmd:synth_xilinx}
2722 \begin{lstlisting}[numbers=left,frame=single]
2723 synth_xilinx [options]
2725 This command runs synthesis for Xilinx FPGAs. This command does not operate on
2726 partly selected designs. At the moment this command creates netlists that are
2727 compatible with 7-Series Xilinx devices.
2730 use the specified module as top module
2733 write the design to the specified edif file. writing of an output file
2734 is omitted if this parameter is not specified.
2736 -run <from_label>:<to_label>
2737 only run the commands between the labels (see below). an empty
2738 from label is synonymous to 'begin', and empty to label is
2739 synonymous to the end of the command list.
2742 flatten design before synthesis
2745 run 'abc' with -dff option
2748 The following commands are executed by this synthesis command:
2751 read_verilog -lib +/xilinx/cells_sim.v
2752 read_verilog -lib +/xilinx/brams_bb.v
2753 read_verilog -lib +/xilinx/drams_bb.v
2754 hierarchy -check -top <top>
2756 flatten: (only if -flatten)
2765 memory_bram -rules +/xilinx/brams.txt
2766 techmap -map +/xilinx/brams_map.v
2769 memory_bram -rules +/xilinx/drams.txt
2770 techmap -map +/xilinx/drams_map.v
2776 techmap -map +/techmap.v -map +/xilinx/arith_map.v
2784 techmap -map +/xilinx/cells_map.v
2785 dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
2793 edif: (only if -edif)
2794 write_edif <file-name>
2797 \section{tcl -- execute a TCL script file}
2799 \begin{lstlisting}[numbers=left,frame=single]
2802 This command executes the tcl commands in the specified file.
2803 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
2805 The tcl command 'yosys -import' can be used to import all yosys
2806 commands directly as tcl commands to the tcl shell. The yosys
2807 command 'proc' is wrapped using the tcl command 'procs' in order
2808 to avoid a name collision with the tcl builtin command 'proc'.
2811 \section{techmap -- generic technology mapper}
2813 \begin{lstlisting}[numbers=left,frame=single]
2814 techmap [-map filename] [selection]
2816 This pass implements a very simple technology mapper that replaces cells in
2817 the design with implementations given in form of a Verilog or ilang source
2821 the library of cell implementations to be used.
2822 without this parameter a builtin library is used that
2823 transforms the internal RTL cells to the internal gate
2827 like -map above, but with an in-memory design instead of a file.
2830 load the cell implementations as separate modules into the design
2831 instead of inlining them.
2834 only run the specified number of iterations.
2837 instead of the iterative breadth-first algorithm use a recursive
2838 depth-first algorithm. both methods should yield equivalent results,
2839 but may differ in performance.
2842 Automatically call "proc" on implementations that contain processes.
2845 this option will cause techmap to exit with an error if it can't map
2846 a selected cell. only cell types that end on an underscore are accepted
2847 as final cell types by this mode.
2849 -D <define>, -I <incdir>
2850 this options are passed as-is to the Verilog frontend for loading the
2851 map file. Note that the Verilog frontend is also called with the
2852 '-ignore_redef' option set.
2854 When a module in the map file has the 'techmap_celltype' attribute set, it will
2855 match cells with a type that match the text value of this attribute. Otherwise
2856 the module name will be used to match the cell.
2858 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
2859 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
2861 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
2862 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
2864 When a module in the map file has the 'techmap_wrap' attribute set, techmap
2865 will create a wrapper for the cell and then run the command string that the
2866 attribute is set to on the wrapper module.
2868 All wires in the modules from the map file matching the pattern _TECHMAP_*
2869 or *._TECHMAP_* are special wires that are used to pass instructions from
2870 the mapping module to the techmap command. At the moment the following special
2871 wires are supported:
2874 When this wire is set to a non-zero constant value, techmap will not
2875 use this module and instead try the next module with a matching
2876 'techmap_celltype' attribute.
2878 When such a wire exists but does not have a constant value after all
2879 _TECHMAP_DO_* commands have been executed, an error is generated.
2882 This wires are evaluated in alphabetical order. The constant text value
2883 of this wire is a yosys command (or sequence of commands) that is run
2884 by techmap on the module. A common use case is to run 'proc' on modules
2885 that are written using always-statements.
2887 When such a wire has a non-constant value at the time it is to be
2888 evaluated, an error is produced. That means it is possible for such a
2889 wire to start out as non-constant and evaluate to a constant value
2890 during processing of other _TECHMAP_DO_* commands.
2892 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
2893 in this case techmap will create a copy for each distinct configuration
2894 of constant inputs and shorted inputs at this point and import the
2895 constant and connected bits into the map module. All further commands
2896 are executed in this copy. This is a very convenient way of creating
2897 optimized specializations of techmap modules without using the special
2898 parameters described below.
2900 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
2901 then techmap will recursively replace the cells in the module with their
2902 implementation. This is not affected by the -max_iter option.
2904 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
2906 In addition to this special wires, techmap also supports special parameters in
2907 modules in the map file:
2910 When a parameter with this name exists, it will be set to the type name
2911 of the cell that matches the module.
2913 _TECHMAP_CONSTMSK_<port-name>_
2914 _TECHMAP_CONSTVAL_<port-name>_
2915 When this pair of parameters is available in a module for a port, then
2916 former has a 1-bit for each constant input bit and the latter has the
2917 value for this bit. The unused bits of the latter are set to undef (x).
2919 _TECHMAP_BITS_CONNMAP_
2920 _TECHMAP_CONNMAP_<port-name>_
2921 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
2922 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
2923 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
2924 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
2925 This can be used to detect shorted inputs.
2927 When a module in the map file has a parameter where the according cell in the
2928 design has a port, the module from the map file is only used if the port in
2929 the design is connected to a constant value. The parameter is then set to the
2932 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
2933 of the cell that is being replaced.
2935 See 'help extract' for a pass that does the opposite thing.
2937 See 'help flatten' for a pass that does flatten the design (which is
2938 essentially techmap but using the design itself as map library).
2941 \section{tee -- redirect command output to file}
2943 \begin{lstlisting}[numbers=left,frame=single]
2944 tee [-q] [-o logfile|-a logfile] cmd
2946 Execute the specified command, optionally writing the commands output to the
2947 specified logfile(s).
2950 Do not print output to the normal destination (console and/or log file)
2953 Write output to this file, truncate if exists.
2956 Write output to this file, append if exists.
2959 \section{test\_abcloop -- automatically test handling of loops in abc command}
2960 \label{cmd:test_abcloop}
2961 \begin{lstlisting}[numbers=left,frame=single]
2962 test_abcloop [options]
2964 Test handling of logic loops in ABC.
2967 create this number of circuits and test them (default = 100).
2969 -s {positive_integer}
2970 use this value as rng seed value (default = unix time).
2973 \section{test\_autotb -- generate simple test benches}
2974 \label{cmd:test_autotb}
2975 \begin{lstlisting}[numbers=left,frame=single]
2976 test_autotb [options] [filename]
2978 Automatically create primitive Verilog test benches for all modules in the
2979 design. The generated testbenches toggle the input pins of the module in
2980 a semi-random manner and dumps the resulting output signals.
2982 This can be used to check the synthesis results for simple circuits by
2983 comparing the testbench output for the input files and the synthesis results.
2985 The backend automatically detects clock signals. Additionally a signal can
2986 be forced to be interpreted as clock signal by setting the attribute
2987 'gentb_clock' on the signal.
2989 The attribute 'gentb_constant' can be used to force a signal to a constant
2990 value after initialization. This can e.g. be used to force a reset signal
2991 low in order to explore more inner states in a state machine.
2994 number of iterations the test bench should run (default = 1000)
2997 \section{test\_cell -- automatically test the implementation of a cell type}
2998 \label{cmd:test_cell}
2999 \begin{lstlisting}[numbers=left,frame=single]
3000 test_cell [options] {cell-types}
3002 Tests the internal implementation of the given cell type (for example '$add')
3003 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
3005 Run with 'all' instead of a cell type to run the test on all supported
3006 cell types. Use for example 'all /$add' for all cell types except $add.
3009 create this number of cell instances and test them (default = 100).
3011 -s {positive_integer}
3012 use this value as rng seed value (default = unix time).
3015 don't generate circuits. instead load the specified ilang file.
3017 -w {filename_prefix}
3018 don't test anything. just generate the circuits and write them
3019 to ilang files with the specified prefix
3022 pass this option to techmap.
3025 use "techmap -map +/simlib.v -max_iter 2 -autoproc"
3028 instead of calling "techmap", call "aigmap"
3031 when creating test benches with dividers, create an additional mux
3032 to mask out the division-by-zero case
3034 -script {script_file}
3035 instead of calling "techmap", call "script {script_file}".
3038 set some input bits to random constant values
3041 do not check SAT model or run SAT equivalence checking
3044 print additional debug information to the console
3047 create a Verilog test bench to test simlib and write_verilog
3050 \section{trace -- redirect command output to file}
3052 \begin{lstlisting}[numbers=left,frame=single]
3055 Execute the specified command, logging all changes the command performs on
3056 the design in real time.
3059 \section{verific -- load Verilog and VHDL designs using Verific}
3061 \begin{lstlisting}[numbers=left,frame=single]
3062 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
3064 Load the specified Verilog/SystemVerilog files into Verific.
3067 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
3069 Load the specified VHDL files into Verific.
3072 verific -import [-gates] {-all | <top-module>..}
3074 Elaborate the design for the specified top modules, import to Yosys and
3075 reset the internal state of Verific. A gate-level netlist is created
3076 when called with -gates.
3078 Visit http://verific.com/ for more information on Verific.
3081 \section{verilog\_defaults -- set default options for read\_verilog}
3082 \label{cmd:verilog_defaults}
3083 \begin{lstlisting}[numbers=left,frame=single]
3084 verilog_defaults -add [options]
3086 Add the specified options to the list of default options to read_verilog.
3089 verilog_defaults -clear
3090 Clear the list of Verilog default options.
3093 verilog_defaults -push verilog_defaults -pop
3094 Push or pop the list of default options to a stack. Note that -push does
3098 \section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
3099 \label{cmd:vhdl2verilog}
3100 \begin{lstlisting}[numbers=left,frame=single]
3101 vhdl2verilog [options] <vhdl-file>..
3103 This command reads VHDL source files using the 'vhdl2verilog' tool and the
3104 Yosys Verilog frontend.
3107 do not import the vhdl2verilog output. instead write it to the
3110 -vhdl2verilog_dir <directory>
3111 do use the specified vhdl2verilog installation. this is the directory
3112 that contains the setup_env.sh file. when this option is not present,
3113 it is assumed that vhdl2verilog is in the PATH environment variable.
3115 -top <top-entity-name>
3116 The name of the top entity. This option is mandatory.
3118 The following options are passed as-is to vhdl2verilog:
3120 -arch <architecture_name>
3130 vhdl2verilog can be obtained from:
3131 http://www.edautils.com/vhdl2verilog.html
3134 \section{wreduce -- reduce the word size of operations if possible}
3136 \begin{lstlisting}[numbers=left,frame=single]
3137 wreduce [options] [selection]
3139 This command reduces the word size of operations. For example it will replace
3140 the 32 bit adders in the following code with adders of more appropriate widths:
3142 module test(input [3:0] a, b, c, output [7:0] y);
3143 assign y = a + b + c + 1;
3147 \section{write\_blif -- write design to BLIF file}
3148 \label{cmd:write_blif}
3149 \begin{lstlisting}[numbers=left,frame=single]
3150 write_blif [options] [filename]
3152 Write the current design to an BLIF file.
3155 set the specified module as design top module
3157 -buf <cell-type> <in-port> <out-port>
3158 use cells of type <cell-type> with the specified port names for buffers
3160 -unbuf <cell-type> <in-port> <out-port>
3161 replace buffer cells with the specified name and port names with
3162 a .names statement that models a buffer
3164 -true <cell-type> <out-port>
3165 -false <cell-type> <out-port>
3166 -undef <cell-type> <out-port>
3167 use the specified cell types to drive nets that are constant 1, 0, or
3168 undefined. when '-' is used as <cell-type>, then <out-port> specifies
3169 the wire name to be used for the constant signal and no cell driving
3170 that wire is generated.
3172 The following options can be useful when the generated file is not going to be
3173 read by a BLIF parser but a custom tool. It is recommended to not name the output
3174 file *.blif when any of this options is used.
3177 do not translate Yosys's internal gates to generic BLIF logic
3178 functions. Instead create .subckt or .gate lines for all cells.
3181 print .gate instead of .subckt lines for all cells that are not
3182 instantiations of other modules from this design.
3185 do not generate buffers for connected wires. instead use the
3186 non-standard .conn statement.
3189 use the non-standard .attr statement to write cell attributes
3192 use the non-standard .param statement to write cell parameters
3195 write blackbox cells with .blackbox statement.
3198 do not write definitions for the $true, $false and $undef wires.
3201 \section{write\_btor -- write design to BTOR file}
3202 \label{cmd:write_btor}
3203 \begin{lstlisting}[numbers=left,frame=single]
3204 write_btor [filename]
3206 Write the current design to an BTOR file.
3209 \section{write\_edif -- write design to EDIF netlist file}
3210 \label{cmd:write_edif}
3211 \begin{lstlisting}[numbers=left,frame=single]
3212 write_edif [options] [filename]
3214 Write the current design to an EDIF netlist file.
3217 set the specified module as design top module
3219 Unfortunately there are different "flavors" of the EDIF file format. This
3220 command generates EDIF files for the Xilinx place&route tools. It might be
3221 necessary to make small modifications to this command when a different tool
3225 \section{write\_file -- write a text to a file}
3226 \label{cmd:write_file}
3227 \begin{lstlisting}[numbers=left,frame=single]
3228 write_file [options] output_file [input_file]
3230 Write the text from the input file to the output file.
3233 Append to output file (instead of overwriting)
3236 Inside a script the input file can also can a here-document:
3238 write_file hello.txt <<EOT
3243 \section{write\_ilang -- write design to ilang file}
3244 \label{cmd:write_ilang}
3245 \begin{lstlisting}[numbers=left,frame=single]
3246 write_ilang [filename]
3248 Write the current design to an 'ilang' file. (ilang is a text representation
3249 of a design in yosys's internal format.)
3252 only write selected parts of the design.
3255 \section{write\_intersynth -- write design to InterSynth netlist file}
3256 \label{cmd:write_intersynth}
3257 \begin{lstlisting}[numbers=left,frame=single]
3258 write_intersynth [options] [filename]
3260 Write the current design to an 'intersynth' netlist file. InterSynth is
3261 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
3264 do not generate celltypes and conntypes commands. i.e. just output
3265 the netlists. this is used for postsilicon synthesis.
3267 -lib <verilog_or_ilang_file>
3268 Use the specified library file for determining whether cell ports are
3269 inputs or outputs. This option can be used multiple times to specify
3270 more than one library.
3273 only write selected modules. modules must be selected entirely or
3276 http://www.clifford.at/intersynth/
3279 \section{write\_json -- write design to a JSON file}
3280 \label{cmd:write_json}
3281 \begin{lstlisting}[numbers=left,frame=single]
3282 write_json [options] [filename]
3284 Write a JSON netlist of the current design.
3287 include AIG models for the different gate types
3290 The general syntax of the JSON output created by this command is as follows:
3296 <port_name>: <port_details>,
3300 <cell_name>: <cell_details>,
3304 <net_name>: <net_details>,
3314 Where <port_details> is:
3317 "direction": <"input" | "output" | "inout">,
3318 "bits": <bit_vector>
3321 And <cell_details> is:
3324 "hide_name": <1 | 0>,
3325 "type": <cell_type>,
3327 <parameter_name>: <parameter_value>,
3331 <attribute_name>: <attribute_value>,
3334 "port_directions": {
3335 <port_name>: <"input" | "output" | "inout">,
3339 <port_name>: <bit_vector>,
3344 And <net_details> is:
3347 "hide_name": <1 | 0>,
3348 "bits": <bit_vector>
3351 The "hide_name" fields are set to 1 when the name of this cell or net is
3352 automatically created and is likely not of interest for a regular user.
3354 The "port_directions" section is only included for cells for which the
3357 Module and cell ports and nets can be single bit wide or vectors of multiple
3358 bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
3359 values referenced above are vectors of this integers. Signal bits that are
3360 connected to a constant driver are denoted as string "0" or "1" instead of
3363 For example the following Verilog code:
3365 module test(input x, y);
3366 (* keep *) foo #(.P(
42), .Q(
1337))
3367 foo_inst (.A(
{x, y
}), .B(
{y, x
}), .C(
{4'd10,
{4{x
}}}));
3370 Translates to the following JSON output:
3377 "direction": "input",
3381 "direction": "input",
3398 "C":
[ 2,
2,
2,
2, "
0", "
1", "
0", "
1"
],
3424 The models are given as And-Inverter-Graphs (AIGs) in the following form:
3428 /*
0 */
[ <node-spec>
],
3429 /*
1 */
[ <node-spec>
],
3430 /*
2 */
[ <node-spec>
],
3436 The following node-types may be used:
3438 [ "port", <portname>, <bitindex>, <out-list>
]
3439 - the value of the specified input port bit
3441 [ "nport", <portname>, <bitindex>, <out-list>
]
3442 - the inverted value of the specified input port bit
3444 [ "and", <node-index>, <node-index>, <out-list>
]
3445 - the ANDed value of the speciefied nodes
3447 [ "nand", <node-index>, <node-index>, <out-list>
]
3448 - the inverted ANDed value of the speciefied nodes
3450 [ "true", <out-list>
]
3451 - the constant value
1
3453 [ "false", <out-list>
]
3454 - the constant value
0
3456 All nodes appear in topological order. I.e. only nodes with smaller indices
3457 are referenced by "and" and "nand" nodes.
3459 The optional <out-list> at the end of a node specification is a list of
3460 output portname and bitindex pairs, specifying the outputs driven by this node.
3462 For example, the following is the model for a
3-input
3-output $reduce_and cell
3463 inferred by the following code:
3465 module test(input
[2:
0] in, output
[2:
0] out);
3469 "$reduce_and:
3U:
3":
[
3470 /*
0 */
[ "port", "A",
0 ],
3471 /*
1 */
[ "port", "A",
1 ],
3472 /*
2 */
[ "and",
0,
1 ],
3473 /*
3 */
[ "port", "A",
2 ],
3474 /*
4 */
[ "and",
2,
3, "Y",
0 ],
3475 /*
5 */
[ "false", "Y",
1, "Y",
2 ]
3478 Future version of Yosys might add support for additional fields in the JSON
3479 format. A program processing this format must ignore all unkown fields.
3482 \section{write
\_smt2 -- write design to SMT-LIBv2 file
}
3483 \label{cmd:write_smt2
}
3484 \begin{lstlisting
}[numbers=left,frame=single
]
3485 write_smt2
[options
] [filename
]
3487 Write a SMT-LIBv2
[1] description of the current design. For a module with name
3488 '<mod>' this will declare the sort '<mod>_s' (state of the module) and the
3489 functions operating on that state.
3491 The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions
3492 are provided that can be used to access the values of the signals in the module.
3493 Only ports, and signals with the 'keep' attribute set are made available via
3494 such functions. Without the -bv option, multi-bit wires are exported as
3495 separate functions of type Bool for the individual bits. With the -bv option
3496 multi-bit wires are exported as single functions of type BitVec.
3498 The '<mod>_t' function evaluates to 'true' when the given pair of states
3499 describes a valid state transition.
3501 The '<mod>_a' function evaluates to 'true' when the given state satisfies
3502 the asserts in the module.
3504 The '<mod>_u' function evaluates to 'true' when the given state satisfies
3505 the assumptions in the module.
3507 The '<mod>_i' function evaluates to 'true' when the given state conforms
3508 to the initial state.
3511 this will print the recursive walk used to export the modules.
3514 enable support for BitVec (FixedSizeBitVectors theory). with this
3515 option set multi-bit wires are represented using the BitVec sort and
3516 support for coarse grain cells (incl. arithmetic) is enabled.
3519 enable support for memories (via ArraysEx theory). this option
3520 also implies -bv. only $mem cells without merged registers in
3521 read ports are supported. call "memory" with -nordff to make sure
3522 that no registers are merged into $mem read ports. '<mod>_m' functions
3523 will be generated for accessing the arrays that are used to represent
3527 also create '<mod>_n' functions for all registers.
3529 -tpl <template_file>
3530 use the given template file. the line containing only the token '
%%'
3531 is replaced with the regular output of this command.
3533 [1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
3534 R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
3536 ---------------------------------------------------------------------------
3540 Consider the following module (test.v). We want to prove that the output can
3541 never transition from a non-zero value to a zero value.
3543 module test(input clk, output reg
[3:
0] y);
3544 always @(posedge clk)
3548 For this proof we create the following template (test.tpl).
3550 ; we need QF_UFBV for this poof
3553 ; insert the auto-generated code here
3556 ; declare two state variables s1 and s2
3557 (declare-fun s1 () test_s)
3558 (declare-fun s2 () test_s)
3560 ; state s2 is the successor of state s1
3561 (assert (test_t s1 s2))
3563 ; we are looking for a model with y non-zero in s1
3564 (assert (distinct (|test_n y| s1) #b0000))
3566 ; we are looking for a model with y zero in s2
3567 (assert (= (|test_n y| s2) #b0000))
3569 ; is there such a model?
3572 The following yosys script will create a 'test.smt2' file for our proof:
3575 hierarchy -check; proc; opt; check -assert
3576 write_smt2 -bv -tpl test.tpl test.smt2
3578 Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
3579 from non-zero to zero in the test design.
3582 \section{write
\_smv -- write design to SMV file
}
3583 \label{cmd:write_smv
}
3584 \begin{lstlisting
}[numbers=left,frame=single
]
3585 write_smv
[options
] [filename
]
3587 Write an SMV description of the current design.
3590 this will print the recursive walk used to export the modules.
3592 -tpl <template_file>
3593 use the given template file. the line containing only the token '
%%'
3594 is replaced with the regular output of this command.
3596 THIS COMMAND IS UNDER CONSTRUCTION
3599 \section{write
\_spice -- write design to SPICE netlist file
}
3600 \label{cmd:write_spice
}
3601 \begin{lstlisting
}[numbers=left,frame=single
]
3602 write_spice
[options
] [filename
]
3604 Write the current design to an SPICE netlist file.
3607 generate multi-bit ports in MSB first order
3608 (default is LSB first)
3611 set the net name for constant
0 (default: Vss)
3614 set the net name for constant
1 (default: Vdd)
3617 prefix for not-connected nets (default: _NC)
3620 set the specified module as design top module
3623 \section{write
\_verilog -- write design to Verilog file
}
3624 \label{cmd:write_verilog
}
3625 \begin{lstlisting
}[numbers=left,frame=single
]
3626 write_verilog
[options
] [filename
]
3628 Write the current design to a Verilog file.
3631 without this option all internal object names (the ones with a dollar
3632 instead of a backslash prefix) are changed to short names in the
3633 format '_<number>_'.
3636 with this option no attributes are included in the output
3639 with this option attributes are included as comments in the output
3642 without this option all internal cells are converted to Verilog
3646 usually modules with the 'blackbox' attribute are ignored. with
3647 this option set only the modules with the 'blackbox' attribute
3648 are written to the output file.
3651 only write selected modules. modules must be selected entirely or