1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command name instead of "yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interpreted as the command string to be passed to ABC. The
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
}
28 for -liberty with -constr:
29 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
};
30 buffer; upsize
{D
}; dnsize
{D
}; stime -p
33 strash; scorr; ifraig; retime; strash; dch -f; if
36 strash; scorr; ifraig; retime; strash; dch -f; map
39 use different default scripts that are slightly faster (at the cost
42 for -liberty without -constr:
45 for -liberty with -constr:
46 retime
{D
}; map
{D
}; buffer; upsize
{D
}; dnsize
{D
}; stime -p
55 generate netlists for the specified cell library (using the liberty
59 pass this file with timing constraints to ABC. use with -liberty.
61 a constr file contains two lines:
62 set_driving_cell <cell_name>
63 set_load <floating_point_number>
65 the set_driving_cell statement defines which cell type is assumed to
66 drive the primary inputs and the set_load statement sets the load in
67 femtofarads for each primary output.
70 set delay target. the string
{D
} in the default scripts above is
71 replaced by this option when used, and an empty string otherwise.
74 generate netlist using luts of (max) the specified width.
77 generate netlist using luts of (max) the specified width <w2>. All
78 luts with width <= <w1> have constant cost. for luts larger than <w1>
79 the area cost doubles with each additional input bit. the delay cost
80 is still constant for all lut widths.
82 -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
83 generate netlist using luts. Use the specified costs for luts with
1,
87 Map the the specified list of gate types. Supported gates types are:
88 AND, NAND, OR, NOR, XOR, XNOR, MUX, AOI3, OAI3, AOI4, OAI4.
89 (The NOT gate is always added to this list automatically.)
92 also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
93 clock domains are automatically partitioned in clock domains and each
94 domain is passed through ABC independently.
96 -clk
[!
]<clock-signal-name>
[,
[!
]<enable-signal-name>
]
97 use only the specified clock domain. this is like -dff, but only FF
98 cells that belong to the specified clock domain are used.
101 set the "keep" attribute on flip-flop output wires. (and thus preserve
102 them, for example for equivalence checking.)
105 when this option is used, the temporary files created by this pass
106 are not removed. this is useful for debugging.
109 print the temp dir name in log. usually this is suppressed so that the
110 command output is identical across runs.
113 set a 'abcgroup' attribute on all objects created by ABC. The value of
114 this attribute is a unique integer for each ABC process started. This
115 is useful for debugging the partitioning of clock domains.
117 When neither -liberty nor -lut is used, the Yosys standard cell library is
118 loaded into ABC before the ABC script is executed.
120 This pass does not operate on modules with unprocessed processes in it.
121 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
123 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
126 \section{add -- add objects to the design
}
128 \begin{lstlisting
}[numbers=left,frame=single
]
129 add <command>
[selection
]
131 This command adds objects to the design. It operates on all fully selected
132 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
135 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
137 Add a wire (input, inout, output port) with the given name and width. The
138 command will fail if the object exists already and has different properties
139 than the object to be created.
142 add -global_input <name> <width>
[selection
]
144 Like 'add -input', but also connect the signal between instances of the
148 \section{aigmap -- map logic to and-inverter-graph circuit
}
150 \begin{lstlisting
}[numbers=left,frame=single
]
151 aigmap
[options
] [selection
]
153 Replace all logic cells with circuits made of only $_AND_ and
157 Enable creation of $_NAND_ cells
160 \section{alumacc -- extract ALU and MACC cells
}
162 \begin{lstlisting
}[numbers=left,frame=single
]
165 This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
169 \section{cd -- a shortcut for 'select -module <name>'
}
171 \begin{lstlisting
}[numbers=left,frame=single
]
174 This is just a shortcut for 'select -module <modname>'.
179 When no module with the specified name is found, but there is a cell
180 with the specified name in the current module, then this is equivalent
185 This is just a shortcut for 'select -clear'.
188 \section{check -- check for obvious problems in the design
}
190 \begin{lstlisting
}[numbers=left,frame=single
]
191 check
[options
] [selection
]
193 This pass identifies the following problems in the current design:
195 - combinatorial loops
197 - two or more conflicting drivers for one wire
199 - used wires that do not have a driver
201 When called with -noinit then this command also checks for wires which have
202 the 'init' attribute set.
204 When called with -assert then the command will produce an error if any
205 problems are found in the current design.
208 \section{chparam -- re-evaluate modules with new parameters
}
210 \begin{lstlisting
}[numbers=left,frame=single
]
211 chparam
[ -set name value
]...
[selection
]
213 Re-evaluate the selected modules with new parameters. String values must be
214 passed in double quotes (").
217 chparam -list
[selection
]
219 List the available parameters of the selected modules.
222 \section{clean -- remove unused cells and wires
}
224 \begin{lstlisting
}[numbers=left,frame=single
]
225 clean
[options
] [selection
]
227 This is identical to 'opt_clean', but less verbose.
229 When commands are separated using the ';;' token, this command will be executed
230 between the commands.
232 When commands are separated using the ';;;' token, this command will be executed
233 in -purge mode between the commands.
236 \section{connect -- create or remove connections
}
238 \begin{lstlisting
}[numbers=left,frame=single
]
239 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
241 Create a connection. This is equivalent to adding the statement 'assign
242 <lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
243 drivers for <lhs-expr> are unconnected. This can be overwritten by using
247 connect
[-nomap
] -unset <expr>
249 Unconnect all existing drivers for the specified expression.
252 connect
[-nomap
] -port <cell> <port> <expr>
254 Connect the specified cell port to the specified cell port.
257 Per default signal alias names are resolved and all signal names are mapped
258 the the signal name of the primary driver. Using the -nomap option deactivates
261 The connect command operates in one module only. Either only one module must
262 be selected or an active module must be set using the 'cd' command.
264 This command does not operate on module with processes.
267 \section{connwrappers -- replace undef values with defined constants
}
268 \label{cmd:connwrappers
}
269 \begin{lstlisting
}[numbers=left,frame=single
]
270 connwrappers
[options
] [selection
]
272 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
273 in wrapper cells with a (larger) constant port size. I.e. the upper bits
274 of the wrapper output are signed/unsigned bit extended. This command uses this
275 knowledge to rewire the inputs of the driven cells to match the output of
278 -signed <cell_type> <port_name> <width_param>
279 -unsigned <cell_type> <port_name> <width_param>
280 consider the specified signed/unsigned wrapper output
282 -port <cell_type> <port_name> <width_param> <sign_param>
283 use the specified parameter to decide if signed or unsigned
285 The options -signed, -unsigned, and -port can be specified multiple times.
288 \section{copy -- copy modules in the design
}
290 \begin{lstlisting
}[numbers=left,frame=single
]
291 copy old_name new_name
293 Copy the specified module. Note that selection patterns are not supported
297 \section{cover -- print code coverage counters
}
299 \begin{lstlisting
}[numbers=left,frame=single
]
300 cover
[options
] [pattern
]
302 Print the code coverage counters collected using the cover() macro in the Yosys
303 C++ code. This is useful to figure out what parts of Yosys are utilized by a
307 Do not print output to the normal destination (console and/or log file)
310 Write output to this file, truncate if exists.
313 Write output to this file, append if exists.
316 Write output to a newly created file in the specified directory.
318 When one or more pattern (shell wildcards) are specified, then only counters
319 matching at least one pattern are printed.
322 It is also possible to instruct Yosys to print the coverage counters on program
323 exit to a file using environment variables:
325 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
327 This will create a file (with an auto-generated name) in this
328 directory and write the coverage counters to it.
330 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
332 This will append the coverage counters to the specified file.
335 Hint: Use the following AWK command to consolidate Yosys coverage files:
337 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
338 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
341 Coverage counters are only available in Yosys for Linux.
344 \section{delete -- delete objects in the design
}
346 \begin{lstlisting
}[numbers=left,frame=single
]
349 Deletes the selected objects. This will also remove entire modules, if the
350 whole module is selected.
353 delete
{-input|-output|-port
} [selection
]
355 Does not delete any object but removes the input and/or output flag on the
356 selected wires, thus 'deleting' module ports.
359 \section{design -- save, restore and reset current design
}
361 \begin{lstlisting
}[numbers=left,frame=single
]
364 Clear the current design.
369 Save the current design under the given name.
374 Save the current design under the given name and then clear the current design.
379 Push the current design to the stack and then clear the current design.
384 Reset the current design and pop the last design from the stack.
389 Reset the current design and load the design previously saved under the given
393 design -copy-from <name>
[-as <new_mod_name>
] <selection>
395 Copy modules from the specified design into the current one. The selection is
396 evaluated in the other design.
399 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
401 Copy modules from the current design into the specified one.
404 \section{dff2dffe -- transform \$dff cells to \$dffe cells
}
406 \begin{lstlisting
}[numbers=left,frame=single
]
407 dff2dffe
[options
] [selection
]
409 This pass transforms $dff cells driven by a tree of multiplexers with one or
410 more feedback paths to $dffe cells. It also works on gate-level cells such as
411 $_DFF_P_, $_DFF_N_ and $_MUX_.
414 operate in the opposite direction: replace $dffe cells with combinations
415 of $dff and $mux cells. the options below are ignore in unmap mode.
417 -direct <internal_gate_type> <external_gate_type>
418 map directly to external gate type. <internal_gate_type> can
419 be any internal gate-level FF cell (except $_DFFE_??_). the
420 <external_gate_type> is the cell type name for a cell with an
421 identical interface to the <internal_gate_type>, except it
422 also has an high-active enable port 'E'.
423 Usually <external_gate_type> is an intermediate cell type
424 that is then translated to the final type using 'techmap'.
426 -direct-match <pattern>
427 like -direct for all DFF cell types matching the expression.
428 this will use $__DFFE_* as <external_gate_type> matching the
429 internal gate type $_DFF_*_, except for $_DFF_
[NP
]_, which is
430 converted to $_DFFE_
[NP
]_.
433 \section{dffinit -- set INIT param on FF cells
}
435 \begin{lstlisting
}[numbers=left,frame=single
]
436 dffinit
[options
] [selection
]
438 This pass sets an FF cell parameter to the the initial value of the net it
439 drives. (This is primarily used in FPGA flows.)
441 -ff <cell_name> <output_port> <init_param>
442 operate on the specified cell type. this option can be used
446 \section{dfflibmap -- technology mapping of flip-flops
}
447 \label{cmd:dfflibmap
}
448 \begin{lstlisting
}[numbers=left,frame=single
]
449 dfflibmap
[-prepare
] -liberty <file>
[selection
]
451 Map internal flip-flop cells to the flip-flop cells in the technology
452 library specified in the given liberty file.
454 This pass may add inverters as needed. Therefore it is recommended to
455 first run this pass and then map the logic paths to the target technology.
457 When called with -prepare, this command will convert the internal FF cells
458 to the internal cell types that best match the cells found in the given
462 \section{dffsr2dff -- convert DFFSR cells to simpler FF cell types
}
463 \label{cmd:dffsr2dff
}
464 \begin{lstlisting
}[numbers=left,frame=single
]
465 dffsr2dff
[options
] [selection
]
467 This pass converts DFFSR cells ($dffsr, $_DFFSR_???_) and ADFF cells ($adff,
468 $_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.
471 \section{dump -- print parts of the design in ilang format
}
473 \begin{lstlisting
}[numbers=left,frame=single
]
474 dump
[options
] [selection
]
476 Write the selected parts of the design to the console or specified file in
480 also dump the module headers, even if only parts of a single
484 only dump the module headers if the entire module is selected
487 write to the specified file.
490 like -outfile but append instead of overwrite
493 \section{echo -- turning echoing back of commands on and off
}
495 \begin{lstlisting
}[numbers=left,frame=single
]
498 Print all commands to log before executing them.
503 Do not print all commands to log before executing them. (default)
506 \section{edgetypes -- list all types of edges in selection
}
507 \label{cmd:edgetypes
}
508 \begin{lstlisting
}[numbers=left,frame=single
]
509 edgetypes
[options
] [selection
]
511 This command lists all unique types of 'edges' found in the selection. An 'edge'
512 is a
4-tuple of source and sink cell type and port name.
515 \section{equiv
\_add -- add a \$equiv cell
}
516 \label{cmd:equiv_add
}
517 \begin{lstlisting
}[numbers=left,frame=single
]
518 equiv_add
[-try
] gold_sig gate_sig
520 This command adds an $equiv cell for the specified signals.
523 equiv_add
[-try
] -cell gold_cell gate_cell
525 This command adds $equiv cells for the ports of the specified cells.
528 \section{equiv
\_induct -- proving \$equiv cells using temporal induction
}
529 \label{cmd:equiv_induct
}
530 \begin{lstlisting
}[numbers=left,frame=single
]
531 equiv_induct
[options
] [selection
]
533 Uses a version of temporal induction to prove $equiv cells.
535 Only selected $equiv cells are proven and only selected cells are used to
539 enable modelling of undef states
542 the max. number of time steps to be considered (default =
4)
544 This command is very effective in proving complex sequential circuits, when
545 the internal state of the circuit quickly propagates to $equiv cells.
547 However, this command uses a weak definition of 'equivalence': This command
548 proves that the two circuits will not diverge after they produce equal
549 outputs (observable points via $equiv) for at least <N> cycles (the <N>
552 Combined with simulation this is very powerful because simulation can give
553 you confidence that the circuits start out synced for at least <N> cycles
557 \section{equiv
\_make -- prepare a circuit for equivalence checking
}
558 \label{cmd:equiv_make
}
559 \begin{lstlisting
}[numbers=left,frame=single
]
560 equiv_make
[options
] gold_module gate_module equiv_module
562 This creates a module annotated with $equiv cells from two presumably
563 equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
564 to work with the created equivalent checking module.
567 Also match cells and wires with $... names.
570 Do not match cells or signals that match the names in the file.
573 Match FSM encodings using the description from the file.
574 See 'help fsm_recode' for details.
576 Note: The circuit created by this command is not a miter (with something like
577 a trigger output), but instead uses $equiv cells to encode the equivalence
578 checking problem. Use 'miter -equiv' if you want to create a miter circuit.
581 \section{equiv
\_mark -- mark equivalence checking regions
}
582 \label{cmd:equiv_mark
}
583 \begin{lstlisting
}[numbers=left,frame=single
]
584 equiv_mark
[options
] [selection
]
586 This command marks the regions in an equivalence checking module. Region
0 is
587 the proven part of the circuit. Regions with higher numbers are connected
588 unproven subcricuits. The integer attribute 'equiv_region' is set on all
592 \section{equiv
\_miter -- extract miter from equiv circuit
}
593 \label{cmd:equiv_miter
}
594 \begin{lstlisting
}[numbers=left,frame=single
]
595 equiv_miter
[options
] miter_module
[selection
]
597 This creates a miter module for further analysis of the selected $equiv cells.
600 Create a trigger output
603 Create cmp_* outputs for individual unproven $equiv cells
606 Create a $assert cell for each unproven $equiv cell
609 Create compare logic that handles undefs correctly
612 \section{equiv
\_purge -- purge equivalence checking module
}
613 \label{cmd:equiv_purge
}
614 \begin{lstlisting
}[numbers=left,frame=single
]
615 equiv_purge
[options
] [selection
]
617 This command removes the proven part of an equivalence checking module, leaving
618 only the unproven segments in the design. This will also remove and add module
622 \section{equiv
\_remove -- remove \$equiv cells
}
623 \label{cmd:equiv_remove
}
624 \begin{lstlisting
}[numbers=left,frame=single
]
625 equiv_remove
[options
] [selection
]
627 This command removes the selected $equiv cells. If neither -gold nor -gate is
628 used then only proven cells are removed.
637 \section{equiv
\_simple -- try proving simple \$equiv instances
}
638 \label{cmd:equiv_simple
}
639 \begin{lstlisting
}[numbers=left,frame=single
]
640 equiv_simple
[options
] [selection
]
642 This command tries to prove $equiv cells using a simple direct SAT approach.
648 enable modelling of undef states
651 disabling grouping of $equiv cells by output wire
654 the max. number of time steps to be considered (default =
1)
657 \section{equiv
\_status -- print status of equivalent checking module
}
658 \label{cmd:equiv_status
}
659 \begin{lstlisting
}[numbers=left,frame=single
]
660 equiv_status
[options
] [selection
]
662 This command prints status information for all selected $equiv cells.
665 produce an error if any unproven $equiv cell is found
668 \section{equiv
\_struct -- structural equivalence checking
}
669 \label{cmd:equiv_struct
}
670 \begin{lstlisting
}[numbers=left,frame=single
]
671 equiv_struct
[options
] [selection
]
673 This command adds additional $equiv cells based on the assumption that the
674 gold and gate circuit are structurally equivalent. Note that this can introduce
675 bad $equiv cells in cases where the netlists are not structurally equivalent,
676 for example when analyzing circuits with cells with commutative inputs. This
677 command will also de-duplicate gates.
680 by default this command performans forward sweeps until nothing can
681 be merged by forwards sweeps, then backward sweeps until forward
682 sweeps are effective again. with this option set only forward sweeps
686 add the specified cell type to the list of cell types that are only
687 merged in forward sweeps and never in backward sweeps. $equiv is in
688 this list automatically.
691 by default, the internal RTL and gate cell types are ignored. add
692 this option to also process those cell types with this command.
695 maximum number of iterations to run before aborting
698 \section{eval -- evaluate the circuit given an input
}
700 \begin{lstlisting
}[numbers=left,frame=single
]
701 eval
[options
] [selection
]
703 This command evaluates the value of a signal given the value of all required
706 -set <signal> <value>
707 set the specified signal to the specified value.
710 set all unspecified source signals to undef (x)
713 create a truth table using the specified input signals
716 show the value for the specified signal. if no -show option is passed
717 then all output ports of the current module are used.
720 \section{expose -- convert internal signals to module ports
}
722 \begin{lstlisting
}[numbers=left,frame=single
]
723 expose
[options
] [selection
]
725 This command exposes all selected internal signals of a module as additional
729 only consider wires that are directly driven by register cell.
732 when exposing a wire, create an input/output pair and cut the internal
733 signal path at that wire.
736 only expose those signals that are shared among the selected modules.
737 this is useful for preparing modules for equivalence checking.
740 also turn connections to instances of other modules to additional
741 inputs and outputs and remove the module instances.
744 turn flip-flops to sets of inputs and outputs.
747 when creating new wire/port names, the original object name is suffixed
748 with this separator (default: '.') and the port name or a type
749 designator for the exposed signal.
752 \section{extract -- find subcircuits and replace them with cells
}
754 \begin{lstlisting
}[numbers=left,frame=single
]
755 extract -map <map_file>
[options
] [selection
]
756 extract -mine <out_file>
[options
] [selection
]
758 This pass looks for subcircuits that are isomorphic to any of the modules
759 in the given map file and replaces them with instances of this modules. The
760 map file can be a Verilog source file
(*.v) or an ilang file (*.il).
763 use the modules in this file as reference. This option can be used
767 use the modules in this in-memory design as reference. This option can
768 be used multiple times.
771 print debug output while analyzing
774 also find instances with constant drivers. this may be much
775 slower than the normal operation.
778 normally builtin port swapping rules for internal cells are used per
779 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
780 when this option is used.
782 -compat <needle_type> <haystack_type>
783 Per default, the cells in the map file (needle) must have the
784 type as the cells in the active design (haystack). This option
785 can be used to register additional pairs of types that should
786 match. This option can be used multiple times.
788 -swap <needle_type> <port1>,<port2>[,...]
789 Register a set of swappable ports for a needle cell type.
790 This option can be used multiple times.
792 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
793 Register a valid permutation of swappable ports for a needle
794 cell type. This option can be used multiple times.
796 -cell_attr <attribute_name>
797 Attributes on cells with the given name must match.
799 -wire_attr <attribute_name>
800 Attributes on wires with the given name must match.
803 Do not use parameters when matching cells.
805 -ignore_param <cell_type> <parameter_name>
806 Do not use this parameter when matching cells.
808 This pass does not operate on modules with unprocessed processes in it.
809 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
811 This pass can also be used for mining for frequent subcircuits. In this mode
812 the following options are to be used instead of the -map option.
815 mine for frequent subcircuits and write them to the given ilang file
817 -mine_cells_span <min> <max>
818 only mine for subcircuits with the specified number of cells
822 only mine for subcircuits with at least the specified number of matches
825 -mine_limit_matches_per_module <num>
826 when calculating the number of matches for a subcircuit, don't count
827 more than the specified number of matches per module
829 -mine_max_fanout <num>
830 don't consider internal signals with more than <num> connections
832 The modules in the map file may have the attribute 'extract_order' set to an
833 integer value. Then this value is used to determine the order in which the pass
834 tries to map the modules to the design (ascending, default value is 0).
836 See 'help techmap' for a pass that does the opposite thing.
839 \section{flatten -- flatten design}
841 \begin{lstlisting}[numbers=left,frame=single]
844 This pass flattens the design by replacing cells by their implementation. This
845 pass is very similar to the 'techmap' pass. The only difference is that this
846 pass is using the current design as mapping library.
848 Cells and/or modules with the 'keep_hierarchy' attribute set will not be
849 flattened by this command.
852 \section{freduce -- perform functional reduction}
854 \begin{lstlisting}[numbers=left,frame=single]
855 freduce [options] [selection]
857 This pass performs functional reduction in the circuit. I.e. if two nodes are
858 equivalent, they are merged to one node and one of the redundant drivers is
859 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
862 enable verbose or very verbose output
865 enable explicit handling of inverted signals
868 stop after <n> reduction operations. this is mostly used for
869 debugging the freduce command itself.
872 dump the design to <prefix>_<module>_<num>.il after each reduction
873 operation. this is mostly used for debugging the freduce command.
875 This pass is undef-aware, i.e. it considers don't-care values for detecting
878 All selected wires are considered for rewiring. The selected cells cover the
879 circuit that is analyzed.
882 \section{fsm -- extract and optimize finite state machines}
884 \begin{lstlisting}[numbers=left,frame=single]
885 fsm [options] [selection]
887 This pass calls all the other fsm_* passes in a useful order. This performs
888 FSM extraction and optimization. It also calls opt_clean as needed:
890 fsm_detect unless got option -nodetect
897 fsm_expand if got option -expand
898 opt_clean if got option -expand
899 fsm_opt if got option -expand
901 fsm_recode unless got option -norecode
905 fsm_export if got option -export
906 fsm_map unless got option -nomap
910 -expand, -norecode, -export, -nomap
911 enable or disable passes as indicated above
914 -fm_set_fsm_file file
916 passed through to fsm_recode pass
919 \section{fsm\_detect -- finding FSMs in design}
920 \label{cmd:fsm_detect}
921 \begin{lstlisting}[numbers=left,frame=single]
922 fsm_detect [selection]
924 This pass detects finite state machines by identifying the state signal.
925 The state signal is then marked by setting the attribute 'fsm_encoding'
926 on the state signal to "auto".
928 Existing 'fsm_encoding' attributes are not changed by this pass.
930 Signals can be protected from being detected by this pass by setting the
931 'fsm_encoding' attribute to "none".
934 \section{fsm\_expand -- expand FSM cells by merging logic into it}
935 \label{cmd:fsm_expand}
936 \begin{lstlisting}[numbers=left,frame=single]
937 fsm_expand [selection]
939 The fsm_extract pass is conservative about the cells that belong to a finite
940 state machine. This pass can be used to merge additional auxiliary gates into
941 the finite state machine.
944 \section{fsm\_export -- exporting FSMs to KISS2 files}
945 \label{cmd:fsm_export}
946 \begin{lstlisting}[numbers=left,frame=single]
947 fsm_export [-noauto] [-o filename] [-origenc] [selection]
949 This pass creates a KISS2 file for every selected FSM. For FSMs with the
950 'fsm_export' attribute set, the attribute value is used as filename, otherwise
951 the module and cell name is used as filename. If the parameter '-o' is given,
952 the first exported FSM is written to the specified filename. This overwrites
953 the setting as specified with the 'fsm_export' attribute. All other FSMs are
954 exported to the default name as mentioned above.
957 only export FSMs that have the 'fsm_export' attribute set
960 filename of the first exported FSM
963 use binary state encoding as state names instead of s0, s1, ...
966 \section{fsm\_extract -- extracting FSMs in design}
967 \label{cmd:fsm_extract}
968 \begin{lstlisting}[numbers=left,frame=single]
969 fsm_extract [selection]
971 This pass operates on all signals marked as FSM state signals using the
972 'fsm_encoding' attribute. It consumes the logic that creates the state signal
973 and uses the state signal to generate control signal and replaces it with an
976 The generated FSM cell still generates the original state signal with its
977 original encoding. The 'fsm_opt' pass can be used in combination with the
978 'opt_clean' pass to eliminate this signal.
981 \section{fsm\_info -- print information on finite state machines}
983 \begin{lstlisting}[numbers=left,frame=single]
986 This pass dumps all internal information on FSM cells. It can be useful for
987 analyzing the synthesis process and is called automatically by the 'fsm'
988 pass so that this information is included in the synthesis log file.
991 \section{fsm\_map -- mapping FSMs to basic logic}
993 \begin{lstlisting}[numbers=left,frame=single]
996 This pass translates FSM cells to flip-flops and logic.
999 \section{fsm\_opt -- optimize finite state machines}
1001 \begin{lstlisting}[numbers=left,frame=single]
1004 This pass optimizes FSM cells. It detects which output signals are actually
1005 not used and removes them from the FSM. This pass is usually used in
1006 combination with the 'opt_clean' pass (see also 'help fsm').
1009 \section{fsm\_recode -- recoding finite state machines}
1010 \label{cmd:fsm_recode}
1011 \begin{lstlisting}[numbers=left,frame=single]
1012 fsm_recode [options] [selection]
1014 This pass reassign the state encodings for FSM cells. At the moment only
1015 one-hot encoding and binary encoding is supported.
1017 specify the encoding scheme used for FSMs without the
1018 'fsm_encoding' attribute or with the attribute set to `auto'.
1020 -fm_set_fsm_file <file>
1021 generate a file containing the mapping from old to new FSM encoding
1022 in form of Synopsys Formality set_fsm_* commands.
1025 write the mappings from old to new FSM encoding to a file in the
1028 .fsm <module_name> <state_signal>
1029 .map <old_bitpattern> <new_bitpattern>
1032 \section{help -- display help messages}
1034 \begin{lstlisting}[numbers=left,frame=single]
1035 help ................ list all commands
1036 help <command> ...... print help message for given command
1037 help -all ........... print complete command reference
1039 help -cells .......... list all cell types
1040 help <celltype> ..... print help message for given cell type
1041 help <celltype>+ .... print verilog code for given cell type
1044 \section{hierarchy -- check, expand and clean up design hierarchy}
1045 \label{cmd:hierarchy}
1046 \begin{lstlisting}[numbers=left,frame=single]
1047 hierarchy [-check] [-top <module>]
1048 hierarchy -generate <cell-types> <port-decls>
1050 In parametric designs, a module might exists in several variations with
1051 different parameter values. This pass looks at all modules in the current
1052 design an re-runs the language frontends for the parametric modules as
1056 also check the design hierarchy. this generates an error when
1057 an unknown module is used as cell type.
1060 by default the hierarchy command will not remove library (blackbox)
1061 modules. use this option to also remove unused blackbox modules.
1064 search for files named <module_name>.v in the specified directory
1065 for unknown modules and automatically run read_verilog for each
1069 per default this pass also converts positional arguments in cells
1070 to arguments using port names. this option disables this behavior.
1073 per default this pass sets the "keep" attribute on all modules
1074 that directly or indirectly contain one or more $assert cells. this
1075 option disables this behavior.
1078 use the specified top module to built a design hierarchy. modules
1079 outside this tree (unused modules) are removed.
1081 when the -top option is used, the 'top' attribute will be set on the
1082 specified top module. otherwise a module with the 'top' attribute set
1083 will implicitly be used as top module, if such a module exists.
1086 automatically determine the top of the design hierarchy and mark it.
1088 In -generate mode this pass generates blackbox modules for the given cell
1089 types (wildcards supported). For this the design is searched for cells that
1090 match the given types and then the given port declarations are used to
1091 determine the direction of the ports. The syntax for a port declaration is:
1093 {i|o|io}[@<num>]:<portname>
1095 Input ports are specified with the 'i' prefix, output ports with the 'o'
1096 prefix and inout ports with the 'io' prefix. The optional <num> specifies
1097 the position of the port in the parameter list (needed when instantiated
1098 using positional arguments). When <num> is not specified, the <portname> can
1099 also contain wildcard characters.
1101 This pass ignores the current selection and always operates on all modules
1102 in the current design.
1105 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers}
1107 \begin{lstlisting}[numbers=left,frame=single]
1108 hilomap [options] [selection]
1110 Map constants to 'tielo' and 'tiehi' driver cells.
1112 -hicell <celltype> <portname>
1113 Replace constant hi bits with this cell.
1115 -locell <celltype> <portname>
1116 Replace constant lo bits with this cell.
1119 Create only one hi/lo cell and connect all constant bits
1120 to that cell. Per default a separate cell is created for
1124 \section{history -- show last interactive commands}
1126 \begin{lstlisting}[numbers=left,frame=single]
1129 This command prints all commands in the shell history buffer. This are
1130 all commands executed in an interactive session, but not the commands
1131 from executed scripts.
1134 \section{ice40\_ffinit -- iCE40: handle FF init values}
1135 \label{cmd:ice40_ffinit}
1136 \begin{lstlisting}[numbers=left,frame=single]
1137 ice40_ffinit [options] [selection]
1139 Remove zero init values for FF output signals. Add inverters to implement
1140 nonzero init values.
1143 \section{ice40\_ffssr -- iCE40: merge synchronous set/reset into FF cells}
1144 \label{cmd:ice40_ffssr}
1145 \begin{lstlisting}[numbers=left,frame=single]
1146 ice40_ffssr [options] [selection]
1148 Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.
1151 \section{ice40\_opt -- iCE40: perform simple optimizations}
1152 \label{cmd:ice40_opt}
1153 \begin{lstlisting}[numbers=left,frame=single]
1154 ice40_opt [options] [selection]
1156 This command executes the following script:
1159 <ice40 specific optimizations>
1160 opt_const -mux_undef -undriven [-full]
1164 while <changed design>
1167 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
1168 \label{cmd:iopadmap}
1169 \begin{lstlisting}[numbers=left,frame=single]
1170 iopadmap [options] [selection]
1172 Map module inputs/outputs to PAD cells from a library. This pass
1173 can only map to very simple PAD cells. Use 'techmap' to further map
1174 the resulting cells to more sophisticated PAD cells.
1176 -inpad <celltype> <portname>[:<portname>]
1177 Map module input ports to the given cell type with the
1178 given output port name. if a 2nd portname is given, the
1179 signal is passed through the pad call, using the 2nd
1182 -outpad <celltype> <portname>[:<portname>]
1183 -inoutpad <celltype> <portname>[:<portname>]
1184 Similar to -inpad, but for output and inout ports.
1186 -widthparam <param_name>
1187 Use the specified parameter name to set the port width.
1189 -nameparam <param_name>
1190 Use the specified parameter to set the port name.
1193 create individual bit-wide buffers even for ports that
1194 are wider. (the default behavior is to create word-wide
1195 buffers using -widthparam to set the word size on the cell.)
1198 \section{json -- write design in JSON format}
1200 \begin{lstlisting}[numbers=left,frame=single]
1201 json [options] [selection]
1203 Write a JSON netlist of all selected objects.
1206 write to the specified file.
1209 also include AIG models for the different gate types
1211 See 'help write_json' for a description of the JSON format used.
1214 \section{log -- print text and log files}
1216 \begin{lstlisting}[numbers=left,frame=single]
1219 Print the given string to the screen and/or the log file. This is useful for TCL
1220 scripts, because the TCL command "puts" only goes to stdout but not to
1224 Print the output to stdout too. This is useful when all Yosys is executed
1225 with a script and the -q (quiet operation) argument to notify the user.
1228 Print the output to stderr too.
1231 Don't use the internal log() command. Use either -stdout or -stderr,
1232 otherwise no output will be generated at all.
1235 do not append a newline
1238 \section{ls -- list modules or objects in modules}
1240 \begin{lstlisting}[numbers=left,frame=single]
1243 When no active module is selected, this prints a list of modules.
1245 When an active module is selected, this prints a list of objects in the module.
1248 \section{lut2mux -- convert \$lut to \$\_MUX\_}
1250 \begin{lstlisting}[numbers=left,frame=single]
1251 lut2mux [options] [selection]
1253 This pass converts $lut cells to $_MUX_ gates.
1256 \section{maccmap -- mapping macc cells}
1258 \begin{lstlisting}[numbers=left,frame=single]
1259 maccmap [-unmap] [selection]
1261 This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
1262 is used then the $macc cell is mapped to $add, $sub, etc. cells instead.
1265 \section{memory -- translate memories to basic cells}
1267 \begin{lstlisting}[numbers=left,frame=single]
1268 memory [-nomap] [-nordff] [-bram <bram_rules>] [selection]
1270 This pass calls all the other memory_* passes in a useful order:
1272 memory_dff [-nordff]
1277 memory_bram -rules <bram_rules> (when called with -bram)
1278 memory_map (skipped if called with -nomap)
1280 This converts memories to word-wide DFFs and address decoders
1281 or multiport memory blocks if called with the -nomap option.
1284 \section{memory\_bram -- map memories to block rams}
1285 \label{cmd:memory_bram}
1286 \begin{lstlisting}[numbers=left,frame=single]
1287 memory_bram -rules <rule_file> [selection]
1289 This pass converts the multi-port $mem memory cells into block ram instances.
1290 The given rules file describes the available resources and how they should be
1293 The rules file contains a set of block ram description and a sequence of match
1294 rules. A block ram description looks like this:
1296 bram RAMB1024X32 # name of BRAM cell
1297 init 1 # set to '1' if BRAM can be initialized
1298 abits 10 # number of address bits
1299 dbits 32 # number of data bits
1300 groups 2 # number of port groups
1301 ports 1 1 # number of ports in each group
1302 wrmode 1 0 # set to '1' if this groups is write ports
1303 enable 4 1 # number of enable bits
1304 transp 0 2 # transparent (for read ports)
1305 clocks 1 2 # clock configuration
1306 clkpol 2 2 # clock polarity configuration
1309 For the option 'transp' the value 0 means non-transparent, 1 means transparent
1310 and a value greater than 1 means configurable. All groups with the same
1311 value greater than 1 share the same configuration bit.
1313 For the option 'clocks' the value 0 means non-clocked, and a value greater
1314 than 0 means clocked. All groups with the same value share the same clock
1317 For the option 'clkpol' the value 0 means negative edge, 1 means positive edge
1318 and a value greater than 1 means configurable. All groups with the same value
1319 greater than 1 share the same configuration bit.
1321 Using the same bram name in different bram blocks will create different variants
1322 of the bram. Verilog configuration parameters for the bram are created as needed.
1324 It is also possible to create variants by repeating statements in the bram block
1325 and appending '@<label>' to the individual statements.
1327 A match rule looks like this:
1330 max waste 16384 # only use this bram if <= 16k ram bits are unused
1331 min efficiency 80 # only use this bram if efficiency is at least 80%
1334 It is possible to match against the following values with min/max rules:
1336 words ........ number of words in memory in design
1337 abits ........ number of address bits on memory in design
1338 dbits ........ number of data bits on memory in design
1339 wports ....... number of write ports on memory in design
1340 rports ....... number of read ports on memory in design
1341 ports ........ number of ports on memory in design
1342 bits ......... number of bits in memory in design
1343 dups .......... number of duplications for more read ports
1345 awaste ....... number of unused address slots for this match
1346 dwaste ....... number of unused data bits for this match
1347 bwaste ....... number of unused bram bits for this match
1348 waste ........ total number of unused bram bits (bwaste*dups)
1349 efficiency ... total percentage of used and non-duplicated bits
1351 acells ....... number of cells in 'address-direction'
1352 dcells ....... number of cells in 'data-direction'
1353 cells ........ total number of cells (acells*dcells*dups)
1355 The interface for the created bram instances is derived from the bram
1356 description. Use 'techmap' to convert the created bram instances into
1357 instances of the actual bram cells of your target architecture.
1359 A match containing the command 'or_next_if_better' is only used if it
1360 has a higher efficiency than the next match (and the one after that if
1361 the next also has 'or_next_if_better' set, and so forth).
1363 A match containing the command 'make_transp' will add external circuitry
1364 to simulate 'transparent read', if necessary.
1366 A match containing the command 'make_outreg' will add external flip-flops
1367 to implement synchronous read ports, if necessary.
1369 A match containing the command 'shuffle_enable A' will re-organize
1370 the data bits to accommodate the enable pattern of port A.
1373 \section{memory\_collect -- creating multi-port memory cells}
1374 \label{cmd:memory_collect}
1375 \begin{lstlisting}[numbers=left,frame=single]
1376 memory_collect [selection]
1378 This pass collects memories and memory ports and creates generic multiport
1382 \section{memory\_dff -- merge input/output DFFs into memories}
1383 \label{cmd:memory_dff}
1384 \begin{lstlisting}[numbers=left,frame=single]
1385 memory_dff [options] [selection]
1387 This pass detects DFFs at memory ports and merges them into the memory port.
1388 I.e. it consumes an asynchronous memory port and the flip-flops at its
1389 interface and yields a synchronous memory port.
1392 do not merge registers on read ports
1395 \section{memory\_map -- translate multiport memories to basic cells}
1396 \label{cmd:memory_map}
1397 \begin{lstlisting}[numbers=left,frame=single]
1398 memory_map [selection]
1400 This pass converts multiport memory cells as generated by the memory_collect
1401 pass to word-wide DFFs and address decoders.
1404 \section{memory\_share -- consolidate memory ports}
1405 \label{cmd:memory_share}
1406 \begin{lstlisting}[numbers=left,frame=single]
1407 memory_share [selection]
1409 This pass merges share-able memory ports into single memory ports.
1411 The following methods are used to consolidate the number of memory ports:
1413 - When write ports are connected to async read ports accessing the same
1414 address, then this feedback path is converted to a write port with
1415 byte/part enable signals.
1417 - When multiple write ports access the same address then this is converted
1418 to a single write port with a more complex data and/or enable logic path.
1420 - When multiple write ports are never accessed at the same time (a SAT
1421 solver is used to determine this), then the ports are merged into a single
1424 Note that in addition to the algorithms implemented in this pass, the $memrd
1425 and $memwr cells are also subject to generic resource sharing passes (and other
1426 optimizations) such as opt_share.
1429 \section{memory\_unpack -- unpack multi-port memory cells}
1430 \label{cmd:memory_unpack}
1431 \begin{lstlisting}[numbers=left,frame=single]
1432 memory_unpack [selection]
1434 This pass converts the multi-port $mem memory cells into individual $memrd and
1435 $memwr cells. It is the counterpart to the memory_collect pass.
1438 \section{miter -- automatically create a miter circuit}
1440 \begin{lstlisting}[numbers=left,frame=single]
1441 miter -equiv [options] gold_name gate_name miter_name
1443 Creates a miter circuit for equivalence checking. The gold- and gate- modules
1444 must have the same interfaces. The miter circuit will have all inputs of the
1445 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
1446 output that goes high if an output mismatch between the two source modules is
1450 a undef (x) bit in the gold module output will match any value in
1451 the gate module output.
1454 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
1455 on the miter circuit.
1458 also create a cmp_* output for each gold/gate output pair.
1461 also create an 'assert' cell that checks if trigger is always low.
1464 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
1467 miter -assert [options] module [miter_name]
1469 Creates a miter circuit for property checking. All input ports are kept,
1470 output ports are discarded. An additional output 'trigger' is created that
1471 goes high when an assert is violated. Without a miter_name, the existing
1475 keep module output ports.
1478 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
1481 \section{muxcover -- cover trees of MUX cells with wider MUXes}
1482 \label{cmd:muxcover}
1483 \begin{lstlisting}[numbers=left,frame=single]
1484 muxcover [options] [selection]
1486 Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells
1488 -mux4, -mux8, -mux16
1489 Use the specified types of MUXes. If none of those options are used,
1490 the effect is the same as if all of them where used.
1493 Do not insert decoder logic. This reduces the number of possible
1494 substitutions, but guarantees that the resulting circuit is not
1495 less efficient than the original circuit.
1498 \section{nlutmap -- map to LUTs of different sizes}
1500 \begin{lstlisting}[numbers=left,frame=single]
1501 nlutmap [options] [selection]
1503 This pass uses successive calls to 'abc' to map to an architecture. That
1504 provides a small number of differently sized LUTs.
1506 -luts N_1,N_2,N_3,...
1507 The number of LUTs with 1, 2, 3, ... inputs that are
1508 available in the target architecture.
1510 Excess logic that does not fit into the specified LUTs is mapped back
1511 to generic logic gates ($_AND_, etc.).
1514 \section{opt -- perform simple optimizations}
1516 \begin{lstlisting}[numbers=left,frame=single]
1517 opt [options] [selection]
1519 This pass calls all the other opt_* passes in a useful order. This performs
1520 a series of trivial optimizations and cleanups. This pass executes the other
1521 passes in the following order:
1523 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1524 opt_share [-share_all] -nomux
1528 opt_reduce [-fine] [-full]
1529 opt_share [-share_all]
1532 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1533 while <changed design>
1535 When called with -fast the following script is used instead:
1538 opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
1539 opt_share [-share_all]
1542 while <changed design in opt_rmdff>
1544 Note: Options in square brackets (such as [-keepdc]) are passed through to
1545 the opt_* commands when given to 'opt'.
1548 \section{opt\_clean -- remove unused cells and wires}
1549 \label{cmd:opt_clean}
1550 \begin{lstlisting}[numbers=left,frame=single]
1551 opt_clean [options] [selection]
1553 This pass identifies wires and cells that are unused and removes them. Other
1554 passes often remove cells but leave the wires in the design or reconnect the
1555 wires but leave the old cells in the design. This pass can be used to clean up
1556 after the passes that do the actual work.
1558 This pass only operates on completely selected modules without processes.
1561 also remove internal nets if they have a public name
1564 \section{opt\_const -- perform const folding}
1565 \label{cmd:opt_const}
1566 \begin{lstlisting}[numbers=left,frame=single]
1567 opt_const [options] [selection]
1569 This pass performs const folding on internal cell types with constant inputs.
1572 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
1575 replace $mux cells with inverters or buffers when possible
1578 replace undriven nets with undef (x) constants
1581 optimize clock inverters by changing FF types
1584 perform fine-grain optimizations
1587 alias for -mux_undef -mux_bool -undriven -fine
1590 some optimizations change the behavior of the circuit with respect to
1591 don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
1592 all result bits to be set to x. this behavior changes when 'a+0' is
1593 replaced by 'a'. the -keepdc option disables all such optimizations.
1596 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
1597 \label{cmd:opt_muxtree}
1598 \begin{lstlisting}[numbers=left,frame=single]
1599 opt_muxtree [selection]
1601 This pass analyzes the control signals for the multiplexer trees in the design
1602 and identifies inputs that can never be active. It then removes this dead
1603 branches from the multiplexer trees.
1605 This pass only operates on completely selected modules without processes.
1608 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
1609 \label{cmd:opt_reduce}
1610 \begin{lstlisting}[numbers=left,frame=single]
1611 opt_reduce [options] [selection]
1613 This pass performs two interlinked optimizations:
1615 1. it consolidates trees of large AND gates or OR gates and eliminates
1618 2. it identifies duplicated inputs to MUXes and replaces them with a single
1619 input with the original control signals OR'ed together.
1622 perform fine-grain optimizations
1628 \section{opt\_rmdff -- remove DFFs with constant inputs}
1629 \label{cmd:opt_rmdff}
1630 \begin{lstlisting}[numbers=left,frame=single]
1631 opt_rmdff [selection]
1633 This pass identifies flip-flops with constant inputs and replaces them with
1637 \section{opt\_share -- consolidate identical cells}
1638 \label{cmd:opt_share}
1639 \begin{lstlisting}[numbers=left,frame=single]
1640 opt_share [options] [selection]
1642 This pass identifies cells with identical type and input signals. Such cells
1643 are then merged to one cell.
1646 Do not merge MUX cells.
1649 Operate on all cell types, not just built-in types.
1652 \section{plugin -- load and list loaded plugins}
1654 \begin{lstlisting}[numbers=left,frame=single]
1657 Load and list loaded plugins.
1659 -i <plugin_filename>
1660 Load (install) the specified plugin.
1663 Register the specified alias name for the loaded plugin
1669 \section{pmuxtree -- transform \$pmux cells to trees of \$mux cells}
1670 \label{cmd:pmuxtree}
1671 \begin{lstlisting}[numbers=left,frame=single]
1672 pmuxtree [options] [selection]
1674 This pass transforms $pmux cells to a trees of $mux cells.
1677 \section{prep -- generic synthesis script}
1679 \begin{lstlisting}[numbers=left,frame=single]
1682 This command runs a conservative RTL synthesis. A typical application for this
1683 is the preparation stage of a verification flow. This command does not operate
1684 on partly selected designs.
1687 use the specified module as top module (default='top')
1690 passed to 'memory_dff'. prohibits merging of FFs into memory read ports
1692 -run <from_label>[:<to_label>]
1693 only run the commands between the labels (see below). an empty
1694 from label is synonymous to 'begin', and empty to label is
1695 synonymous to the end of the command list.
1698 The following commands are executed by this synthesis command:
1701 hierarchy -check [-top <top>]
1710 memory_dff [-nordff]
1720 \section{proc -- translate processes to netlists}
1722 \begin{lstlisting}[numbers=left,frame=single]
1723 proc [options] [selection]
1725 This pass calls all the other proc_* passes in the most common order.
1736 This replaces the processes in the design with multiplexers,
1737 flip-flops and latches.
1739 The following options are supported:
1741 -global_arst [!]<netname>
1742 This option is passed through to proc_arst.
1745 \section{proc\_arst -- detect asynchronous resets}
1746 \label{cmd:proc_arst}
1747 \begin{lstlisting}[numbers=left,frame=single]
1748 proc_arst [-global_arst [!]<netname>] [selection]
1750 This pass identifies asynchronous resets in the processes and converts them
1751 to a different internal representation that is suitable for generating
1752 flip-flop cells with asynchronous resets.
1754 -global_arst [!]<netname>
1755 In modules that have a net with the given name, use this net as async
1756 reset for registers that have been assign initial values in their
1757 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
1758 active low reset signals. Note: the frontend stores the default value
1759 in the 'init' attribute on the net.
1762 \section{proc\_clean -- remove empty parts of processes}
1763 \label{cmd:proc_clean}
1764 \begin{lstlisting}[numbers=left,frame=single]
1765 proc_clean [selection]
1767 This pass removes empty parts of processes and ultimately removes a process
1768 if it contains only empty structures.
1771 \section{proc\_dff -- extract flip-flops from processes}
1772 \label{cmd:proc_dff}
1773 \begin{lstlisting}[numbers=left,frame=single]
1774 proc_dff [selection]
1776 This pass identifies flip-flops in the processes and converts them to
1777 d-type flip-flop cells.
1780 \section{proc\_dlatch -- extract latches from processes}
1781 \label{cmd:proc_dlatch}
1782 \begin{lstlisting}[numbers=left,frame=single]
1783 proc_dlatch [selection]
1785 This pass identifies latches in the processes and converts them to
1789 \section{proc\_init -- convert initial block to init attributes}
1790 \label{cmd:proc_init}
1791 \begin{lstlisting}[numbers=left,frame=single]
1792 proc_init [selection]
1794 This pass extracts the 'init' actions from processes (generated from Verilog
1795 'initial' blocks) and sets the initial value to the 'init' attribute on the
1799 \section{proc\_mux -- convert decision trees to multiplexers}
1800 \label{cmd:proc_mux}
1801 \begin{lstlisting}[numbers=left,frame=single]
1802 proc_mux [selection]
1804 This pass converts the decision trees in processes (originating from if-else
1805 and case statements) to trees of multiplexer cells.
1808 \section{proc\_rmdead -- eliminate dead trees in decision trees}
1809 \label{cmd:proc_rmdead}
1810 \begin{lstlisting}[numbers=left,frame=single]
1811 proc_rmdead [selection]
1813 This pass identifies unreachable branches in decision trees and removes them.
1816 \section{qwp -- quadratic wirelength placer}
1818 \begin{lstlisting}[numbers=left,frame=single]
1819 qwp [options] [selection]
1821 This command runs quadratic wirelength placement on the selected modules and
1822 annotates the cells in the design with 'qwp_position' attributes.
1825 Add left-to-right constraints: constrain all inputs on the left border
1826 outputs to the right border.
1829 Add constraints for inputs/outputs to be placed in alphanumerical
1830 order along the y-axis (top-to-bottom).
1833 Number of grid divisions in x- and y-direction. (default=16)
1835 -dump <html_file_name>
1836 Dump a protocol of the placement algorithm to the html file.
1838 Note: This implementation of a quadratic wirelength placer uses exact
1839 dense matrix operations. It is only a toy-placer for small circuits.
1842 \section{read\_blif -- read BLIF file}
1843 \label{cmd:read_blif}
1844 \begin{lstlisting}[numbers=left,frame=single]
1845 read_blif [filename]
1847 Load modules from a BLIF file into the current design.
1850 \section{read\_ilang -- read modules from ilang file}
1851 \label{cmd:read_ilang}
1852 \begin{lstlisting}[numbers=left,frame=single]
1853 read_ilang [filename]
1855 Load modules from an ilang file to the current design. (ilang is a text
1856 representation of a design in yosys's internal format.)
1859 \section{read\_liberty -- read cells from liberty file}
1860 \label{cmd:read_liberty}
1861 \begin{lstlisting}[numbers=left,frame=single]
1862 read_liberty [filename]
1864 Read cells from liberty file as modules into current design.
1867 only create empty blackbox modules
1870 ignore re-definitions of modules. (the default behavior is to
1871 create an error message.)
1874 ignore cells with missing function specification of outputs
1877 ignore cells with a missing or invalid direction
1878 specification on a pin
1880 -setattr <attribute_name>
1881 set the specified attribute (to the value 1) on all loaded modules
1884 \section{read\_verilog -- read modules from Verilog file}
1885 \label{cmd:read_verilog}
1886 \begin{lstlisting}[numbers=left,frame=single]
1887 read_verilog [options] [filename]
1889 Load modules from a Verilog file to the current design. A large subset of
1890 Verilog-2005 is supported.
1893 enable support for SystemVerilog features. (only a small subset
1894 of SystemVerilog is supported)
1897 enable support for assert() and assume() from SystemVerilog
1898 replace the implicit -D SYNTHESIS with -D FORMAL
1901 dump abstract syntax tree (before simplification)
1904 dump abstract syntax tree (after simplification)
1907 dump ast as Verilog code (after simplification)
1910 enable parser debug output
1913 usually latches are synthesized into logic loops
1914 this option prohibits this and sets the output to 'x'
1915 in what would be the latches hold condition
1917 this behavior can also be achieved by setting the
1918 'nolatches' attribute on the respective module or
1922 under certain conditions memories are converted to registers
1923 early during simplification to ensure correct handling of
1924 complex corner cases. this option disables this behavior.
1926 this can also be achieved by setting the 'nomem2reg'
1927 attribute on the respective module or register.
1929 This is potentially dangerous. Usually the front-end has good
1930 reasons for converting an array to a list of registers.
1931 Prohibiting this step will likely result in incorrect synthesis
1935 always convert memories to registers. this can also be
1936 achieved by setting the 'mem2reg' attribute on the respective
1940 do not infer $meminit cells and instead convert initialized
1941 memories to registers directly in the front-end.
1944 dump Verilog code after pre-processor
1947 do not run the pre-processor
1950 disable DPI-C support
1953 only create empty blackbox modules. This implies -DBLACKBOX.
1956 don't perform basic optimizations (such as const folding) in the
1957 high-level front-end.
1960 interpret cell types starting with '$' as internal cell types
1963 ignore re-definitions of modules. (the default behavior is to
1964 create an error message.)
1967 only read the abstract syntax tree and defer actual compilation
1968 to a later 'hierarchy' command. Useful in cases where the default
1969 parameters of modules yield invalid or not synthesizable code.
1972 make the default of `default_nettype be "none" instead of "wire".
1974 -setattr <attribute_name>
1975 set the specified attribute (to the value 1) on all loaded modules
1978 define the preprocessor symbol 'name' and set its optional value
1982 add 'dir' to the directories which are used when searching include
1985 The command 'verilog_defaults' can be used to register default options for
1986 subsequent calls to 'read_verilog'.
1988 Note that the Verilog frontend does a pretty good job of processing valid
1989 verilog input, but has not very good error reporting. It generally is
1990 recommended to use a simulator (for example Icarus Verilog) for checking
1991 the syntax of the code, rather than to rely on read_verilog for that.
1994 \section{rename -- rename object in the design}
1996 \begin{lstlisting}[numbers=left,frame=single]
1997 rename old_name new_name
1999 Rename the specified object. Note that selection patterns are not supported
2003 rename -enumerate [-pattern <pattern>] [selection]
2005 Assign short auto-generated names to all selected wires and cells with private
2006 names. The -pattern option can be used to set the pattern for the new names.
2007 The character % in the pattern is replaced with a integer number. The default
2010 rename -hide [selection]
2012 Assign private names (the ones with $-prefix) to all selected wires and cells
2013 with public names. This ignores all selected ports.
2015 rename -top new_name
2020 \section{sat -- solve a SAT problem in the circuit}
2022 \begin{lstlisting}[numbers=left,frame=single]
2023 sat [options] [selection]
2025 This command solves a SAT problem defined over the currently selected circuit
2026 and additional constraints passed as parameters.
2029 show all solutions to the problem (this can grow exponentially, use
2030 -max <N> instead to get <N> solutions)
2033 like -all, but limit number of solutions to <N>
2036 enable modeling of undef value (aka 'x-bits')
2037 this option is implied by -set-def, -set-undef et. cetera
2040 maximize the number of undef bits in solutions, giving a better
2041 picture of which input bits are actually vital to the solution.
2043 -set <signal> <value>
2044 set the specified signal to the specified value.
2047 add a constraint that all bits of the given signal must be defined
2049 -set-any-undef <signal>
2050 add a constraint that at least one bit of the given signal is undefined
2052 -set-all-undef <signal>
2053 add a constraint that all bits of the given signal are undefined
2056 add -set-def constraints for all module inputs
2059 show the model for the specified signal. if no -show option is
2060 passed then a set of signals to be shown is automatically selected.
2062 -show-inputs, -show-outputs, -show-ports
2063 add all module (input/output) ports to the list of shown signals
2065 -show-regs, -show-public, -show-all
2066 show all registers, show signals with 'public' names, show all signals
2069 ignore all solutions that involve a division by zero
2071 -ignore_unknown_cells
2072 ignore all cells that can not be matched to a SAT model
2074 The following options can be used to set up a sequential problem:
2077 set up a sequential problem with <N> time steps. The steps will
2078 be numbered from 1 to N.
2080 note: for large <N> it can be significantly faster to use
2081 -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.
2083 -set-at <N> <signal> <value>
2084 -unset-at <N> <signal>
2085 set or unset the specified signal to the specified value in the
2086 given timestep. this has priority over a -set for the same signal.
2089 set all assumptions provided via $assume cells
2091 -set-def-at <N> <signal>
2092 -set-any-undef-at <N> <signal>
2093 -set-all-undef-at <N> <signal>
2094 add undef constraints in the given timestep.
2096 -set-init <signal> <value>
2097 set the initial value for the register driving the signal to the value
2100 set all initial states (not set using -set-init) to undef
2103 do not force a value for the initial state but do not allow undef
2106 set all initial states (not set using -set-init) to zero
2108 -dump_vcd <vcd-file-name>
2109 dump SAT model (counter example in proof) to VCD file
2111 -dump_json <json-file-name>
2112 dump SAT model (counter example in proof) to a WaveJSON file.
2114 -dump_cnf <cnf-file-name>
2115 dump CNF of SAT problem (in DIMACS format). in temporal induction
2116 proofs this is the CNF of the first induction step.
2118 The following additional options can be used to set up a proof. If also -seq
2119 is passed, a temporal induction proof is performed.
2122 Perform a temporal induction proof. In a temporal induction proof it is
2123 proven that the condition holds forever after the number of time steps
2124 specified using -seq.
2127 Perform a temporal induction proof. Assume an initial state with all
2128 registers set to defined values for the induction step.
2130 -tempinduct-baseonly
2131 Run only the basecase half of temporal induction (requires -maxsteps)
2133 -tempinduct-inductonly
2134 Run only the induction half of temporal induction
2136 -tempinduct-skip <N>
2137 Skip the first <N> steps of the induction proof.
2139 note: this will assume that the base case holds for <N> steps.
2140 this must be proven independently with "-tempinduct-baseonly
2141 -maxsteps <N>". Use -initsteps if you just want to set a
2142 minimal induction length.
2144 -prove <signal> <value>
2145 Attempt to proof that <signal> is always <value>.
2147 -prove-x <signal> <value>
2148 Like -prove, but an undef (x) bit in the lhs matches any value on
2149 the right hand side. Useful for equivalence checking.
2152 Prove that all asserts in the design hold.
2155 Do not enforce the prove-condition for the first <N> time steps.
2158 Set a maximum length for the induction.
2161 Set initial length for the induction.
2162 This will speed up the search of the right induction length
2163 for deep induction proofs.
2166 Increase the size of the induction proof in steps of <N>.
2167 This will speed up the search of the right induction length
2168 for deep induction proofs.
2171 Maximum number of seconds a single SAT instance may take.
2174 Return an error and stop the synthesis script if the proof fails.
2177 Like -verify but do not return an error for timeouts.
2180 Return an error and stop the synthesis script if the proof succeeds.
2183 Like -falsify but do not return an error for timeouts.
2186 \section{scatter -- add additional intermediate nets}
2188 \begin{lstlisting}[numbers=left,frame=single]
2191 This command adds additional intermediate nets on all cell ports. This is used
2192 for testing the correct use of the SigMap helper in passes. If you don't know
2193 what this means: don't worry -- you only need this pass when testing your own
2194 extensions to Yosys.
2196 Use the opt_clean command to get rid of the additional nets.
2199 \section{scc -- detect strongly connected components (logic loops)}
2201 \begin{lstlisting}[numbers=left,frame=single]
2202 scc [options] [selection]
2204 This command identifies strongly connected components (aka logic loops) in the
2208 expect to find exactly <num> SSCs. A different number of SSCs will
2212 limit to loops not longer than the specified number of cells. This
2213 can e.g. be useful in identifying small local loops in a module that
2214 implements one large SCC.
2217 do not count cells that have their output fed back into one of their
2218 inputs as single-cell scc.
2221 Usually this command only considers internal non-memory cells. With
2222 this option set, all cells are considered. For unknown cells all ports
2223 are assumed to be bidirectional 'inout' ports.
2225 -set_attr <name> <value>
2226 -set_cell_attr <name> <value>
2227 -set_wire_attr <name> <value>
2228 set the specified attribute on all cells and/or wires that are part of
2229 a logic loop. the special token {} in the value is replaced with a
2230 unique identifier for the logic loop.
2233 replace the current selection with a selection of all cells and wires
2234 that are part of a found logic loop
2237 \section{script -- execute commands from script file}
2239 \begin{lstlisting}[numbers=left,frame=single]
2240 script <filename> [<from_label>:<to_label>]
2242 This command executes the yosys commands in the specified file.
2244 The 2nd argument can be used to only execute the section of the
2245 file between the specified labels. An empty from label is synonymous
2246 for the beginning of the file and an empty to label is synonymous
2247 for the end of the file.
2249 If only one label is specified (without ':') then only the block
2250 marked with that label (until the next label) is executed.
2253 \section{select -- modify and view the list of selected objects}
2255 \begin{lstlisting}[numbers=left,frame=single]
2256 select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
2257 select [ -assert-none | -assert-any ] {-read <filename> | <selection>}
2258 select [ -list | -write <filename> | -count | -clear ]
2259 select -module <modname>
2261 Most commands use the list of currently selected objects to determine which part
2262 of the design to operate on. This command can be used to modify and view this
2263 list of selected objects.
2265 Note that many commands support an optional [selection] argument that can be
2266 used to override the global selection for the command. The syntax of this
2267 optional argument is identical to the syntax of the <selection> argument
2271 add or remove the given objects to the current selection.
2272 without this options the current selection is replaced.
2275 do not modify the current selection. instead save the new selection
2276 under the given name (see @<name> below). to save the current selection,
2277 use "select -set <name> %"
2280 do not modify the current selection. instead assert that the given
2281 selection is empty. i.e. produce an error if any object matching the
2285 do not modify the current selection. instead assert that the given
2286 selection is non-empty. i.e. produce an error if no object matching
2287 the selection is found.
2290 do not modify the current selection. instead assert that the given
2291 selection contains exactly N objects.
2294 list all objects in the current selection
2297 like -list but write the output to the specified file
2300 read the specified file (written by -write)
2303 count all objects in the current selection
2306 clear the current selection. this effectively selects the whole
2307 design. it also resets the selected module (see -module). use the
2308 command 'select *' to select everything but stay in the current module.
2311 create an empty selection. the current module is unchanged.
2314 limit the current scope to the specified module.
2315 the difference between this and simply selecting the module
2316 is that all object names are interpreted relative to this
2317 module after this command until the selection is cleared again.
2319 When this command is called without an argument, the current selection
2320 is displayed in a compact form (i.e. only the module name when a whole module
2323 The <selection> argument itself is a series of commands for a simple stack
2324 machine. Each element on the stack represents a set of selected objects.
2325 After this commands have been executed, the union of all remaining sets
2326 on the stack is computed and used as selection for the command.
2328 Pushing (selecting) object when not in -module mode:
2331 select the specified module(s)
2333 <mod_pattern>/<obj_pattern>
2334 select the specified object(s) from the module(s)
2336 Pushing (selecting) object when in -module mode:
2339 select the specified object(s) from the current module
2341 A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
2342 matching module names, or one of the following:
2344 A:<pattern>, A:<pattern>=<pattern>
2345 all modules with an attribute matching the given pattern
2346 in addition to = also <, <=, >=, and > are supported
2348 An <obj_pattern> can be an object name, wildcard expression, or one of
2352 all wires with a name matching the given wildcard pattern
2354 i:<pattern>, o:<pattern>, x:<pattern>
2355 all inputs (i:), outputs (o:) or any ports (x:) with matching names
2357 s:<size>, s:<min>:<max>
2358 all wires with a matching width
2361 all memories with a name matching the given pattern
2364 all cells with a name matching the given pattern
2367 all cells with a type matching the given pattern
2370 all processes with a name matching the given pattern
2373 all objects with an attribute name matching the given pattern
2375 a:<pattern>=<pattern>
2376 all objects with a matching attribute name-value-pair.
2377 in addition to = also <, <=, >=, and > are supported
2379 r:<pattern>, r:<pattern>=<pattern>
2380 cells with matching parameters. also with <, <=, >= and >.
2383 all objects with a name matching the given pattern
2384 (i.e. 'n:' is optional as it is the default matching rule)
2387 push the selection saved prior with 'select -set <name> ...'
2389 The following actions can be performed on the top sets on the stack:
2392 push a copy of the current selection to the stack
2395 replace the stack with a union of all elements on it
2398 replace top set with its invert
2401 replace the two top sets on the stack with their union
2404 replace the two top sets on the stack with their intersection
2407 pop the top set from the stack and subtract it from the new top
2410 like %d but swap the roles of two top sets on the stack
2413 create a copy of the top set from the stack and push it
2415 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2416 expand top set <num1> num times according to the specified rules.
2417 (i.e. select all cells connected to selected wires and select all
2418 wires connected to selected cells) The rules specify which cell
2419 ports to use for this. the syntax for a rule is a '-' for exclusion
2420 and a '+' for inclusion, followed by an optional comma separated
2421 list of cell types followed by an optional comma separated list of
2422 cell ports in square brackets. a rule can also be just a cell or wire
2423 name that limits the expansion (is included but does not go beyond).
2424 select at most <num2> objects. a warning message is printed when this
2425 limit is reached. When '*' is used instead of <num1> then the process
2426 is repeated until no further object are selected.
2428 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2429 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
2430 similar to %x, but only select input (%ci) or output cones (%co)
2432 %xe[...] %cie[...] %coe
2433 like %x, %ci, and %co but only consider combinatorial cells
2436 expand top set by selecting all wires that are (at least in part)
2437 aliases for selected wires.
2440 expand top set by adding all modules that implement cells in selected
2444 expand top set by selecting all modules that contain selected objects
2447 select modules that implement selected cells
2450 select cells that implement selected modules
2453 select <num> random objects from top selection (default 1)
2455 Example: the following command selects all wires that are connected to a
2456 'GATE' input of a 'SWITCH' cell:
2458 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
2461 \section{setattr -- set/unset attributes on objects}
2463 \begin{lstlisting}[numbers=left,frame=single]
2464 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
2466 Set/unset the given attributes on the selected objects. String values must be
2467 passed in double quotes (").
2469 When called with -mod, this command will set and unset attributes on modules
2470 instead of objects within modules.
2473 \section{setparam -- set/unset parameters on objects}
2474 \label{cmd:setparam}
2475 \begin{lstlisting}[numbers=left,frame=single]
2476 setparam [ -set name value | -unset name ]... [selection]
2478 Set/unset the given parameters on the selected cells. String values must be
2479 passed in double quotes (").
2482 \section{setundef -- replace undef values with defined constants}
2483 \label{cmd:setundef}
2484 \begin{lstlisting}[numbers=left,frame=single]
2485 setundef [options] [selection]
2487 This command replaced undef (x) constants with defined (0/1) constants.
2490 also set undriven nets to constant values
2493 replace with bits cleared (0)
2496 replace with bits set (1)
2499 replace with random bits using the specified integer als seed
2500 value for the random number generator.
2503 \section{share -- perform sat-based resource sharing}
2505 \begin{lstlisting}[numbers=left,frame=single]
2506 share [options] [selection]
2508 This pass merges shareable resources into a single resource. A SAT solver
2509 is used to determine if two resources are share-able.
2512 Per default the selection of cells that is considered for sharing is
2513 narrowed using a list of cell types. With this option all selected
2514 cells are considered for resource sharing.
2516 IMPORTANT NOTE: If the -all option is used then no cells with internal
2517 state must be selected!
2520 Per default some heuristics are used to reduce the number of cells
2521 considered for resource sharing to only large resources. This options
2522 turns this heuristics off, resulting in much more cells being considered
2523 for resource sharing.
2526 Only consider the simple part of the control logic in SAT solving, resulting
2527 in much easier SAT problems at the cost of maybe missing some opportunities
2528 for resource sharing.
2531 Only perform the first N merges, then stop. This is useful for debugging.
2534 \section{shell -- enter interactive command mode}
2536 \begin{lstlisting}[numbers=left,frame=single]
2539 This command enters the interactive command mode. This can be useful
2540 in a script to interrupt the script at a certain point and allow for
2541 interactive inspection or manual synthesis of the design at this point.
2543 The command prompt of the interactive shell indicates the current
2544 selection (see 'help select'):
2547 the entire design is selected
2550 only part of the design is selected
2553 the entire module 'modname' is selected using 'select -module modname'
2556 only part of current module 'modname' is selected
2558 When in interactive shell, some errors (e.g. invalid command arguments)
2559 do not terminate yosys but return to the command prompt.
2561 This command is the default action if nothing else has been specified
2562 on the command line.
2564 Press Ctrl-D or type 'exit' to leave the interactive shell.
2567 \section{show -- generate schematics using graphviz}
2569 \begin{lstlisting}[numbers=left,frame=single]
2570 show [options] [selection]
2572 Create a graphviz DOT file for the selected part of the design and compile it
2573 to a graphics file (usually SVG or PostScript).
2576 Run the specified command with the graphics file as parameter.
2579 Generate a graphics file in the specified format.
2580 Usually <format> is 'svg' or 'ps'.
2582 -lib <verilog_or_ilang_file>
2583 Use the specified library file for determining whether cell ports are
2584 inputs or outputs. This option can be used multiple times to specify
2585 more than one library.
2587 note: in most cases it is better to load the library before calling
2588 show with 'read_verilog -lib <filename>'. it is also possible to
2589 load liberty files with 'read_liberty -lib <filename>'.
2592 generate <prefix>.* instead of ~/.yosys_show.*
2594 -color <color> <object>
2595 assign the specified color to the specified object. The object can be
2596 a single selection wildcard expressions or a saved set of objects in
2597 the @<name> syntax (see "help select" for details).
2599 -label <text> <object>
2600 assign the specified label text to the specified object. The object can
2601 be a single selection wildcard expressions or a saved set of objects in
2602 the @<name> syntax (see "help select" for details).
2605 Randomly assign colors to the wires. The integer argument is the seed
2606 for the random number generator. Change the seed value if the colored
2607 graph still is ambiguous. A seed of zero deactivates the coloring.
2609 -colorattr <attribute_name>
2610 Use the specified attribute to assign colors. A unique color is
2611 assigned to each unique value of this attribute.
2614 annotate busses with a label indicating the width of the bus.
2617 mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
2618 cell parameter) with an asterisk next to the port name.
2621 stretch the graph so all inputs are on the left side and all outputs
2622 (including inout ports) are on the right side.
2625 wait for the use to press enter to before returning
2628 enumerate objects with internal ($-prefixed) names
2631 do not abbreviate objects with internal ($-prefixed) names
2634 do not add the module name as graph title to the dot file
2636 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
2637 specified, 'xdot' is used to display the schematic.
2639 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
2640 unless another prefix is specified using -prefix <prefix>.
2642 Yosys on Windows and YosysJS use different defaults: The output is written
2643 to 'show.dot' in the current directory and new viewer is launched.
2646 \section{simplemap -- mapping simple coarse-grain cells}
2647 \label{cmd:simplemap}
2648 \begin{lstlisting}[numbers=left,frame=single]
2649 simplemap [selection]
2651 This pass maps a small selection of simple coarse-grain cells to yosys gate
2652 primitives. The following internal cell types are mapped by this pass:
2654 $not, $pos, $and, $or, $xor, $xnor
2655 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
2656 $logic_not, $logic_and, $logic_or, $mux, $tribuf
2657 $sr, $dff, $dffsr, $adff, $dlatch
2660 \section{singleton -- create singleton modules}
2661 \label{cmd:singleton}
2662 \begin{lstlisting}[numbers=left,frame=single]
2663 singleton [selection]
2665 By default, a module that is instantiated by several other modules is only
2666 kept once in the design. This preserves the original modularity of the design
2667 and reduces the overall size of the design in memory. But it prevents certain
2668 optimizations and other operations on the design. This pass creates singleton
2669 modules for all selected cells. The created modules are marked with the
2670 'singleton' attribute.
2672 This commands only operates on modules that by themself have the 'singleton'
2673 attribute set (the 'top' module is a singleton implicitly).
2676 \section{splice -- create explicit splicing cells}
2678 \begin{lstlisting}[numbers=left,frame=single]
2679 splice [options] [selection]
2681 This command adds $slice and $concat cells to the design to make the splicing
2682 of multi-bit signals explicit. This for example is useful for coarse grain
2683 synthesis, where dedicated hardware is needed to splice signals.
2686 only select the cell ports to rewire by the cell. if the selection
2687 contains a cell, than all cell inputs are rewired, if necessary.
2690 only select the cell ports to rewire by the wire. if the selection
2691 contains a wire, than all cell ports driven by this wire are wired,
2695 it is sufficient if the driver of any bit of a cell port is selected.
2696 by default all bits must be selected.
2699 also add $slice and $concat cells to drive otherwise unused wires.
2702 do not rewire selected module outputs.
2705 only rewire cell ports with the specified name. can be used multiple
2706 times. implies -no_output.
2709 do not rewire cell ports with the specified name. can be used multiple
2710 times. can not be combined with -port <name>.
2712 By default selected output wires and all cell ports of selected cells driven
2713 by selected wires are rewired.
2716 \section{splitnets -- split up multi-bit nets}
2717 \label{cmd:splitnets}
2718 \begin{lstlisting}[numbers=left,frame=single]
2719 splitnets [options] [selection]
2721 This command splits multi-bit nets into single-bit nets.
2723 -format char1[char2[char3]]
2724 the first char is inserted between the net name and the bit index, the
2725 second char is appended to the netname. e.g. -format () creates net
2726 names like 'mysignal(42)'. the 3rd character is the range separation
2727 character when creating multi-bit wires. the default is '[]:'.
2730 also split module ports. per default only internal signals are split.
2733 don't blindly split nets in individual bits. instead look at the driver
2734 and split nets so that no driver drives only part of a net.
2737 \section{stat -- print some statistics}
2739 \begin{lstlisting}[numbers=left,frame=single]
2740 stat [options] [selection]
2742 Print some statistics (number of objects) on the selected portion of the
2746 print design hierarchy with this module as top. if the design is fully
2747 selected and a module has the 'top' attribute set, this module is used
2748 default value for this option.
2750 -liberty <liberty_file>
2751 use cell area information from the provided liberty file
2754 annotate internal cell types with their word width.
2755 e.g. $add_8 for an 8 bit wide $add cell.
2758 \section{submod -- moving part of a module to a new submodule}
2760 \begin{lstlisting}[numbers=left,frame=single]
2761 submod [-copy] [selection]
2763 This pass identifies all cells with the 'submod' attribute and moves them to
2764 a newly created module. The value of the attribute is used as name for the
2765 cell that replaces the group of cells with the same attribute value.
2767 This pass can be used to create a design hierarchy in flat design. This can
2768 be useful for analyzing or reverse-engineering a design.
2770 This pass only operates on completely selected modules with no processes
2774 submod -name <name> [-copy] [selection]
2776 As above, but don't use the 'submod' attribute but instead use the selection.
2777 Only objects from one module might be selected. The value of the -name option
2778 is used as the value of the 'submod' attribute above.
2780 By default the cells are 'moved' from the source module and the source module
2781 will use an instance of the new module after this command is finished. Call
2782 with -copy to not modify the source module.
2785 \section{synth -- generic synthesis script}
2787 \begin{lstlisting}[numbers=left,frame=single]
2790 This command runs the default synthesis script. This command does not operate
2791 on partly selected designs.
2794 use the specified module as top module (default='top')
2797 passed to 'fsm_recode' via 'fsm'
2800 do not run FSM optimization
2803 do not run abc (as if yosys was compiled without ABC support)
2806 do not run 'alumacc' pass. i.e. keep arithmetic operators in
2807 their direct form ($add, $sub, etc.).
2810 passed to 'memory'. prohibits merging of FFs into memory read ports
2812 -run <from_label>[:<to_label>]
2813 only run the commands between the labels (see below). an empty
2814 from label is synonymous to 'begin', and empty to label is
2815 synonymous to the end of the command list.
2818 The following commands are executed by this synthesis command:
2821 hierarchy -check [-top <top>]
2853 \section{synth\_greenpak4 -- synthesis for GreenPAK4 FPGAs}
2854 \label{cmd:synth_greenpak4}
2855 \begin{lstlisting}[numbers=left,frame=single]
2856 synth_greenpak4 [options]
2858 This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
2861 use the specified module as top module (default='top')
2864 write the design to the specified BLIF file. writing of an output file
2865 is omitted if this parameter is not specified.
2868 write the design to the specified edif file. writing of an output file
2869 is omitted if this parameter is not specified.
2871 -run <from_label>:<to_label>
2872 only run the commands between the labels (see below). an empty
2873 from label is synonymous to 'begin', and empty to label is
2874 synonymous to the end of the command list.
2877 do not flatten design before synthesis
2880 run 'abc' with -dff option
2883 The following commands are executed by this synthesis command:
2886 read_verilog -lib +/greenpak4/cells_sim.v
2887 hierarchy -check -top <top>
2889 flatten: (unless -noflatten)
2898 opt -fast -mux_undef -undriven -fine
2902 dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
2904 abc -dff (only if -retime)
2907 nlutmap -luts 0,8,16,2
2911 techmap -map +/greenpak4/cells_map.v
2920 write_blif -gates -attr -param <file-name>
2923 write_edif <file-name>
2926 \section{synth\_ice40 -- synthesis for iCE40 FPGAs}
2927 \label{cmd:synth_ice40}
2928 \begin{lstlisting}[numbers=left,frame=single]
2929 synth_ice40 [options]
2931 This command runs synthesis for iCE40 FPGAs. This work is experimental.
2934 use the specified module as top module (default='top')
2937 write the design to the specified BLIF file. writing of an output file
2938 is omitted if this parameter is not specified.
2941 write the design to the specified edif file. writing of an output file
2942 is omitted if this parameter is not specified.
2944 -run <from_label>:<to_label>
2945 only run the commands between the labels (see below). an empty
2946 from label is synonymous to 'begin', and empty to label is
2947 synonymous to the end of the command list.
2950 do not flatten design before synthesis
2953 run 'abc' with -dff option
2956 do not use SB_CARRY cells in output netlist
2959 do not use SB_RAM40_4K* cells in output netlist
2962 run two passes of 'abc' for slightly improved logic density
2965 The following commands are executed by this synthesis command:
2968 read_verilog -lib +/ice40/cells_sim.v
2969 hierarchy -check -top <top>
2971 flatten: (unless -noflatten)
2979 bram: (skip if -nobram)
2980 memory_bram -rules +/ice40/brams.txt
2981 techmap -map +/ice40/brams_map.v
2984 opt -fast -mux_undef -undriven -fine
2987 techmap -map +/techmap.v [-map +/ice40/arith_map.v]
2988 abc -dff (only if -retime)
2993 dff2dffe -direct-match $_DFF_*
2994 techmap -map +/ice40/cells_map.v
2995 opt_const -mux_undef
3003 ice40_opt (only if -abc2)
3008 techmap -map +/ice40/cells_map.v
3017 write_blif -gates -attr -param <file-name>
3020 write_edif <file-name>
3023 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
3024 \label{cmd:synth_xilinx}
3025 \begin{lstlisting}[numbers=left,frame=single]
3026 synth_xilinx [options]
3028 This command runs synthesis for Xilinx FPGAs. This command does not operate on
3029 partly selected designs. At the moment this command creates netlists that are
3030 compatible with 7-Series Xilinx devices.
3033 use the specified module as top module
3036 write the design to the specified edif file. writing of an output file
3037 is omitted if this parameter is not specified.
3039 -run <from_label>:<to_label>
3040 only run the commands between the labels (see below). an empty
3041 from label is synonymous to 'begin', and empty to label is
3042 synonymous to the end of the command list.
3045 flatten design before synthesis
3048 run 'abc' with -dff option
3051 The following commands are executed by this synthesis command:
3054 read_verilog -lib +/xilinx/cells_sim.v
3055 read_verilog -lib +/xilinx/brams_bb.v
3056 read_verilog -lib +/xilinx/drams_bb.v
3057 hierarchy -check -top <top>
3059 flatten: (only if -flatten)
3067 memory_bram -rules +/xilinx/brams.txt
3068 techmap -map +/xilinx/brams_map.v
3071 memory_bram -rules +/xilinx/drams.txt
3072 techmap -map +/xilinx/drams_map.v
3080 techmap -map +/techmap.v -map +/xilinx/arith_map.v
3084 abc -luts 2:2,3,6:5,10,20 [-dff]
3088 techmap -map +/xilinx/cells_map.v
3089 dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
3097 edif: (only if -edif)
3098 write_edif <file-name>
3101 \section{tcl -- execute a TCL script file}
3103 \begin{lstlisting}[numbers=left,frame=single]
3106 This command executes the tcl commands in the specified file.
3107 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
3109 The tcl command 'yosys -import' can be used to import all yosys
3110 commands directly as tcl commands to the tcl shell. The yosys
3111 command 'proc' is wrapped using the tcl command 'procs' in order
3112 to avoid a name collision with the tcl builtin command 'proc'.
3115 \section{techmap -- generic technology mapper}
3117 \begin{lstlisting}[numbers=left,frame=single]
3118 techmap [-map filename] [selection]
3120 This pass implements a very simple technology mapper that replaces cells in
3121 the design with implementations given in form of a Verilog or ilang source
3125 the library of cell implementations to be used.
3126 without this parameter a builtin library is used that
3127 transforms the internal RTL cells to the internal gate
3131 like -map above, but with an in-memory design instead of a file.
3134 load the cell implementations as separate modules into the design
3135 instead of inlining them.
3138 only run the specified number of iterations.
3141 instead of the iterative breadth-first algorithm use a recursive
3142 depth-first algorithm. both methods should yield equivalent results,
3143 but may differ in performance.
3146 Automatically call "proc" on implementations that contain processes.
3149 this option will cause techmap to exit with an error if it can't map
3150 a selected cell. only cell types that end on an underscore are accepted
3151 as final cell types by this mode.
3153 -D <define>, -I <incdir>
3154 this options are passed as-is to the Verilog frontend for loading the
3155 map file. Note that the Verilog frontend is also called with the
3156 '-ignore_redef' option set.
3158 When a module in the map file has the 'techmap_celltype' attribute set, it will
3159 match cells with a type that match the text value of this attribute. Otherwise
3160 the module name will be used to match the cell.
3162 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
3163 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
3165 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
3166 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
3168 When a module in the map file has the 'techmap_wrap' attribute set, techmap
3169 will create a wrapper for the cell and then run the command string that the
3170 attribute is set to on the wrapper module.
3172 All wires in the modules from the map file matching the pattern _TECHMAP_*
3173 or *._TECHMAP_* are special wires that are used to pass instructions from
3174 the mapping module to the techmap command. At the moment the following special
3175 wires are supported:
3178 When this wire is set to a non-zero constant value, techmap will not
3179 use this module and instead try the next module with a matching
3180 'techmap_celltype' attribute.
3182 When such a wire exists but does not have a constant value after all
3183 _TECHMAP_DO_* commands have been executed, an error is generated.
3186 This wires are evaluated in alphabetical order. The constant text value
3187 of this wire is a yosys command (or sequence of commands) that is run
3188 by techmap on the module. A common use case is to run 'proc' on modules
3189 that are written using always-statements.
3191 When such a wire has a non-constant value at the time it is to be
3192 evaluated, an error is produced. That means it is possible for such a
3193 wire to start out as non-constant and evaluate to a constant value
3194 during processing of other _TECHMAP_DO_* commands.
3196 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
3197 in this case techmap will create a copy for each distinct configuration
3198 of constant inputs and shorted inputs at this point and import the
3199 constant and connected bits into the map module. All further commands
3200 are executed in this copy. This is a very convenient way of creating
3201 optimized specializations of techmap modules without using the special
3202 parameters described below.
3204 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
3205 then techmap will recursively replace the cells in the module with their
3206 implementation. This is not affected by the -max_iter option.
3208 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
3210 In addition to this special wires, techmap also supports special parameters in
3211 modules in the map file:
3214 When a parameter with this name exists, it will be set to the type name
3215 of the cell that matches the module.
3217 _TECHMAP_CONSTMSK_<port-name>_
3218 _TECHMAP_CONSTVAL_<port-name>_
3219 When this pair of parameters is available in a module for a port, then
3220 former has a 1-bit for each constant input bit and the latter has the
3221 value for this bit. The unused bits of the latter are set to undef (x).
3223 _TECHMAP_BITS_CONNMAP_
3224 _TECHMAP_CONNMAP_<port-name>_
3225 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
3226 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
3227 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
3228 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
3229 This can be used to detect shorted inputs.
3231 When a module in the map file has a parameter where the according cell in the
3232 design has a port, the module from the map file is only used if the port in
3233 the design is connected to a constant value. The parameter is then set to the
3236 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
3237 of the cell that is being replaced.
3239 See 'help extract' for a pass that does the opposite thing.
3241 See 'help flatten' for a pass that does flatten the design (which is
3242 essentially techmap but using the design itself as map library).
3245 \section{tee -- redirect command output to file}
3247 \begin{lstlisting}[numbers=left,frame=single]
3248 tee [-q] [-o logfile|-a logfile] cmd
3250 Execute the specified command, optionally writing the commands output to the
3251 specified logfile(s).
3254 Do not print output to the normal destination (console and/or log file)
3257 Write output to this file, truncate if exists.
3260 Write output to this file, append if exists.
3263 \section{test\_abcloop -- automatically test handling of loops in abc command}
3264 \label{cmd:test_abcloop}
3265 \begin{lstlisting}[numbers=left,frame=single]
3266 test_abcloop [options]
3268 Test handling of logic loops in ABC.
3271 create this number of circuits and test them (default = 100).
3273 -s {positive_integer}
3274 use this value as rng seed value (default = unix time).
3277 \section{test\_autotb -- generate simple test benches}
3278 \label{cmd:test_autotb}
3279 \begin{lstlisting}[numbers=left,frame=single]
3280 test_autotb [options] [filename]
3282 Automatically create primitive Verilog test benches for all modules in the
3283 design. The generated testbenches toggle the input pins of the module in
3284 a semi-random manner and dumps the resulting output signals.
3286 This can be used to check the synthesis results for simple circuits by
3287 comparing the testbench output for the input files and the synthesis results.
3289 The backend automatically detects clock signals. Additionally a signal can
3290 be forced to be interpreted as clock signal by setting the attribute
3291 'gentb_clock' on the signal.
3293 The attribute 'gentb_constant' can be used to force a signal to a constant
3294 value after initialization. This can e.g. be used to force a reset signal
3295 low in order to explore more inner states in a state machine.
3298 number of iterations the test bench should run (default = 1000)
3301 \section{test\_cell -- automatically test the implementation of a cell type}
3302 \label{cmd:test_cell}
3303 \begin{lstlisting}[numbers=left,frame=single]
3304 test_cell [options] {cell-types}
3306 Tests the internal implementation of the given cell type (for example '$add')
3307 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
3309 Run with 'all' instead of a cell type to run the test on all supported
3310 cell types. Use for example 'all /$add' for all cell types except $add.
3313 create this number of cell instances and test them (default = 100).
3315 -s {positive_integer}
3316 use this value as rng seed value (default = unix time).
3319 don't generate circuits. instead load the specified ilang file.
3321 -w {filename_prefix}
3322 don't test anything. just generate the circuits and write them
3323 to ilang files with the specified prefix
3326 pass this option to techmap.
3329 use "techmap -map +/simlib.v -max_iter 2 -autoproc"
3332 instead of calling "techmap", call "aigmap"
3335 when creating test benches with dividers, create an additional mux
3336 to mask out the division-by-zero case
3338 -script {script_file}
3339 instead of calling "techmap", call "script {script_file}".
3342 set some input bits to random constant values
3345 do not check SAT model or run SAT equivalence checking
3348 do not check const-eval models
3351 print additional debug information to the console
3354 create a Verilog test bench to test simlib and write_verilog
3357 \section{torder -- print cells in topological order}
3359 \begin{lstlisting}[numbers=left,frame=single]
3360 torder [options] [selection]
3362 This command prints the selected cells in topological order.
3364 -stop <cell_type> <cell_port>
3365 do not use the specified cell port in topological sorting
3368 by default Q outputs of internal FF cells and memory read port outputs
3369 are not used in topological sorting. this option deactivates that.
3372 \section{trace -- redirect command output to file}
3374 \begin{lstlisting}[numbers=left,frame=single]
3377 Execute the specified command, logging all changes the command performs on
3378 the design in real time.
3381 \section{tribuf -- infer tri-state buffers}
3383 \begin{lstlisting}[numbers=left,frame=single]
3384 tribuf [options] [selection]
3386 This pass transforms $mux cells with 'z' inputs to tristate buffers.
3389 merge multiple tri-state buffers driving the same net
3390 into a single buffer.
3393 convert tri-state buffers that do not drive output ports
3394 to non-tristate logic. this option implies -merge.
3397 \section{verific -- load Verilog and VHDL designs using Verific}
3399 \begin{lstlisting}[numbers=left,frame=single]
3400 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
3402 Load the specified Verilog/SystemVerilog files into Verific.
3405 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
3407 Load the specified VHDL files into Verific.
3410 verific -import [-gates] {-all | <top-module>..}
3412 Elaborate the design for the specified top modules, import to Yosys and
3413 reset the internal state of Verific. A gate-level netlist is created
3414 when called with -gates.
3416 Visit http://verific.com/ for more information on Verific.
3419 \section{verilog\_defaults -- set default options for read\_verilog}
3420 \label{cmd:verilog_defaults}
3421 \begin{lstlisting}[numbers=left,frame=single]
3422 verilog_defaults -add [options]
3424 Add the specified options to the list of default options to read_verilog.
3427 verilog_defaults -clear
3428 Clear the list of Verilog default options.
3431 verilog_defaults -push verilog_defaults -pop
3432 Push or pop the list of default options to a stack. Note that -push does
3436 \section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
3437 \label{cmd:vhdl2verilog}
3438 \begin{lstlisting}[numbers=left,frame=single]
3439 vhdl2verilog [options] <vhdl-file>..
3441 This command reads VHDL source files using the 'vhdl2verilog' tool and the
3442 Yosys Verilog frontend.
3445 do not import the vhdl2verilog output. instead write it to the
3448 -vhdl2verilog_dir <directory>
3449 do use the specified vhdl2verilog installation. this is the directory
3450 that contains the setup_env.sh file. when this option is not present,
3451 it is assumed that vhdl2verilog is in the PATH environment variable.
3453 -top <top-entity-name>
3454 The name of the top entity. This option is mandatory.
3456 The following options are passed as-is to vhdl2verilog:
3458 -arch <architecture_name>
3468 vhdl2verilog can be obtained from:
3469 http://www.edautils.com/vhdl2verilog.html
3472 \section{wreduce -- reduce the word size of operations if possible}
3474 \begin{lstlisting}[numbers=left,frame=single]
3475 wreduce [options] [selection]
3477 This command reduces the word size of operations. For example it will replace
3478 the 32 bit adders in the following code with adders of more appropriate widths:
3480 module test(input [3:0] a, b, c, output [7:0] y);
3481 assign y = a + b + c + 1;
3485 \section{write\_blif -- write design to BLIF file}
3486 \label{cmd:write_blif}
3487 \begin{lstlisting}[numbers=left,frame=single]
3488 write_blif [options] [filename]
3490 Write the current design to an BLIF file.
3493 set the specified module as design top module
3495 -buf <cell-type> <in-port> <out-port>
3496 use cells of type <cell-type> with the specified port names for buffers
3498 -unbuf <cell-type> <in-port> <out-port>
3499 replace buffer cells with the specified name and port names with
3500 a .names statement that models a buffer
3502 -true <cell-type> <out-port>
3503 -false <cell-type> <out-port>
3504 -undef <cell-type> <out-port>
3505 use the specified cell types to drive nets that are constant 1, 0, or
3506 undefined. when '-' is used as <cell-type>, then <out-port> specifies
3507 the wire name to be used for the constant signal and no cell driving
3508 that wire is generated.
3510 The following options can be useful when the generated file is not going to be
3511 read by a BLIF parser but a custom tool. It is recommended to not name the output
3512 file *.blif when any of this options is used.
3515 do not translate Yosys's internal gates to generic BLIF logic
3516 functions. Instead create .subckt or .gate lines for all cells.
3519 print .gate instead of .subckt lines for all cells that are not
3520 instantiations of other modules from this design.
3523 do not generate buffers for connected wires. instead use the
3524 non-standard .conn statement.
3527 use the non-standard .attr statement to write cell attributes
3530 use the non-standard .param statement to write cell parameters
3533 use the non-standard .cname statement to write cell names
3536 write blackbox cells with .blackbox statement.
3539 do not write definitions for the $true, $false and $undef wires.
3542 \section{write\_btor -- write design to BTOR file}
3543 \label{cmd:write_btor}
3544 \begin{lstlisting}[numbers=left,frame=single]
3545 write_btor [filename]
3547 Write the current design to an BTOR file.
3550 \section{write\_edif -- write design to EDIF netlist file}
3551 \label{cmd:write_edif}
3552 \begin{lstlisting}[numbers=left,frame=single]
3553 write_edif [options] [filename]
3555 Write the current design to an EDIF netlist file.
3558 set the specified module as design top module
3560 Unfortunately there are different "flavors" of the EDIF file format. This
3561 command generates EDIF files for the Xilinx place&route tools. It might be
3562 necessary to make small modifications to this command when a different tool
3566 \section{write\_file -- write a text to a file}
3567 \label{cmd:write_file}
3568 \begin{lstlisting}[numbers=left,frame=single]
3569 write_file [options] output_file [input_file]
3571 Write the text from the input file to the output file.
3574 Append to output file (instead of overwriting)
3577 Inside a script the input file can also can a here-document:
3579 write_file hello.txt <<EOT
3584 \section{write\_ilang -- write design to ilang file}
3585 \label{cmd:write_ilang}
3586 \begin{lstlisting}[numbers=left,frame=single]
3587 write_ilang [filename]
3589 Write the current design to an 'ilang' file. (ilang is a text representation
3590 of a design in yosys's internal format.)
3593 only write selected parts of the design.
3596 \section{write\_intersynth -- write design to InterSynth netlist file}
3597 \label{cmd:write_intersynth}
3598 \begin{lstlisting}[numbers=left,frame=single]
3599 write_intersynth [options] [filename]
3601 Write the current design to an 'intersynth' netlist file. InterSynth is
3602 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
3605 do not generate celltypes and conntypes commands. i.e. just output
3606 the netlists. this is used for postsilicon synthesis.
3608 -lib <verilog_or_ilang_file>
3609 Use the specified library file for determining whether cell ports are
3610 inputs or outputs. This option can be used multiple times to specify
3611 more than one library.
3614 only write selected modules. modules must be selected entirely or
3617 http://www.clifford.at/intersynth/
3620 \section{write\_json -- write design to a JSON file}
3621 \label{cmd:write_json}
3622 \begin{lstlisting}[numbers=left,frame=single]
3623 write_json [options] [filename]
3625 Write a JSON netlist of the current design.
3628 include AIG models for the different gate types
3631 The general syntax of the JSON output created by this command is as follows:
3637 <port_name>: <port_details>,
3641 <cell_name>: <cell_details>,
3645 <net_name>: <net_details>,
3655 Where <port_details> is:
3658 "direction": <"input" | "output" | "inout">,
3659 "bits": <bit_vector>
3662 And <cell_details> is:
3665 "hide_name": <1 | 0>,
3666 "type": <cell_type>,
3668 <parameter_name>: <parameter_value>,
3672 <attribute_name>: <attribute_value>,
3675 "port_directions": {
3676 <port_name>: <"input" | "output" | "inout">,
3680 <port_name>: <bit_vector>,
3685 And <net_details> is:
3688 "hide_name": <1 | 0>,
3689 "bits": <bit_vector>
3692 The "hide_name" fields are set to 1 when the name of this cell or net is
3693 automatically created and is likely not of interest for a regular user.
3695 The "port_directions" section is only included for cells for which the
3698 Module and cell ports and nets can be single bit wide or vectors of multiple
3699 bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
3700 values referenced above are vectors of this integers. Signal bits that are
3701 connected to a constant driver are denoted as string "0" or "1" instead of
3704 For example the following Verilog code:
3706 module test(input x, y);
3707 (* keep *) foo #(.P(
42), .Q(
1337))
3708 foo_inst (.A(
{x, y
}), .B(
{y, x
}), .C(
{4'd10,
{4{x
}}}));
3711 Translates to the following JSON output:
3718 "direction": "input",
3722 "direction": "input",
3739 "C":
[ 2,
2,
2,
2, "
0", "
1", "
0", "
1"
],
3765 The models are given as And-Inverter-Graphs (AIGs) in the following form:
3769 /*
0 */
[ <node-spec>
],
3770 /*
1 */
[ <node-spec>
],
3771 /*
2 */
[ <node-spec>
],
3777 The following node-types may be used:
3779 [ "port", <portname>, <bitindex>, <out-list>
]
3780 - the value of the specified input port bit
3782 [ "nport", <portname>, <bitindex>, <out-list>
]
3783 - the inverted value of the specified input port bit
3785 [ "and", <node-index>, <node-index>, <out-list>
]
3786 - the ANDed value of the speciefied nodes
3788 [ "nand", <node-index>, <node-index>, <out-list>
]
3789 - the inverted ANDed value of the speciefied nodes
3791 [ "true", <out-list>
]
3792 - the constant value
1
3794 [ "false", <out-list>
]
3795 - the constant value
0
3797 All nodes appear in topological order. I.e. only nodes with smaller indices
3798 are referenced by "and" and "nand" nodes.
3800 The optional <out-list> at the end of a node specification is a list of
3801 output portname and bitindex pairs, specifying the outputs driven by this node.
3803 For example, the following is the model for a
3-input
3-output $reduce_and cell
3804 inferred by the following code:
3806 module test(input
[2:
0] in, output
[2:
0] out);
3810 "$reduce_and:
3U:
3":
[
3811 /*
0 */
[ "port", "A",
0 ],
3812 /*
1 */
[ "port", "A",
1 ],
3813 /*
2 */
[ "and",
0,
1 ],
3814 /*
3 */
[ "port", "A",
2 ],
3815 /*
4 */
[ "and",
2,
3, "Y",
0 ],
3816 /*
5 */
[ "false", "Y",
1, "Y",
2 ]
3819 Future version of Yosys might add support for additional fields in the JSON
3820 format. A program processing this format must ignore all unkown fields.
3823 \section{write
\_smt2 -- write design to SMT-LIBv2 file
}
3824 \label{cmd:write_smt2
}
3825 \begin{lstlisting
}[numbers=left,frame=single
]
3826 write_smt2
[options
] [filename
]
3828 Write a SMT-LIBv2
[1] description of the current design. For a module with name
3829 '<mod>' this will declare the sort '<mod>_s' (state of the module) and the
3830 functions operating on that state.
3832 The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions
3833 are provided that can be used to access the values of the signals in the module.
3834 Only ports, and signals with the 'keep' attribute set are made available via
3835 such functions. Without the -bv option, multi-bit wires are exported as
3836 separate functions of type Bool for the individual bits. With the -bv option
3837 multi-bit wires are exported as single functions of type BitVec.
3839 The '<mod>_t' function evaluates to 'true' when the given pair of states
3840 describes a valid state transition.
3842 The '<mod>_a' function evaluates to 'true' when the given state satisfies
3843 the asserts in the module.
3845 The '<mod>_u' function evaluates to 'true' when the given state satisfies
3846 the assumptions in the module.
3848 The '<mod>_i' function evaluates to 'true' when the given state conforms
3849 to the initial state.
3852 this will print the recursive walk used to export the modules.
3855 enable support for BitVec (FixedSizeBitVectors theory). with this
3856 option set multi-bit wires are represented using the BitVec sort and
3857 support for coarse grain cells (incl. arithmetic) is enabled.
3860 enable support for memories (via ArraysEx theory). this option
3861 also implies -bv. only $mem cells without merged registers in
3862 read ports are supported. call "memory" with -nordff to make sure
3863 that no registers are merged into $mem read ports. '<mod>_m' functions
3864 will be generated for accessing the arrays that are used to represent
3868 also create '<mod>_n' functions for all registers.
3871 also create '<mod>_n' functions for all public wires.
3873 -tpl <template_file>
3874 use the given template file. the line containing only the token '
%%'
3875 is replaced with the regular output of this command.
3877 [1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
3878 R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
3880 ---------------------------------------------------------------------------
3884 Consider the following module (test.v). We want to prove that the output can
3885 never transition from a non-zero value to a zero value.
3887 module test(input clk, output reg
[3:
0] y);
3888 always @(posedge clk)
3892 For this proof we create the following template (test.tpl).
3894 ; we need QF_UFBV for this poof
3897 ; insert the auto-generated code here
3900 ; declare two state variables s1 and s2
3901 (declare-fun s1 () test_s)
3902 (declare-fun s2 () test_s)
3904 ; state s2 is the successor of state s1
3905 (assert (test_t s1 s2))
3907 ; we are looking for a model with y non-zero in s1
3908 (assert (distinct (|test_n y| s1) #b0000))
3910 ; we are looking for a model with y zero in s2
3911 (assert (= (|test_n y| s2) #b0000))
3913 ; is there such a model?
3916 The following yosys script will create a 'test.smt2' file for our proof:
3919 hierarchy -check; proc; opt; check -assert
3920 write_smt2 -bv -tpl test.tpl test.smt2
3922 Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
3923 from non-zero to zero in the test design.
3926 \section{write
\_smv -- write design to SMV file
}
3927 \label{cmd:write_smv
}
3928 \begin{lstlisting
}[numbers=left,frame=single
]
3929 write_smv
[options
] [filename
]
3931 Write an SMV description of the current design.
3934 this will print the recursive walk used to export the modules.
3936 -tpl <template_file>
3937 use the given template file. the line containing only the token '
%%'
3938 is replaced with the regular output of this command.
3940 THIS COMMAND IS UNDER CONSTRUCTION
3943 \section{write
\_spice -- write design to SPICE netlist file
}
3944 \label{cmd:write_spice
}
3945 \begin{lstlisting
}[numbers=left,frame=single
]
3946 write_spice
[options
] [filename
]
3948 Write the current design to an SPICE netlist file.
3951 generate multi-bit ports in MSB first order
3952 (default is LSB first)
3955 set the net name for constant
0 (default: Vss)
3958 set the net name for constant
1 (default: Vdd)
3961 prefix for not-connected nets (default: _NC)
3964 set the specified module as design top module
3967 \section{write
\_verilog -- write design to Verilog file
}
3968 \label{cmd:write_verilog
}
3969 \begin{lstlisting
}[numbers=left,frame=single
]
3970 write_verilog
[options
] [filename
]
3972 Write the current design to a Verilog file.
3975 without this option all internal object names (the ones with a dollar
3976 instead of a backslash prefix) are changed to short names in the
3977 format '_<number>_'.
3980 with this option no attributes are included in the output
3983 with this option attributes are included as comments in the output
3986 without this option all internal cells are converted to Verilog
3990 usually modules with the 'blackbox' attribute are ignored. with
3991 this option set only the modules with the 'blackbox' attribute
3992 are written to the output file.
3995 only write selected modules. modules must be selected entirely or
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