1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command name instead of "yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interprated as the command string to be passed to ABC. the
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
}
28 for -liberty with -constr:
29 strash; scorr; ifraig; retime
{D
}; strash; dch -f; map
{D
};
30 buffer; upsize
{D
}; dnsize
{D
}; stime -p
33 strash; scorr; ifraig; retime; strash; dch -f; if
36 strash; scorr; ifraig; retime; strash; dch -f; map
39 use different default scripts that are slightly faster (at the cost
42 for -liberty without -constr:
45 for -liberty with -constr:
46 retime
{D
}; map
{D
}; buffer; upsize
{D
}; dnsize
{D
}; stime -p
55 generate netlists for the specified cell library (using the liberty
59 pass this file with timing constraints to ABC. use with -liberty.
61 a constr file contains two lines:
62 set_driving_cell <cell_name>
63 set_load <floating_point_number>
65 the set_driving_cell statement defines which cell type is assumed to
66 drive the primary inputs and the set_load statement sets the load in
67 femtofarads for each primary output.
70 set delay target. the string
{D
} in the default scripts above is
71 replaced by this option when used, and an empty string otherwise.
74 generate netlist using luts of (max) the specified width.
77 generate netlist using luts of (max) the specified width <w2>. All
78 luts with width <= <w1> have constant cost. for luts larger than <w1>
79 the area cost doubles with each additional input bit. the delay cost
80 is still constant for all lut widths.
83 also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
84 clock domains are automatically partitioned in clock domains and each
85 domain is passed through ABC independently.
87 -clk
[!
]<clock-signal-name>
[,
[!
]<enable-signal-name>
]
88 use only the specified clock domain. this is like -dff, but only FF
89 cells that belong to the specified clock domain are used.
92 set the "keep" attribute on flip-flop output wires. (and thus preserve
93 them, for example for equivialence checking.)
96 when this option is used, the temporary files created by this pass
97 are not removed. this is useful for debugging.
100 print the temp dir name in log. usually this is suppressed so that the
101 command output is identical across runs.
104 set a 'abcgroup' attribute on all objects created by ABC. The value of
105 this attribute is a unique integer for each ABC process started. This
106 is useful for debugging the partitioning of clock domains.
108 When neither -liberty nor -lut is used, the Yosys standard cell library is
109 loaded into ABC before the ABC script is executed.
111 This pass does not operate on modules with unprocessed processes in it.
112 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
114 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
117 \section{add -- add objects to the design
}
119 \begin{lstlisting
}[numbers=left,frame=single
]
120 add <command>
[selection
]
122 This command adds objects to the design. It operates on all fully selected
123 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
126 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
128 Add a wire (input, inout, output port) with the given name and width. The
129 command will fail if the object exists already and has different properties
130 than the object to be created.
133 add -global_input <name> <width>
[selection
]
135 Like 'add -input', but also connect the signal between instances of the
139 \section{alumacc -- extract ALU and MACC cells
}
141 \begin{lstlisting
}[numbers=left,frame=single
]
144 This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
148 \section{cd -- a shortcut for 'select -module <name>'
}
150 \begin{lstlisting
}[numbers=left,frame=single
]
153 This is just a shortcut for 'select -module <modname>'.
158 When no module with the specified name is found, but there is a cell
159 with the specified name in the current module, then this is equivialent
164 This is just a shortcut for 'select -clear'.
167 \section{clean -- remove unused cells and wires
}
169 \begin{lstlisting
}[numbers=left,frame=single
]
170 clean
[options
] [selection
]
172 This is identical to 'opt_clean', but less verbose.
174 When commands are separated using the ';;' token, this command will be executed
175 between the commands.
177 When commands are separated using the ';;;' token, this command will be executed
178 in -purge mode between the commands.
181 \section{connect -- create or remove connections
}
183 \begin{lstlisting
}[numbers=left,frame=single
]
184 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
186 Create a connection. This is equivialent to adding the statement 'assign
187 <lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing
188 drivers for <lhs-expr> are unconnected. This can be overwritten by using
192 connect
[-nomap
] -unset <expr>
194 Unconnect all existing drivers for the specified expression.
197 connect
[-nomap
] -port <cell> <port> <expr>
199 Connect the specified cell port to the specified cell port.
202 Per default signal alias names are resolved and all signal names are mapped
203 the the signal name of the primary driver. Using the -nomap option deactivates
206 The connect command operates in one module only. Either only one module must
207 be selected or an active module must be set using the 'cd' command.
209 This command does not operate on module with processes.
212 \section{connwrappers -- replace undef values with defined constants
}
213 \label{cmd:connwrappers
}
214 \begin{lstlisting
}[numbers=left,frame=single
]
215 connwrappers
[options
] [selection
]
217 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
218 in wrapper cells with a (larger) constant port size. I.e. the upper bits
219 of the wrapper outut are signed/unsigned bit extended. This command uses this
220 knowlege to rewire the inputs of the driven cells to match the output of
223 -signed <cell_type> <port_name> <width_param>
224 -unsigned <cell_type> <port_name> <width_param>
225 consider the specified signed/unsigned wrapper output
227 -port <cell_type> <port_name> <width_param> <sign_param>
228 use the specified parameter to decide if signed or unsigned
230 The options -signed, -unsigned, and -port can be specified multiple times.
233 \section{copy -- copy modules in the design
}
235 \begin{lstlisting
}[numbers=left,frame=single
]
236 copy old_name new_name
238 Copy the specified module. Note that selection patterns are not supported
242 \section{cover -- print code coverage counters
}
244 \begin{lstlisting
}[numbers=left,frame=single
]
245 cover
[options
] [pattern
]
247 Print the code coverage counters collected using the cover() macro in the Yosys
248 C++ code. This is useful to figure out what parts of Yosys are utilized by a
252 Do not print output to the normal destination (console and/or log file)
255 Write output to this file, truncate if exists.
258 Write output to this file, append if exists.
261 Write output to a newly created file in the specified directory.
263 When one or more pattern (shell wildcards) are specified, then only counters
264 matching at least one pattern are printed.
267 It is also possible to instruct Yosys to print the coverage counters on program
268 exit to a file using environment variables:
270 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
272 This will create a file (with an auto-generated name) in this
273 directory and write the coverage counters to it.
275 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
277 This will append the coverage counters to the specified file.
280 Hint: Use the following AWK command to consolidate Yosys coverage files:
282 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
283 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
286 Coverage counters are only available in Yosys for Linux.
289 \section{delete -- delete objects in the design
}
291 \begin{lstlisting
}[numbers=left,frame=single
]
294 Deletes the selected objects. This will also remove entire modules, if the
295 whole module is selected.
298 delete
{-input|-output|-port
} [selection
]
300 Does not delete any object but removes the input and/or output flag on the
301 selected wires, thus 'deleting' module ports.
304 \section{design -- save, restore and reset current design
}
306 \begin{lstlisting
}[numbers=left,frame=single
]
309 Clear the current design.
314 Save the current design under the given name.
319 Save the current design under the given name and then clear the current design.
324 Push the current design to the stack and then clear the current design.
329 Reset the current design and pop the last design from the stack.
334 Reset the current design and load the design previously saved under the given
338 design -copy-from <name>
[-as <new_mod_name>
] <selection>
340 Copy modules from the specified design into the current one. The selection is
341 evaluated in the other design.
344 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
346 Copy modules from the current design into the soecified one.
349 \section{dff2dffe -- transform \$dff cells to \$dffe cells
}
351 \begin{lstlisting
}[numbers=left,frame=single
]
354 This pass transforms $dff cells driven by a tree of multiplexers with one or
355 more feedback paths to $dffe cells. It also works on gate-level cells such as
356 $_DFF_P_, $_DFF_N_ and $_MUX_.
359 operate in the opposite direction: replace $dffe cells with combinations
360 of $dff and $mux cells. the options below are ignore in unmap mode.
362 -direct <internal_gate_type> <external_gate_type>
363 map directly to external gate type. <internal_gate_type> can
364 be any internal gate-level FF cell (except $_DFFE_??_). the
365 <external_gate_type> is the cell type name for a cell with an
366 identical interface to the <internal_gate_type>, except it
367 also has an high-active enable port 'E'.
368 Usually <external_gate_type> is an intemediate cell type
369 that is then translated to the final type using 'techmap'.
372 \section{dfflibmap -- technology mapping of flip-flops
}
373 \label{cmd:dfflibmap
}
374 \begin{lstlisting
}[numbers=left,frame=single
]
375 dfflibmap
[-prepare
] -liberty <file>
[selection
]
377 Map internal flip-flop cells to the flip-flop cells in the technology
378 library specified in the given liberty file.
380 This pass may add inverters as needed. Therefore it is recommended to
381 first run this pass and then map the logic paths to the target technology.
383 When called with -prepare, this command will convert the internal FF cells
384 to the internal cell types that best match the cells found in the given
388 \section{dump -- print parts of the design in ilang format
}
390 \begin{lstlisting
}[numbers=left,frame=single
]
391 dump
[options
] [selection
]
393 Write the selected parts of the design to the console or specified file in
397 also dump the module headers, even if only parts of a single
401 only dump the module headers if the entire module is selected
404 write to the specified file.
407 like -outfile but append instead of overwrite
410 \section{echo -- turning echoing back of commands on and off
}
412 \begin{lstlisting
}[numbers=left,frame=single
]
415 Print all commands to log before executing them.
420 Do not print all commands to log before executing them. (default)
423 \section{equiv
\_add -- add a \$equiv cell
}
424 \label{cmd:equiv_add
}
425 \begin{lstlisting
}[numbers=left,frame=single
]
426 equiv_add gold_sig gate_sig
428 This command adds an $equiv cell for the specified signals.
431 \section{equiv
\_induct -- proving \$equiv cells using temporal induction
}
432 \label{cmd:equiv_induct
}
433 \begin{lstlisting
}[numbers=left,frame=single
]
434 equiv_induct
[options
] [selection
]
436 Uses a version of temporal induction to prove $equiv cells.
438 Only selected $equiv cells are proven and only selected cells are used to
442 enable modelling of undef states
445 the max. number of time steps to be considered (default =
4)
447 This command is very effective in proving complex sequential circuits, when
448 the internal state of the circuit quickly propagates to $equiv cells.
450 However, this command uses a weak definition of 'equivalence': This command
451 proves that the two circuits will not diverge after they produce equal
452 outputs (observable points via $equiv) for at least <N> cycles (the <N>
455 Combined with simulation this is very powerful because simulation can give
456 you confidence that the circuits start out synced for at least <N> cycles
460 \section{equiv
\_make -- prepare a circuit for equivalence checking
}
461 \label{cmd:equiv_make
}
462 \begin{lstlisting
}[numbers=left,frame=single
]
463 equiv_make
[options
] gold_module gate_module equiv_module
465 This creates a module annotated with $equiv cells from two presumably
466 equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
467 to work with the created equivalent checking module.
470 Also match cells and wires with $... names.
473 Do not match cells or signals that match the names in the file.
476 Match FSM encodings using the desiption from the file.
477 See 'help fsm_recode' for details.
479 Note: The circuit created by this command is not a miter (with something like
480 a trigger output), but instead uses $equiv cells to encode the equivalence
481 checking problem. Use 'miter -equiv' if you want to create a miter circuit.
484 \section{equiv
\_miter -- extract miter from equiv circuit
}
485 \label{cmd:equiv_miter
}
486 \begin{lstlisting
}[numbers=left,frame=single
]
487 equiv_miter
[options
] miter_module
[selection
]
489 This creates a miter module for further analysis of the selected $equiv cells.
492 Create a trigger output
495 Create cmp_* outputs for individual unproven $equiv cells
498 Create a $assert cell for each unproven $equiv cell
501 Create compare logic that handles undefs correctly
504 \section{equiv
\_remove -- remove \$equiv cells
}
505 \label{cmd:equiv_remove
}
506 \begin{lstlisting
}[numbers=left,frame=single
]
507 equiv_remove
[options
] [selection
]
509 This command removes the selected $equiv cells. If neither -gold nor -gate is
510 used then only proven cells are removed.
519 \section{equiv
\_simple -- try proving simple \$equiv instances
}
520 \label{cmd:equiv_simple
}
521 \begin{lstlisting
}[numbers=left,frame=single
]
522 equiv_simple
[options
] [selection
]
524 This command tries to prove $equiv cells using a simple direct SAT approach.
530 enable modelling of undef states
533 disabling grouping of $equiv cells by output wire
536 the max. number of time steps to be considered (default =
1)
539 \section{equiv
\_status -- print status of equivalent checking module
}
540 \label{cmd:equiv_status
}
541 \begin{lstlisting
}[numbers=left,frame=single
]
542 equiv_status
[options
] [selection
]
544 This command prints status information for all selected $equiv cells.
547 produce an error if any unproven $equiv cell is found
550 \section{eval -- evaluate the circuit given an input
}
552 \begin{lstlisting
}[numbers=left,frame=single
]
553 eval
[options
] [selection
]
555 This command evaluates the value of a signal given the value of all required
558 -set <signal> <value>
559 set the specified signal to the specified value.
562 set all unspecified source signals to undef (x)
565 create a truth table using the specified input signals
568 show the value for the specified signal. if no -show option is passed
569 then all output ports of the current module are used.
572 \section{expose -- convert internal signals to module ports
}
574 \begin{lstlisting
}[numbers=left,frame=single
]
575 expose
[options
] [selection
]
577 This command exposes all selected internal signals of a module as additional
581 only consider wires that are directly driven by register cell.
584 when exposing a wire, create an input/output pair and cut the internal
585 signal path at that wire.
588 only expose those signals that are shared ammong the selected modules.
589 this is useful for preparing modules for equivialence checking.
592 also turn connections to instances of other modules to additional
593 inputs and outputs and remove the module instances.
596 turn flip-flops to sets of inputs and outputs.
599 when creating new wire/port names, the original object name is suffixed
600 with this separator (default: '.') and the port name or a type
601 designator for the exposed signal.
604 \section{extract -- find subcircuits and replace them with cells
}
606 \begin{lstlisting
}[numbers=left,frame=single
]
607 extract -map <map_file>
[options
] [selection
]
608 extract -mine <out_file>
[options
] [selection
]
610 This pass looks for subcircuits that are isomorphic to any of the modules
611 in the given map file and replaces them with instances of this modules. The
612 map file can be a verilog source file
(*.v) or an ilang file (*.il).
615 use the modules in this file as reference. This option can be used
619 use the modules in this in-memory design as reference. This option can
620 be used multiple times.
623 print debug output while analyzing
626 also find instances with constant drivers. this may be much
627 slower than the normal operation.
630 normally builtin port swapping rules for internal cells are used per
631 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
632 when this option is used.
634 -compat <needle_type> <haystack_type>
635 Per default, the cells in the map file (needle) must have the
636 type as the cells in the active design (haystack). This option
637 can be used to register additional pairs of types that should
638 match. This option can be used multiple times.
640 -swap <needle_type> <port1>,<port2>[,...]
641 Register a set of swapable ports for a needle cell type.
642 This option can be used multiple times.
644 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
645 Register a valid permutation of swapable ports for a needle
646 cell type. This option can be used multiple times.
648 -cell_attr <attribute_name>
649 Attributes on cells with the given name must match.
651 -wire_attr <attribute_name>
652 Attributes on wires with the given name must match.
655 Do not use parameters when matching cells.
657 -ignore_param <cell_type> <parameter_name>
658 Do not use this parameter when matching cells.
660 This pass does not operate on modules with uprocessed processes in it.
661 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
663 This pass can also be used for mining for frequent subcircuits. In this mode
664 the following options are to be used instead of the -map option.
667 mine for frequent subcircuits and write them to the given ilang file
669 -mine_cells_span <min> <max>
670 only mine for subcircuits with the specified number of cells
674 only mine for subcircuits with at least the specified number of matches
677 -mine_limit_matches_per_module <num>
678 when calculating the number of matches for a subcircuit, don't count
679 more than the specified number of matches per module
681 -mine_max_fanout <num>
682 don't consider internal signals with more than <num> connections
684 The modules in the map file may have the attribute 'extract_order' set to an
685 integer value. Then this value is used to determine the order in which the pass
686 tries to map the modules to the design (ascending, default value is 0).
688 See 'help techmap' for a pass that does the opposite thing.
691 \section{flatten -- flatten design}
693 \begin{lstlisting}[numbers=left,frame=single]
696 This pass flattens the design by replacing cells by their implementation. This
697 pass is very simmilar to the 'techmap' pass. The only difference is that this
698 pass is using the current design as mapping library.
701 \section{freduce -- perform functional reduction}
703 \begin{lstlisting}[numbers=left,frame=single]
704 freduce [options] [selection]
706 This pass performs functional reduction in the circuit. I.e. if two nodes are
707 equivialent, they are merged to one node and one of the redundant drivers is
708 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
711 enable verbose or very verbose output
714 enable explicit handling of inverted signals
717 stop after <n> reduction operations. this is mostly used for
718 debugging the freduce command itself.
721 dump the design to <prefix>_<module>_<num>.il after each reduction
722 operation. this is mostly used for debugging the freduce command.
724 This pass is undef-aware, i.e. it considers don't-care values for detecting
727 All selected wires are considered for rewiring. The selected cells cover the
728 circuit that is analyzed.
731 \section{fsm -- extract and optimize finite state machines}
733 \begin{lstlisting}[numbers=left,frame=single]
734 fsm [options] [selection]
736 This pass calls all the other fsm_* passes in a useful order. This performs
737 FSM extraction and optimiziation. It also calls opt_clean as needed:
739 fsm_detect unless got option -nodetect
746 fsm_expand if got option -expand
747 opt_clean if got option -expand
748 fsm_opt if got option -expand
750 fsm_recode unless got option -norecode
754 fsm_export if got option -export
755 fsm_map unless got option -nomap
759 -expand, -norecode, -export, -nomap
760 enable or disable passes as indicated above
763 -fm_set_fsm_file file
765 passed through to fsm_recode pass
768 \section{fsm\_detect -- finding FSMs in design}
769 \label{cmd:fsm_detect}
770 \begin{lstlisting}[numbers=left,frame=single]
771 fsm_detect [selection]
773 This pass detects finite state machines by identifying the state signal.
774 The state signal is then marked by setting the attribute 'fsm_encoding'
775 on the state signal to "auto".
777 Existing 'fsm_encoding' attributes are not changed by this pass.
779 Signals can be protected from being detected by this pass by setting the
780 'fsm_encoding' attribute to "none".
783 \section{fsm\_expand -- expand FSM cells by merging logic into it}
784 \label{cmd:fsm_expand}
785 \begin{lstlisting}[numbers=left,frame=single]
786 fsm_expand [selection]
788 The fsm_extract pass is conservative about the cells that belong to a finite
789 state machine. This pass can be used to merge additional auxiliary gates into
790 the finate state machine.
793 \section{fsm\_export -- exporting FSMs to KISS2 files}
794 \label{cmd:fsm_export}
795 \begin{lstlisting}[numbers=left,frame=single]
796 fsm_export [-noauto] [-o filename] [-origenc] [selection]
798 This pass creates a KISS2 file for every selected FSM. For FSMs with the
799 'fsm_export' attribute set, the attribute value is used as filename, otherwise
800 the module and cell name is used as filename. If the parameter '-o' is given,
801 the first exported FSM is written to the specified filename. This overwrites
802 the setting as specified with the 'fsm_export' attribute. All other FSMs are
803 exported to the default name as mentioned above.
806 only export FSMs that have the 'fsm_export' attribute set
809 filename of the first exported FSM
812 use binary state encoding as state names instead of s0, s1, ...
815 \section{fsm\_extract -- extracting FSMs in design}
816 \label{cmd:fsm_extract}
817 \begin{lstlisting}[numbers=left,frame=single]
818 fsm_extract [selection]
820 This pass operates on all signals marked as FSM state signals using the
821 'fsm_encoding' attribute. It consumes the logic that creates the state signal
822 and uses the state signal to generate control signal and replaces it with an
825 The generated FSM cell still generates the original state signal with its
826 original encoding. The 'fsm_opt' pass can be used in combination with the
827 'opt_clean' pass to eliminate this signal.
830 \section{fsm\_info -- print information on finite state machines}
832 \begin{lstlisting}[numbers=left,frame=single]
835 This pass dumps all internal information on FSM cells. It can be useful for
836 analyzing the synthesis process and is called automatically by the 'fsm'
837 pass so that this information is included in the synthesis log file.
840 \section{fsm\_map -- mapping FSMs to basic logic}
842 \begin{lstlisting}[numbers=left,frame=single]
845 This pass translates FSM cells to flip-flops and logic.
848 \section{fsm\_opt -- optimize finite state machines}
850 \begin{lstlisting}[numbers=left,frame=single]
853 This pass optimizes FSM cells. It detects which output signals are actually
854 not used and removes them from the FSM. This pass is usually used in
855 combination with the 'opt_clean' pass (see also 'help fsm').
858 \section{fsm\_recode -- recoding finite state machines}
859 \label{cmd:fsm_recode}
860 \begin{lstlisting}[numbers=left,frame=single]
861 fsm_recode [options] [selection]
863 This pass reassign the state encodings for FSM cells. At the moment only
864 one-hot encoding and binary encoding is supported.
866 specify the encoding scheme used for FSMs without the
867 'fsm_encoding' attribute or with the attribute set to `auto'.
869 -fm_set_fsm_file <file>
870 generate a file containing the mapping from old to new FSM encoding
871 in form of Synopsys Formality set_fsm_* commands.
874 write the mappings from old to new FSM encoding to a file in the
877 .fsm <module_name> <state_signal>
878 .map <old_bitpattern> <new_bitpattern>
881 \section{help -- display help messages}
883 \begin{lstlisting}[numbers=left,frame=single]
884 help ............. list all commands
885 help <command> ... print help message for given command
886 help -all ........ print complete command reference
889 \section{hierarchy -- check, expand and clean up design hierarchy}
890 \label{cmd:hierarchy}
891 \begin{lstlisting}[numbers=left,frame=single]
892 hierarchy [-check] [-top <module>]
893 hierarchy -generate <cell-types> <port-decls>
895 In parametric designs, a module might exists in several variations with
896 different parameter values. This pass looks at all modules in the current
897 design an re-runs the language frontends for the parametric modules as
901 also check the design hierarchy. this generates an error when
902 an unknown module is used as cell type.
905 by default the hierarchy command will not remove library (blackbox)
906 module. use this options to also remove unused blackbox modules.
909 search for files named <module_name>.v in the specified directory
910 for unknown modules and automatically run read_verilog for each
914 per default this pass also converts positional arguments in cells
915 to arguments using port names. this option disables this behavior.
918 per default this pass sets the "keep" attribute on all modules
919 that directly or indirectly contain one or more $assert cells. this
920 option disables this behavior.
923 use the specified top module to built a design hierarchy. modules
924 outside this tree (unused modules) are removed.
926 when the -top option is used, the 'top' attribute will be set on the
927 specified top module. otherwise a module with the 'top' attribute set
928 will implicitly be used as top module, if such a module exists.
930 In -generate mode this pass generates blackbox modules for the given cell
931 types (wildcards supported). For this the design is searched for cells that
932 match the given types and then the given port declarations are used to
933 determine the direction of the ports. The syntax for a port declaration is:
935 {i|o|io}[@<num>]:<portname>
937 Input ports are specified with the 'i' prefix, output ports with the 'o'
938 prefix and inout ports with the 'io' prefix. The optional <num> specifies
939 the position of the port in the parameter list (needed when instanciated
940 using positional arguments). When <num> is not specified, the <portname> can
941 also contain wildcard characters.
943 This pass ignores the current selection and always operates on all modules
944 in the current design.
947 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers}
949 \begin{lstlisting}[numbers=left,frame=single]
950 hilomap [options] [selection]
952 Map constants to 'tielo' and 'tiehi' driver cells.
954 -hicell <celltype> <portname>
955 Replace constant hi bits with this cell.
957 -locell <celltype> <portname>
958 Replace constant lo bits with this cell.
961 Create only one hi/lo cell and connect all constant bits
962 to that cell. Per default a separate cell is created for
966 \section{history -- show last interactive commands}
968 \begin{lstlisting}[numbers=left,frame=single]
971 This command prints all commands in the shell history buffer. This are
972 all commands executed in an interactive session, but not the commands
973 from executed scripts.
976 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
978 \begin{lstlisting}[numbers=left,frame=single]
979 iopadmap [options] [selection]
981 Map module inputs/outputs to PAD cells from a library. This pass
982 can only map to very simple PAD cells. Use 'techmap' to further map
983 the resulting cells to more sophisticated PAD cells.
985 -inpad <celltype> <portname>[:<portname>]
986 Map module input ports to the given cell type with
987 the given port name. if a 2nd portname is given, the
988 signal is passed through the pad call, using the 2nd
991 -outpad <celltype> <portname>[:<portname>]
992 -inoutpad <celltype> <portname>[:<portname>]
993 Similar to -inpad, but for output and inout ports.
995 -widthparam <param_name>
996 Use the specified parameter name to set the port width.
998 -nameparam <param_name>
999 Use the specified parameter to set the port name.
1002 create individual bit-wide buffers even for ports that
1003 are wider. (the default behavior is to create word-wide
1004 buffers using -widthparam to set the word size on the cell.)
1007 \section{log -- print text and log files}
1009 \begin{lstlisting}[numbers=left,frame=single]
1012 Print the given string to the screen and/or the log file. This is useful for TCL
1013 scripts, because the TCL command "puts" only goes to stdout but not to
1017 Print the output to stdout too. This is useful when all Yosys is executed
1018 with a script and the -q (quiet operation) argument to notify the user.
1021 Print the output to stderr too.
1024 Don't use the internal log() command. Use either -stdout or -stderr,
1025 otherwise no output will be generated at all.
1028 do not append a newline
1031 \section{ls -- list modules or objects in modules}
1033 \begin{lstlisting}[numbers=left,frame=single]
1036 When no active module is selected, this prints a list of modules.
1038 When an active module is selected, this prints a list of objects in the module.
1041 \section{maccmap -- mapping macc cells}
1043 \begin{lstlisting}[numbers=left,frame=single]
1044 maccmap [-unmap] [selection]
1046 This pass maps $macc cells to yosys gate primitives. When the -unmap option is
1047 used then the $macc cell is mapped to $and, $sub, etc. cells instead.
1050 \section{memory -- translate memories to basic cells}
1052 \begin{lstlisting}[numbers=left,frame=single]
1053 memory [-nomap] [-bram <bram_rules>] [selection]
1055 This pass calls all the other memory_* passes in a useful order:
1062 memory_bram -rules <bram_rules> (when called with -bram)
1063 memory_map (skipped if called with -nomap)
1065 This converts memories to word-wide DFFs and address decoders
1066 or multiport memory blocks if called with the -nomap option.
1069 \section{memory\_bram -- map memories to block rams}
1070 \label{cmd:memory_bram}
1071 \begin{lstlisting}[numbers=left,frame=single]
1072 memory_bram -rules <rule_file> [selection]
1074 This pass converts the multi-port $mem memory cells into block ram instances.
1075 The given rules file describes the available resources and how they should be
1078 The rules file contains a set of block ram description and a sequence of match
1079 rules. A block ram description looks like this:
1081 bram RAMB1024X32 # name of BRAM cell
1082 abits 10 # number of address bits
1083 dbits 32 # number of data bits
1084 groups 2 # number of port groups
1085 ports 1 1 # number of ports in each group
1086 wrmode 1 0 # set to '1' if this groups is write ports
1087 enable 4 0 # number of enable bits (for write ports)
1088 transp 0 2 # transparatent (for read ports)
1089 clocks 1 2 # clock configuration
1090 clkpol 2 2 # clock polarity configuration
1093 For the option 'transp' the value 0 means non-transparent, 1 means transparent
1094 and a value greater than 1 means configurable. All groups with the same
1095 value greater than 1 share the same configuration bit.
1097 For the option 'clocks' the value 0 means non-clocked, and a value greater
1098 than 0 means clocked. All groups with the same value share the same clock
1101 For the option 'clkpol' the value 0 means negative edge, 1 means positive edge
1102 and a value greater than 1 means configurable. All groups with the same value
1103 greater than 1 share the same configuration bit.
1105 Using the same bram name in different bram blocks will create different variants
1106 of the bram. Verilog configration parameters for the bram are created as needed.
1108 It is also possible to create variants by repeating statements in the bram block
1109 and appending '@<label>' to the individual statements.
1111 A match rule looks like this:
1114 max waste 16384 # only use this bram if <= 16k ram bits are unused
1115 min efficiency 80 # only use this bram if efficiency is at least 80%
1118 It is possible to match against the following values with min/max rules:
1120 words ........ number of words in memory in design
1121 abits ........ number of address bits on memory in design
1122 dbits ........ number of data bits on memory in design
1123 wports ....... number of write ports on memory in design
1124 rports ....... number of read ports on memory in design
1125 ports ........ number of ports on memory in design
1126 bits ......... number of bits in memory in design
1127 dups .......... number of duplications for more read ports
1129 awaste ....... number of unused address slots for this match
1130 dwaste ....... number of unused data bits for this match
1131 bwaste ....... number of unused bram bits for this match
1132 waste ........ total number of unused bram bits (bwaste*dups)
1133 efficiency ... total percentage of used and non-duplicated bits
1135 acells ....... number of cells in 'address-direction'
1136 dcells ....... number of cells in 'data-direction'
1137 cells ........ total number of cells (acells*dcells*dups)
1139 The interface for the created bram instances is dervived from the bram
1140 description. Use 'techmap' to convert the created bram instances into
1141 instances of the actual bram cells of your target architecture.
1143 A match containing the command 'or_next_if_better' is only used if it
1144 has a higher efficiency than the next match (and the one after that if
1145 the next also has 'or_next_if_better' set, and so forth).
1147 A match containing the command 'make_transp' will add external circuitry
1148 to simulate 'transparent read', if necessary.
1150 A match containing the command 'shuffle_enable A' will re-organize
1151 the data bits to accommodate the enable pattern of port A.
1154 \section{memory\_collect -- creating multi-port memory cells}
1155 \label{cmd:memory_collect}
1156 \begin{lstlisting}[numbers=left,frame=single]
1157 memory_collect [selection]
1159 This pass collects memories and memory ports and creates generic multiport
1163 \section{memory\_dff -- merge input/output DFFs into memories}
1164 \label{cmd:memory_dff}
1165 \begin{lstlisting}[numbers=left,frame=single]
1166 memory_dff [options] [selection]
1168 This pass detects DFFs at memory ports and merges them into the memory port.
1169 I.e. it consumes an asynchronous memory port and the flip-flops at its
1170 interface and yields a synchronous memory port.
1173 do not merge registers on read ports
1176 \section{memory\_map -- translate multiport memories to basic cells}
1177 \label{cmd:memory_map}
1178 \begin{lstlisting}[numbers=left,frame=single]
1179 memory_map [selection]
1181 This pass converts multiport memory cells as generated by the memory_collect
1182 pass to word-wide DFFs and address decoders.
1185 \section{memory\_share -- consolidate memory ports}
1186 \label{cmd:memory_share}
1187 \begin{lstlisting}[numbers=left,frame=single]
1188 memory_share [selection]
1190 This pass merges share-able memory ports into single memory ports.
1192 The following methods are used to consolidate the number of memory ports:
1194 - When write ports are connected to async read ports accessing the same
1195 address, then this feedback path is converted to a write port with
1196 byte/part enable signals.
1198 - When multiple write ports access the same address then this is converted
1199 to a single write port with a more complex data and/or enable logic path.
1201 - When multiple write ports are never accessed at the same time (a SAT
1202 solver is used to determine this), then the ports are merged into a single
1205 Note that in addition to the algorithms implemented in this pass, the $memrd
1206 and $memwr cells are also subject to generic resource sharing passes (and other
1207 optimizations) such as opt_share.
1210 \section{memory\_unpack -- unpack multi-port memory cells}
1211 \label{cmd:memory_unpack}
1212 \begin{lstlisting}[numbers=left,frame=single]
1213 memory_unpack [selection]
1215 This pass converts the multi-port $mem memory cells into individual $memrd and
1216 $memwr cells. It is the counterpart to the memory_collect pass.
1219 \section{miter -- automatically create a miter circuit}
1221 \begin{lstlisting}[numbers=left,frame=single]
1222 miter -equiv [options] gold_name gate_name miter_name
1224 Creates a miter circuit for equivialence checking. The gold- and gate- modules
1225 must have the same interfaces. The miter circuit will have all inputs of the
1226 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
1227 output that goes high if an output mismatch between the two source modules is
1231 a undef (x) bit in the gold module output will match any value in
1232 the gate module output.
1235 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
1236 on the miter circuit.
1239 also create a cmp_* output for each gold/gate output pair.
1242 also create an 'assert' cell that checks if trigger is always low.
1245 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
1248 \section{opt -- perform simple optimizations}
1250 \begin{lstlisting}[numbers=left,frame=single]
1251 opt [options] [selection]
1253 This pass calls all the other opt_* passes in a useful order. This performs
1254 a series of trivial optimizations and cleanups. This pass executes the other
1255 passes in the following order:
1257 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1262 opt_reduce [-fine] [-full]
1266 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1267 while <changed design>
1269 When called with -fast the following script is used instead:
1272 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1276 while <changed design in opt_rmdff>
1278 Note: Options in square brackets (such as [-keepdc]) are passed through to
1279 the opt_* commands when given to 'opt'.
1282 \section{opt\_clean -- remove unused cells and wires}
1283 \label{cmd:opt_clean}
1284 \begin{lstlisting}[numbers=left,frame=single]
1285 opt_clean [options] [selection]
1287 This pass identifies wires and cells that are unused and removes them. Other
1288 passes often remove cells but leave the wires in the design or reconnect the
1289 wires but leave the old cells in the design. This pass can be used to clean up
1290 after the passes that do the actual work.
1292 This pass only operates on completely selected modules without processes.
1295 also remove internal nets if they have a public name
1298 \section{opt\_const -- perform const folding}
1299 \label{cmd:opt_const}
1300 \begin{lstlisting}[numbers=left,frame=single]
1301 opt_const [options] [selection]
1303 This pass performs const folding on internal cell types with constant inputs.
1306 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
1309 replace $mux cells with inverters or buffers when possible
1312 replace undriven nets with undef (x) constants
1315 perform fine-grain optimizations
1318 alias for -mux_undef -mux_bool -undriven -fine
1321 some optimizations change the behavior of the circuit with respect to
1322 don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
1323 all result bits to be set to x. this behavior changes when 'a+0' is
1324 replaced by 'a'. the -keepdc option disables all such optimizations.
1327 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
1328 \label{cmd:opt_muxtree}
1329 \begin{lstlisting}[numbers=left,frame=single]
1330 opt_muxtree [selection]
1332 This pass analyzes the control signals for the multiplexer trees in the design
1333 and identifies inputs that can never be active. It then removes this dead
1334 branches from the multiplexer trees.
1336 This pass only operates on completely selected modules without processes.
1339 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
1340 \label{cmd:opt_reduce}
1341 \begin{lstlisting}[numbers=left,frame=single]
1342 opt_reduce [options] [selection]
1344 This pass performs two interlinked optimizations:
1346 1. it consolidates trees of large AND gates or OR gates and eliminates
1349 2. it identifies duplicated inputs to MUXes and replaces them with a single
1350 input with the original control signals OR'ed together.
1353 perform fine-grain optimizations
1359 \section{opt\_rmdff -- remove DFFs with constant inputs}
1360 \label{cmd:opt_rmdff}
1361 \begin{lstlisting}[numbers=left,frame=single]
1362 opt_rmdff [selection]
1364 This pass identifies flip-flops with constant inputs and replaces them with
1368 \section{opt\_share -- consolidate identical cells}
1369 \label{cmd:opt_share}
1370 \begin{lstlisting}[numbers=left,frame=single]
1371 opt_share [-nomux] [selection]
1373 This pass identifies cells with identical type and input signals. Such cells
1374 are then merged to one cell.
1377 Do not merge MUX cells.
1380 \section{plugin -- load and list loaded plugins}
1382 \begin{lstlisting}[numbers=left,frame=single]
1385 Load and list loaded plugins.
1387 -i <plugin_filename>
1388 Load (install) the specified plugin.
1391 Register the specified alias name for the loaded plugin
1397 \section{proc -- translate processes to netlists}
1399 \begin{lstlisting}[numbers=left,frame=single]
1400 proc [options] [selection]
1402 This pass calls all the other proc_* passes in the most common order.
1412 This replaces the processes in the design with multiplexers and flip-flops.
1414 The following options are supported:
1416 -global_arst [!]<netname>
1417 This option is passed through to proc_arst.
1420 \section{proc\_arst -- detect asynchronous resets}
1421 \label{cmd:proc_arst}
1422 \begin{lstlisting}[numbers=left,frame=single]
1423 proc_arst [-global_arst [!]<netname>] [selection]
1425 This pass identifies asynchronous resets in the processes and converts them
1426 to a different internal representation that is suitable for generating
1427 flip-flop cells with asynchronous resets.
1429 -global_arst [!]<netname>
1430 In modules that have a net with the given name, use this net as async
1431 reset for registers that have been assign initial values in their
1432 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
1433 active low reset signals. Note: the frontend stores the default value
1434 in the 'init' attribute on the net.
1437 \section{proc\_clean -- remove empty parts of processes}
1438 \label{cmd:proc_clean}
1439 \begin{lstlisting}[numbers=left,frame=single]
1440 proc_clean [selection]
1442 This pass removes empty parts of processes and ultimately removes a process
1443 if it contains only empty structures.
1446 \section{proc\_dff -- extract flip-flops from processes}
1447 \label{cmd:proc_dff}
1448 \begin{lstlisting}[numbers=left,frame=single]
1449 proc_dff [selection]
1451 This pass identifies flip-flops in the processes and converts them to
1452 d-type flip-flop cells.
1455 \section{proc\_init -- convert initial block to init attributes}
1456 \label{cmd:proc_init}
1457 \begin{lstlisting}[numbers=left,frame=single]
1458 proc_init [selection]
1460 This pass extracts the 'init' actions from processes (generated from verilog
1461 'initial' blocks) and sets the initial value to the 'init' attribute on the
1465 \section{proc\_mux -- convert decision trees to multiplexers}
1466 \label{cmd:proc_mux}
1467 \begin{lstlisting}[numbers=left,frame=single]
1468 proc_mux [selection]
1470 This pass converts the decision trees in processes (originating from if-else
1471 and case statements) to trees of multiplexer cells.
1474 \section{proc\_rmdead -- eliminate dead trees in decision trees}
1475 \label{cmd:proc_rmdead}
1476 \begin{lstlisting}[numbers=left,frame=single]
1477 proc_rmdead [selection]
1479 This pass identifies unreachable branches in decision trees and removes them.
1482 \section{read\_ilang -- read modules from ilang file}
1483 \label{cmd:read_ilang}
1484 \begin{lstlisting}[numbers=left,frame=single]
1485 read_ilang [filename]
1487 Load modules from an ilang file to the current design. (ilang is a text
1488 representation of a design in yosys's internal format.)
1491 \section{read\_liberty -- read cells from liberty file}
1492 \label{cmd:read_liberty}
1493 \begin{lstlisting}[numbers=left,frame=single]
1494 read_liberty [filename]
1496 Read cells from liberty file as modules into current design.
1499 only create empty blackbox modules
1502 ignore re-definitions of modules. (the default behavior is to
1503 create an error message.)
1506 ignore cells with missing function specification of outputs
1509 ignore cells with a missing or invalid direction
1510 specification on a pin
1512 -setattr <attribute_name>
1513 set the specified attribute (to the value 1) on all loaded modules
1516 \section{read\_verilog -- read modules from verilog file}
1517 \label{cmd:read_verilog}
1518 \begin{lstlisting}[numbers=left,frame=single]
1519 read_verilog [options] [filename]
1521 Load modules from a verilog file to the current design. A large subset of
1522 Verilog-2005 is supported.
1525 enable support for SystemVerilog features. (only a small subset
1526 of SystemVerilog is supported)
1529 dump abstract syntax tree (before simplification)
1532 dump abstract syntax tree (after simplification)
1535 dump ast as verilog code (after simplification)
1538 enable parser debug output
1541 usually latches are synthesized into logic loops
1542 this option prohibits this and sets the output to 'x'
1543 in what would be the latches hold condition
1545 this behavior can also be achieved by setting the
1546 'nolatches' attribute on the respective module or
1550 under certain conditions memories are converted to registers
1551 early during simplification to ensure correct handling of
1552 complex corner cases. this option disables this behavior.
1554 this can also be achieved by setting the 'nomem2reg'
1555 attribute on the respective module or register.
1558 always convert memories to registers. this can also be
1559 achieved by setting the 'mem2reg' attribute on the respective
1563 dump verilog code after pre-processor
1566 do not run the pre-processor
1569 only create empty blackbox modules
1572 don't perform basic optimizations (such as const folding) in the
1573 high-level front-end.
1576 interpret cell types starting with '$' as internal cell types
1579 ignore re-definitions of modules. (the default behavior is to
1580 create an error message.)
1583 only read the abstract syntax tree and defer actual compilation
1584 to a later 'hierarchy' command. Useful in cases where the default
1585 parameters of modules yield invalid or not synthesizable code.
1587 -setattr <attribute_name>
1588 set the specified attribute (to the value 1) on all loaded modules
1591 define the preprocessor symbol 'name' and set its optional value
1595 add 'dir' to the directories which are used when searching include
1598 The command 'verilog_defaults' can be used to register default options for
1599 subsequent calls to 'read_verilog'.
1601 Note that the Verilog frontend does a pretty good job of processing valid
1602 verilog input, but has not very good error reporting. It generally is
1603 recommended to use a simulator (for example icarus verilog) for checking
1604 the syntax of the code, rather than to rely on read_verilog for that.
1607 \section{rename -- rename object in the design}
1609 \begin{lstlisting}[numbers=left,frame=single]
1610 rename old_name new_name
1612 Rename the specified object. Note that selection patterns are not supported
1616 rename -enumerate [-pattern <pattern>] [selection]
1618 Assign short auto-generated names to all selected wires and cells with private
1619 names. The -pattern option can be used to set the pattern for the new names.
1620 The character % in the pattern is replaced with a integer number. The default
1623 rename -hide [selection]
1625 Assign private names (the ones with $-prefix) to all selected wires and cells
1626 with public names. This ignores all selected ports.
1629 \section{sat -- solve a SAT problem in the circuit}
1631 \begin{lstlisting}[numbers=left,frame=single]
1632 sat [options] [selection]
1634 This command solves a SAT problem defined over the currently selected circuit
1635 and additional constraints passed as parameters.
1638 show all solutions to the problem (this can grow exponentially, use
1639 -max <N> instead to get <N> solutions)
1642 like -all, but limit number of solutions to <N>
1645 enable modeling of undef value (aka 'x-bits')
1646 this option is implied by -set-def, -set-undef et. cetera
1649 maximize the number of undef bits in solutions, giving a better
1650 picture of which input bits are actually vital to the solution.
1652 -set <signal> <value>
1653 set the specified signal to the specified value.
1656 add a constraint that all bits of the given signal must be defined
1658 -set-any-undef <signal>
1659 add a constraint that at least one bit of the given signal is undefined
1661 -set-all-undef <signal>
1662 add a constraint that all bits of the given signal are undefined
1665 add -set-def constraints for all module inputs
1668 show the model for the specified signal. if no -show option is
1669 passed then a set of signals to be shown is automatically selected.
1671 -show-inputs, -show-outputs, -show-ports
1672 add all module (input/output) ports to the list of shown signals
1675 ignore all solutions that involve a division by zero
1677 -ignore_unknown_cells
1678 ignore all cells that can not be matched to a SAT model
1680 The following options can be used to set up a sequential problem:
1683 set up a sequential problem with <N> time steps. The steps will
1684 be numbered from 1 to N.
1686 -set-at <N> <signal> <value>
1687 -unset-at <N> <signal>
1688 set or unset the specified signal to the specified value in the
1689 given timestep. this has priority over a -set for the same signal.
1691 -set-def-at <N> <signal>
1692 -set-any-undef-at <N> <signal>
1693 -set-all-undef-at <N> <signal>
1694 add undef constraints in the given timestep.
1696 -set-init <signal> <value>
1697 set the initial value for the register driving the signal to the value
1700 set all initial states (not set using -set-init) to undef
1703 do not force a value for the initial state but do not allow undef
1706 set all initial states (not set using -set-init) to zero
1708 -dump_vcd <vcd-file-name>
1709 dump SAT model (counter example in proof) to VCD file
1711 -dump_cnf <cnf-file-name>
1712 dump CNF of SAT problem (in DIMACS format). in temporal induction
1713 proofs this is the CNF of the first induction step.
1715 The following additional options can be used to set up a proof. If also -seq
1716 is passed, a temporal induction proof is performed.
1719 Perform a temporal induction proof. In a temporalinduction proof it is
1720 proven that the condition holds forever after the number of time steps
1721 specified using -seq.
1724 Perform a temporal induction proof. Assume an initial state with all
1725 registers set to defined values for the induction step.
1727 -prove <signal> <value>
1728 Attempt to proof that <signal> is always <value>.
1730 -prove-x <signal> <value>
1731 Like -prove, but an undef (x) bit in the lhs matches any value on
1732 the right hand side. Useful for equivialence checking.
1735 Prove that all asserts in the design hold.
1738 Do not enforce the prove-condition for the first <N> time steps.
1741 Set a maximum length for the induction.
1744 Set initial length for the induction.
1747 Maximum number of seconds a single SAT instance may take.
1750 Return an error and stop the synthesis script if the proof fails.
1753 Like -verify but do not return an error for timeouts.
1756 Return an error and stop the synthesis script if the proof succeeds.
1759 Like -falsify but do not return an error for timeouts.
1762 \section{scatter -- add additional intermediate nets}
1764 \begin{lstlisting}[numbers=left,frame=single]
1767 This command adds additional intermediate nets on all cell ports. This is used
1768 for testing the correct use of the SigMap helper in passes. If you don't know
1769 what this means: don't worry -- you only need this pass when testing your own
1770 extensions to Yosys.
1772 Use the opt_clean command to get rid of the additional nets.
1775 \section{scc -- detect strongly connected components (logic loops)}
1777 \begin{lstlisting}[numbers=left,frame=single]
1778 scc [options] [selection]
1780 This command identifies strongly connected components (aka logic loops) in the
1784 limit to loops not longer than the specified number of cells. This can
1785 e.g. be useful in identifying local loops in a module that turns out
1786 to be one gigantic SCC.
1789 Usually this command only considers internal non-memory cells. With
1790 this option set, all cells are considered. For unknown cells all ports
1791 are assumed to be bidirectional 'inout' ports.
1793 -set_attr <name> <value>
1794 -set_cell_attr <name> <value>
1795 -set_wire_attr <name> <value>
1796 set the specified attribute on all cells and/or wires that are part of
1797 a logic loop. the special token {} in the value is replaced with a
1798 unique identifier for the logic loop.
1801 replace the current selection with a selection of all cells and wires
1802 that are part of a found logic loop
1805 \section{script -- execute commands from script file}
1807 \begin{lstlisting}[numbers=left,frame=single]
1808 script <filename> [<from_label>:<to_label>]
1810 This command executes the yosys commands in the specified file.
1812 The 2nd argument can be used to only execute the section of the
1813 file between the specified labels. An empty from label is synonymous
1814 for the beginning of the file and an empty to label is synonymous
1815 for the end of the file.
1817 If only one label is specified (without ':') then only the block
1818 marked with that label (until the next label) is executed.
1821 \section{select -- modify and view the list of selected objects}
1823 \begin{lstlisting}[numbers=left,frame=single]
1824 select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
1825 select [ -assert-none | -assert-any ] {-read <filename> | <selection>}
1826 select [ -list | -write <filename> | -count | -clear ]
1827 select -module <modname>
1829 Most commands use the list of currently selected objects to determine which part
1830 of the design to operate on. This command can be used to modify and view this
1831 list of selected objects.
1833 Note that many commands support an optional [selection] argument that can be
1834 used to override the global selection for the command. The syntax of this
1835 optional argument is identical to the syntax of the <selection> argument
1839 add or remove the given objects to the current selection.
1840 without this options the current selection is replaced.
1843 do not modify the current selection. instead save the new selection
1844 under the given name (see @<name> below). to save the current selection,
1845 use "select -set <name> %"
1848 do not modify the current selection. instead assert that the given
1849 selection is empty. i.e. produce an error if any object matching the
1853 do not modify the current selection. instead assert that the given
1854 selection is non-empty. i.e. produce an error if no object matching
1855 the selection is found.
1858 do not modify the current selection. instead assert that the given
1859 selection contains exactly N objects.
1862 list all objects in the current selection
1865 like -list but write the output to the specified file
1868 read the specified file (written by -write)
1871 count all objects in the current selection
1874 clear the current selection. this effectively selects the whole
1875 design. it also resets the selected module (see -module). use the
1876 command 'select *' to select everything but stay in the current module.
1879 create an empty selection. the current module is unchanged.
1882 limit the current scope to the specified module.
1883 the difference between this and simply selecting the module
1884 is that all object names are interpreted relative to this
1885 module after this command until the selection is cleared again.
1887 When this command is called without an argument, the current selection
1888 is displayed in a compact form (i.e. only the module name when a whole module
1891 The <selection> argument itself is a series of commands for a simple stack
1892 machine. Each element on the stack represents a set of selected objects.
1893 After this commands have been executed, the union of all remaining sets
1894 on the stack is computed and used as selection for the command.
1896 Pushing (selecting) object when not in -module mode:
1899 select the specified module(s)
1901 <mod_pattern>/<obj_pattern>
1902 select the specified object(s) from the module(s)
1904 Pushing (selecting) object when in -module mode:
1907 select the specified object(s) from the current module
1909 A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
1910 matching module names, or one of the following:
1912 A:<pattern>, A:<pattern>=<pattern>
1913 all modules with an attribute matching the given pattern
1914 in addition to = also <, <=, >=, and > are supported
1916 An <obj_pattern> can be an object name, wildcard expression, or one of
1920 all wires with a name matching the given wildcard pattern
1922 i:<pattern>, o:<pattern>, x:<pattern>
1923 all inputs (i:), outputs (o:) or any ports (x:) with matching names
1925 s:<size>, s:<min>:<max>
1926 all wires with a matching width
1929 all memories with a name matching the given pattern
1932 all cells with a name matching the given pattern
1935 all cells with a type matching the given pattern
1938 all processes with a name matching the given pattern
1941 all objects with an attribute name matching the given pattern
1943 a:<pattern>=<pattern>
1944 all objects with a matching attribute name-value-pair.
1945 in addition to = also <, <=, >=, and > are supported
1947 r:<pattern>, r:<pattern>=<pattern>
1948 cells with matching parameters. also with <, <=, >= and >.
1951 all objects with a name matching the given pattern
1952 (i.e. 'n:' is optional as it is the default matching rule)
1955 push the selection saved prior with 'select -set <name> ...'
1957 The following actions can be performed on the top sets on the stack:
1960 push a copy of the current selection to the stack
1963 replace the stack with a union of all elements on it
1966 replace top set with its invert
1969 replace the two top sets on the stack with their union
1972 replace the two top sets on the stack with their intersection
1975 pop the top set from the stack and subtract it from the new top
1978 like %d but swap the roles of two top sets on the stack
1981 create a copy of the top set rom the stack and push it
1983 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1984 expand top set <num1> num times according to the specified rules.
1985 (i.e. select all cells connected to selected wires and select all
1986 wires connected to selected cells) The rules specify which cell
1987 ports to use for this. the syntax for a rule is a '-' for exclusion
1988 and a '+' for inclusion, followed by an optional comma separated
1989 list of cell types followed by an optional comma separated list of
1990 cell ports in square brackets. a rule can also be just a cell or wire
1991 name that limits the expansion (is included but does not go beyond).
1992 select at most <num2> objects. a warning message is printed when this
1993 limit is reached. When '*' is used instead of <num1> then the process
1994 is repeated until no further object are selected.
1996 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1997 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1998 simmilar to %x, but only select input (%ci) or output cones (%co)
2001 expand top set by selecting all wires that are (at least in part)
2002 aliases for selected wires.
2005 expand top set by adding all modules of instantiated cells in selected
2009 expand top set by selecting all modules that contain selected objects
2011 Example: the following command selects all wires that are connected to a
2012 'GATE' input of a 'SWITCH' cell:
2014 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
2017 \section{setattr -- set/unset attributes on objects}
2019 \begin{lstlisting}[numbers=left,frame=single]
2020 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
2022 Set/unset the given attributes on the selected objects. String values must be
2023 passed in double quotes (").
2025 When called with -mod, this command will set and unset attributes on modules
2026 instead of objects within modules.
2029 \section{setparam -- set/unset parameters on objects}
2030 \label{cmd:setparam}
2031 \begin{lstlisting}[numbers=left,frame=single]
2032 setparam [ -set name value | -unset name ]... [selection]
2034 Set/unset the given parameters on the selected cells. String values must be
2035 passed in double quotes (").
2038 \section{setundef -- replace undef values with defined constants}
2039 \label{cmd:setundef}
2040 \begin{lstlisting}[numbers=left,frame=single]
2041 setundef [options] [selection]
2043 This command replaced undef (x) constants with defined (0/1) constants.
2046 also set undriven nets to constant values
2049 replace with bits cleared (0)
2052 replace with bits set (1)
2055 replace with random bits using the specified integer als seed
2056 value for the random number generator.
2059 \section{share -- perform sat-based resource sharing}
2061 \begin{lstlisting}[numbers=left,frame=single]
2062 share [options] [selection]
2064 This pass merges shareable resources into a single resource. A SAT solver
2065 is used to determine if two resources are share-able.
2068 Per default the selection of cells that is considered for sharing is
2069 narrowed using a list of cell types. With this option all selected
2070 cells are considered for resource sharing.
2072 IMPORTANT NOTE: If the -all option is used then no cells with internal
2073 state must be selected!
2076 Per default some heuristics are used to reduce the number of cells
2077 considered for resource sharing to only large resources. This options
2078 turns this heuristics off, resulting in much more cells being considered
2079 for resource sharing.
2082 Only consider the simple part of the control logic in SAT solving, resulting
2083 in much easier SAT problems at the cost of maybe missing some oportunities
2084 for resource sharing.
2087 Only perform the first N merges, then stop. This is useful for debugging.
2090 \section{shell -- enter interactive command mode}
2092 \begin{lstlisting}[numbers=left,frame=single]
2095 This command enters the interactive command mode. This can be useful
2096 in a script to interrupt the script at a certain point and allow for
2097 interactive inspection or manual synthesis of the design at this point.
2099 The command prompt of the interactive shell indicates the current
2100 selection (see 'help select'):
2103 the entire design is selected
2106 only part of the design is selected
2109 the entire module 'modname' is selected using 'select -module modname'
2112 only part of current module 'modname' is selected
2114 When in interactive shell, some errors (e.g. invalid command arguments)
2115 do not terminate yosys but return to the command prompt.
2117 This command is the default action if nothing else has been specified
2118 on the command line.
2120 Press Ctrl-D or type 'exit' to leave the interactive shell.
2123 \section{show -- generate schematics using graphviz}
2125 \begin{lstlisting}[numbers=left,frame=single]
2126 show [options] [selection]
2128 Create a graphviz DOT file for the selected part of the design and compile it
2129 to a graphics file (usually SVG or PostScript).
2132 Run the specified command with the graphics file as parameter.
2135 Generate a graphics file in the specified format.
2136 Usually <format> is 'svg' or 'ps'.
2138 -lib <verilog_or_ilang_file>
2139 Use the specified library file for determining whether cell ports are
2140 inputs or outputs. This option can be used multiple times to specify
2141 more than one library.
2144 generate <prefix>.* instead of ~/.yosys_show.*
2146 -color <color> <object>
2147 assign the specified color to the specified object. The object can be
2148 a single selection wildcard expressions or a saved set of objects in
2149 the @<name> syntax (see "help select" for details).
2151 -label <text> <object>
2152 assign the specified label text to the specified object. The object can
2153 be a single selection wildcard expressions or a saved set of objects in
2154 the @<name> syntax (see "help select" for details).
2157 Randomly assign colors to the wires. The integer argument is the seed
2158 for the random number generator. Change the seed value if the colored
2159 graph still is ambigous. A seed of zero deactivates the coloring.
2161 -colorattr <attribute_name>
2162 Use the specified attribute to assign colors. A unique color is
2163 assigned to each unique value of this attribute.
2166 annotate busses with a label indicating the width of the bus.
2169 mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED
2170 cell parameter) with an asterisk next to the port name.
2173 stretch the graph so all inputs are on the left side and all outputs
2174 (including inout ports) are on the right side.
2177 wait for the use to press enter to before returning
2180 enumerate objects with internal ($-prefixed) names
2183 do not abbeviate objects with internal ($-prefixed) names
2186 do not add the module name as graph title to the dot file
2188 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
2189 specified, 'xdot' is used to display the schematic.
2191 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
2192 unless another prefix is specified using -prefix <prefix>.
2195 \section{simplemap -- mapping simple coarse-grain cells}
2196 \label{cmd:simplemap}
2197 \begin{lstlisting}[numbers=left,frame=single]
2198 simplemap [selection]
2200 This pass maps a small selection of simple coarse-grain cells to yosys gate
2201 primitives. The following internal cell types are mapped by this pass:
2203 $not, $pos, $and, $or, $xor, $xnor
2204 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
2205 $logic_not, $logic_and, $logic_or, $mux
2206 $sr, $dff, $dffsr, $adff, $dlatch
2209 \section{splice -- create explicit splicing cells}
2211 \begin{lstlisting}[numbers=left,frame=single]
2212 splice [options] [selection]
2214 This command adds $slice and $concat cells to the design to make the splicing
2215 of multi-bit signals explicit. This for example is useful for coarse grain
2216 synthesis, where dedidacted hardware is needed to splice signals.
2219 only select the cell ports to rewire by the cell. if the selection
2220 contains a cell, than all cell inputs are rewired, if necessary.
2223 only select the cell ports to rewire by the wire. if the selection
2224 contains a wire, than all cell ports driven by this wire are wired,
2228 it is sufficient if the driver of any bit of a cell port is selected.
2229 by default all bits must be selected.
2232 do not rewire selected module outputs.
2235 only rewire cell ports with the specified name. can be used multiple
2236 times. implies -no_output.
2239 do not rewire cell ports with the specified name. can be used multiple
2240 times. can not be combined with -port <name>.
2242 By default selected output wires and all cell ports of selected cells driven
2243 by selected wires are rewired.
2246 \section{splitnets -- split up multi-bit nets}
2247 \label{cmd:splitnets}
2248 \begin{lstlisting}[numbers=left,frame=single]
2249 splitnets [options] [selection]
2251 This command splits multi-bit nets into single-bit nets.
2253 -format char1[char2[char3]]
2254 the first char is inserted between the net name and the bit index, the
2255 second char is appended to the netname. e.g. -format () creates net
2256 names like 'mysignal(42)'. the 3rd character is the range separation
2257 character when creating multi-bit wires. the default is '[]:'.
2260 also split module ports. per default only internal signals are split.
2263 don't blindly split nets in individual bits. instead look at the driver
2264 and split nets so that no driver drives only part of a net.
2267 \section{stat -- print some statistics}
2269 \begin{lstlisting}[numbers=left,frame=single]
2270 stat [options] [selection]
2272 Print some statistics (number of objects) on the selected portion of the
2276 print design hierarchy with this module as top. if the design is fully
2277 selected and a module has the 'top' attribute set, this module is used
2278 default value for this option.
2281 annotate internal cell types with their word width.
2282 e.g. $add_8 for an 8 bit wide $add cell.
2285 \section{submod -- moving part of a module to a new submodule}
2287 \begin{lstlisting}[numbers=left,frame=single]
2290 This pass identifies all cells with the 'submod' attribute and moves them to
2291 a newly created module. The value of the attribute is used as name for the
2292 cell that replaces the group of cells with the same attribute value.
2294 This pass can be used to create a design hierarchy in flat design. This can
2295 be useful for analyzing or reverse-engineering a design.
2297 This pass only operates on completely selected modules with no processes
2301 submod -name <name> [selection]
2303 As above, but don't use the 'submod' attribute but instead use the selection.
2304 Only objects from one module might be selected. The value of the -name option
2305 is used as the value of the 'submod' attribute above.
2308 \section{synth -- generic synthesis script}
2310 \begin{lstlisting}[numbers=left,frame=single]
2313 This command runs the default synthesis script. This command does not operate
2314 on partly selected designs.
2317 use the specified module as top module (default='top')
2320 passed to 'fsm_recode' via 'fsm'
2323 do not run abc (as if yosys was compiled without ABC support)
2325 -run <from_label>[:<to_label>]
2326 only run the commands between the labels (see below). an empty
2327 from label is synonymous to 'begin', and empty to label is
2328 synonymous to the end of the command list.
2331 The following commands are executed by this synthesis command:
2334 hierarchy -check [-top <top>]
2360 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
2361 \label{cmd:synth_xilinx}
2362 \begin{lstlisting}[numbers=left,frame=single]
2363 synth_xilinx [options]
2365 This command runs synthesis for Xilinx FPGAs. This command does not operate on
2366 partly selected designs. At the moment this command creates netlists that are
2367 compatible with 7-Series Xilinx devices.
2370 use the specified module as top module (default='top')
2373 write the design to the specified edif file. writing of an output file
2374 is omitted if this parameter is not specified.
2376 -run <from_label>:<to_label>
2377 only run the commands between the labels (see below). an empty
2378 from label is synonymous to 'begin', and empty to label is
2379 synonymous to the end of the command list.
2382 flatten design before synthesis
2385 run 'abc' with -dff option
2388 The following commands are executed by this synthesis command:
2391 read_verilog -lib +/xilinx/cells_sim.v
2392 hierarchy -check -top <top>
2394 flatten: (only if -flatten)
2403 memory_bram -rules +/xilinx/brams.txt
2404 techmap -map +/xilinx/brams_map.v
2410 techmap -map +/techmap.v -map +/xilinx/arith_map.v
2418 techmap -map +/xilinx/cells_map.v
2422 write_edif synth.edif
2425 \section{tcl -- execute a TCL script file}
2427 \begin{lstlisting}[numbers=left,frame=single]
2430 This command executes the tcl commands in the specified file.
2431 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
2433 The tcl command 'yosys -import' can be used to import all yosys
2434 commands directly as tcl commands to the tcl shell. The yosys
2435 command 'proc' is wrapped using the tcl command 'procs' in order
2436 to avoid a name collision with the tcl builting command 'proc'.
2439 \section{techmap -- generic technology mapper}
2441 \begin{lstlisting}[numbers=left,frame=single]
2442 techmap [-map filename] [selection]
2444 This pass implements a very simple technology mapper that replaces cells in
2445 the design with implementations given in form of a verilog or ilang source
2449 the library of cell implementations to be used.
2450 without this parameter a builtin library is used that
2451 transforms the internal RTL cells to the internal gate
2455 like -map above, but with an in-memory design instead of a file.
2458 like -map, but look for the file in the share directory (where the
2459 yosys data files are). this is mainly used internally when techmap
2460 is called from other commands.
2463 load the cell implementations as separate modules into the design
2464 instead of inlining them.
2467 only run the specified number of iterations.
2470 instead of the iterative breadth-first algorithm use a recursive
2471 depth-first algorithm. both methods should yield equivialent results,
2472 but may differ in performance.
2475 Automatically call "proc" on implementations that contain processes.
2478 this option will cause techmap to exit with an error if it can't map
2479 a selected cell. only cell types that end on an underscore are accepted
2480 as final cell types by this mode.
2482 -D <define>, -I <incdir>
2483 this options are passed as-is to the verilog frontend for loading the
2484 map file. Note that the verilog frontend is also called with the
2485 '-ignore_redef' option set.
2487 When a module in the map file has the 'techmap_celltype' attribute set, it will
2488 match cells with a type that match the text value of this attribute. Otherwise
2489 the module name will be used to match the cell.
2491 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
2492 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
2494 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
2495 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
2497 When a module in the map file has the 'techmap_wrap' attribute set, techmap
2498 will create a wrapper for the cell and then run the command string that the
2499 attribute is set to on the wrapper module.
2501 All wires in the modules from the map file matching the pattern _TECHMAP_*
2502 or *._TECHMAP_* are special wires that are used to pass instructions from
2503 the mapping module to the techmap command. At the moment the following special
2504 wires are supported:
2507 When this wire is set to a non-zero constant value, techmap will not
2508 use this module and instead try the next module with a matching
2509 'techmap_celltype' attribute.
2511 When such a wire exists but does not have a constant value after all
2512 _TECHMAP_DO_* commands have been executed, an error is generated.
2515 This wires are evaluated in alphabetical order. The constant text value
2516 of this wire is a yosys command (or sequence of commands) that is run
2517 by techmap on the module. A common use case is to run 'proc' on modules
2518 that are written using always-statements.
2520 When such a wire has a non-constant value at the time it is to be
2521 evaluated, an error is produced. That means it is possible for such a
2522 wire to start out as non-constant and evaluate to a constant value
2523 during processing of other _TECHMAP_DO_* commands.
2525 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
2526 in this case techmap will create a copy for each distinct configuration
2527 of constant inputs and shorted inputs at this point and import the
2528 constant and connected bits into the map module. All further commands
2529 are executed in this copy. This is a very convenient way of creating
2530 optimizied specializations of techmap modules without using the special
2531 parameters described below.
2533 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
2534 then techmap will recursively replace the cells in the module with their
2535 implementation. This is not affected by the -max_iter option.
2537 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
2539 In addition to this special wires, techmap also supports special parameters in
2540 modules in the map file:
2543 When a parameter with this name exists, it will be set to the type name
2544 of the cell that matches the module.
2546 _TECHMAP_CONSTMSK_<port-name>_
2547 _TECHMAP_CONSTVAL_<port-name>_
2548 When this pair of parameters is available in a module for a port, then
2549 former has a 1-bit for each constant input bit and the latter has the
2550 value for this bit. The unused bits of the latter are set to undef (x).
2552 _TECHMAP_BITS_CONNMAP_
2553 _TECHMAP_CONNMAP_<port-name>_
2554 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
2555 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
2556 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
2557 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
2558 This can be used to detect shorted inputs.
2560 When a module in the map file has a parameter where the according cell in the
2561 design has a port, the module from the map file is only used if the port in
2562 the design is connected to a constant value. The parameter is then set to the
2565 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
2566 of the cell that is beeing replaced.
2568 See 'help extract' for a pass that does the opposite thing.
2570 See 'help flatten' for a pass that does flatten the design (which is
2571 esentially techmap but using the design itself as map library).
2574 \section{tee -- redirect command output to file}
2576 \begin{lstlisting}[numbers=left,frame=single]
2577 tee [-q] [-o logfile|-a logfile] cmd
2579 Execute the specified command, optionally writing the commands output to the
2580 specified logfile(s).
2583 Do not print output to the normal destination (console and/or log file)
2586 Write output to this file, truncate if exists.
2589 Write output to this file, append if exists.
2592 \section{test\_abcloop -- automatically test handling of loops in abc command}
2593 \label{cmd:test_abcloop}
2594 \begin{lstlisting}[numbers=left,frame=single]
2595 test_abcloop [options]
2597 Test handling of logic loops in ABC.
2600 create this number of circuits and test them (default = 100).
2602 -s {positive_integer}
2603 use this value as rng seed value (default = unix time).
2606 \section{test\_autotb -- generate simple test benches}
2607 \label{cmd:test_autotb}
2608 \begin{lstlisting}[numbers=left,frame=single]
2609 test_autotb [options] [filename]
2611 Automatically create primitive verilog test benches for all modules in the
2612 design. The generated testbenches toggle the input pins of the module in
2613 a semi-random manner and dumps the resulting output signals.
2615 This can be used to check the synthesis results for simple circuits by
2616 comparing the testbench output for the input files and the synthesis results.
2618 The backend automatically detects clock signals. Additionally a signal can
2619 be forced to be interpreted as clock signal by setting the attribute
2620 'gentb_clock' on the signal.
2622 The attribute 'gentb_constant' can be used to force a signal to a constant
2623 value after initialization. This can e.g. be used to force a reset signal
2624 low in order to explore more inner states in a state machine.
2627 number of iterations the test bench shuld run (default = 1000)
2630 \section{test\_cell -- automatically test the implementation of a cell type}
2631 \label{cmd:test_cell}
2632 \begin{lstlisting}[numbers=left,frame=single]
2633 test_cell [options] {cell-types}
2635 Tests the internal implementation of the given cell type (for example '$add')
2636 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
2638 Run with 'all' instead of a cell type to run the test on all supported
2639 cell types. Use for example 'all /$add' for all cell types except $add.
2642 create this number of cell instances and test them (default = 100).
2644 -s {positive_integer}
2645 use this value as rng seed value (default = unix time).
2648 don't generate circuits. instead load the specified ilang file.
2650 -w {filename_prefix}
2651 don't test anything. just generate the circuits and write them
2652 to ilang files with the specified prefix
2655 pass this option to techmap.
2658 use "techmap -map +/simlib.v -max_iter 2 -autoproc"
2661 when creating test benches with dividers, create an additional mux
2662 to mask out the division-by-zero case
2664 -script {script_file}
2665 instead of calling "techmap", call "script {script_file}".
2668 set some input bits to random constant values
2671 do not check SAT model or run SAT equivalence checking
2674 print additional debug information to the console
2677 create a verilog test bench to test simlib and write_verilog
2680 \section{trace -- redirect command output to file}
2682 \begin{lstlisting}[numbers=left,frame=single]
2685 Execute the specified command, logging all changes the command performs on
2686 the design in real time.
2689 \section{verific -- load Verilog and VHDL designs using Verific}
2691 \begin{lstlisting}[numbers=left,frame=single]
2692 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
2694 Load the specified Verilog/SystemVerilog files into Verific.
2697 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
2699 Load the specified VHDL files into Verific.
2702 verific -import [-gates] {-all | <top-module>..}
2704 Elaborate the design for the sepcified top modules, import to Yosys and
2705 reset the internal state of Verific. A gate-level netlist is created
2706 when called with -gates.
2708 Visit http://verific.com/ for more information on Verific.
2711 \section{verilog\_defaults -- set default options for read\_verilog}
2712 \label{cmd:verilog_defaults}
2713 \begin{lstlisting}[numbers=left,frame=single]
2714 verilog_defaults -add [options]
2716 Add the sepcified options to the list of default options to read_verilog.
2719 verilog_defaults -clear
2720 Clear the list of verilog default options.
2723 verilog_defaults -push verilog_defaults -pop
2724 Push or pop the list of default options to a stack. Note that -push does
2728 \section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
2729 \label{cmd:vhdl2verilog}
2730 \begin{lstlisting}[numbers=left,frame=single]
2731 vhdl2verilog [options] <vhdl-file>..
2733 This command reads VHDL source files using the 'vhdl2verilog' tool and the
2734 Yosys Verilog frontend.
2737 do not import the vhdl2verilog output. instead write it to the
2740 -vhdl2verilog_dir <directory>
2741 do use the specified vhdl2verilog installation. this is the directory
2742 that contains the setup_env.sh file. when this option is not present,
2743 it is assumed that vhdl2verilog is in the PATH environment variable.
2745 -top <top-entity-name>
2746 The name of the top entity. This option is mandatory.
2748 The following options are passed as-is to vhdl2verilog:
2750 -arch <architecture_name>
2760 vhdl2verilog can be obtained from:
2761 http://www.edautils.com/vhdl2verilog.html
2764 \section{wreduce -- reduce the word size of operations is possible}
2766 \begin{lstlisting}[numbers=left,frame=single]
2767 wreduce [options] [selection]
2769 This command reduces the word size of operations. For example it will replace
2770 the 32 bit adders in the following code with adders of more appropriate widths:
2772 module test(input [3:0] a, b, c, output [7:0] y);
2773 assign y = a + b + c + 1;
2777 \section{write\_blif -- write design to BLIF file}
2778 \label{cmd:write_blif}
2779 \begin{lstlisting}[numbers=left,frame=single]
2780 write_blif [options] [filename]
2782 Write the current design to an BLIF file.
2785 set the specified module as design top module
2787 -buf <cell-type> <in-port> <out-port>
2788 use cells of type <cell-type> with the specified port names for buffers
2790 -unbuf <cell-type> <in-port> <out-port>
2791 replace buffer cells with the specified name and port names with
2792 a .names statement that models a buffer
2794 -true <cell-type> <out-port>
2795 -false <cell-type> <out-port>
2796 -undef <cell-type> <out-port>
2797 use the specified cell types to drive nets that are constant 1, 0, or
2798 undefined. when '-' is used as <cell-type>, then <out-port> specifies
2799 the wire name to be used for the constant signal and no cell driving
2800 that wire is generated.
2802 The following options can be useful when the generated file is not going to be
2803 read by a BLIF parser but a custom tool. It is recommended to not name the output
2804 file *.blif when any of this options is used.
2807 do not translate Yosys's internal gates to generic BLIF logic
2808 functions. Instead create .subckt or .gate lines for all cells.
2811 print .gate instead of .subckt lines for all cells that are not
2812 instantiations of other modules from this design.
2815 do not generate buffers for connected wires. instead use the
2816 non-standard .conn statement.
2819 use the non-standard .param statement to write module parameters
2822 write blackbox cells with .blackbox statement.
2825 do not write definitions for the $true, $false and $undef wires.
2828 \section{write\_btor -- write design to BTOR file}
2829 \label{cmd:write_btor}
2830 \begin{lstlisting}[numbers=left,frame=single]
2831 write_btor [filename]
2833 Write the current design to an BTOR file.
2836 \section{write\_edif -- write design to EDIF netlist file}
2837 \label{cmd:write_edif}
2838 \begin{lstlisting}[numbers=left,frame=single]
2839 write_edif [options] [filename]
2841 Write the current design to an EDIF netlist file.
2844 set the specified module as design top module
2846 Unfortunately there are different "flavors" of the EDIF file format. This
2847 command generates EDIF files for the Xilinx place&route tools. It might be
2848 necessary to make small modifications to this command when a different tool
2852 \section{write\_file -- write a text to a file}
2853 \label{cmd:write_file}
2854 \begin{lstlisting}[numbers=left,frame=single]
2855 write_file [options] output_file [input_file]
2857 Write the text fron the input file to the output file.
2860 Append to output file (instead of overwriting)
2863 Inside a script the input file can also can a here-document:
2865 write_file hello.txt <<EOT
2870 \section{write\_ilang -- write design to ilang file}
2871 \label{cmd:write_ilang}
2872 \begin{lstlisting}[numbers=left,frame=single]
2873 write_ilang [filename]
2875 Write the current design to an 'ilang' file. (ilang is a text representation
2876 of a design in yosys's internal format.)
2879 only write selected parts of the design.
2882 \section{write\_intersynth -- write design to InterSynth netlist file}
2883 \label{cmd:write_intersynth}
2884 \begin{lstlisting}[numbers=left,frame=single]
2885 write_intersynth [options] [filename]
2887 Write the current design to an 'intersynth' netlist file. InterSynth is
2888 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
2891 do not generate celltypes and conntypes commands. i.e. just output
2892 the netlists. this is used for postsilicon synthesis.
2894 -lib <verilog_or_ilang_file>
2895 Use the specified library file for determining whether cell ports are
2896 inputs or outputs. This option can be used multiple times to specify
2897 more than one library.
2900 only write selected modules. modules must be selected entirely or
2903 http://www.clifford.at/intersynth/
2906 \section{write\_smt2 -- write design to SMT-LIBv2 file}
2907 \label{cmd:write_smt2}
2908 \begin{lstlisting}[numbers=left,frame=single]
2909 write_smt2 [options] [filename]
2911 Write a SMT-LIBv2 [1] description of the current design. For a module with name
2912 '<mod>' this will declare the sort '<mod>_s' (state of the module) and the the
2913 function '<mod>_t' (state transition function).
2915 The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions
2916 are provided that can be used to access the values of the signals in the module.
2917 Only ports, and signals with the 'keep' attribute set are made available via
2918 such functions. Without the -bv option, multi-bit wires are exported as
2919 separate functions of type Bool for the individual bits. With the -bv option
2920 multi-bit wires are exported as single functions of type BitVec.
2922 The '<mod>_t' function evaluates to 'true' when the given pair of states
2923 describes a valid state transition.
2926 enable support for BitVec (FixedSizeBitVectors theory). with this
2927 option set multi-bit wires are represented using the BitVec sort and
2928 support for coarse grain cells (incl. arithmetic) is enabled.
2930 -tpl <template_file>
2931 use the given template file. the line containing only the token '%%'
2932 is replaced with the regular output of this command.
2934 [1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
2935 R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
2937 ---------------------------------------------------------------------------
2941 Consider the following module (test.v). We want to prove that the output can
2942 never transition from a non-zero value to a zero value.
2944 module test(input clk, output reg [3:0] y);
2945 always @(posedge clk)
2949 For this proof we create the following template (test.tpl).
2951 ; we need QF_UFBV for this poof
2954 ; insert the auto-generated code here
2957 ; declare two state variables s1 and s2
2958 (declare-fun s1 () test_s)
2959 (declare-fun s2 () test_s)
2961 ; state s2 is the successor of state s1
2962 (assert (test_t s1 s2))
2964 ; we are looking for a model with y non-zero in s1
2965 (assert (distinct (|test_n y| s1) #b0000))
2967 ; we are looking for a model with y zero in s2
2968 (assert (= (|test_n y| s2) #b0000))
2970 ; is there such a model?
2973 The following yosys script will create a 'test.smt2' file for our proof:
2976 hierarchy; proc; techmap; opt -fast
2977 write_smt2 -bv -tpl test.tpl test.smt2
2979 Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
2980 from non-zero to zero in the test design.
2983 \section{write\_spice -- write design to SPICE netlist file}
2984 \label{cmd:write_spice}
2985 \begin{lstlisting}[numbers=left,frame=single]
2986 write_spice [options] [filename]
2988 Write the current design to an SPICE netlist file.
2991 generate multi-bit ports in MSB first order
2992 (default is LSB first)
2995 set the net name for constant 0 (default: Vss)
2998 set the net name for constant 1 (default: Vdd)
3001 prefix for not-connected nets (default: _NC)
3004 set the specified module as design top module
3007 \section{write\_verilog -- write design to verilog file}
3008 \label{cmd:write_verilog}
3009 \begin{lstlisting}[numbers=left,frame=single]
3010 write_verilog [options] [filename]
3012 Write the current design to a verilog file.
3015 without this option all internal object names (the ones with a dollar
3016 instead of a backslash prefix) are changed to short names in the
3017 format '_<number>_'.
3020 with this option no attributes are included in the output
3023 with this option attributes are included as comments in the output
3026 without this option all internal cells are converted to verilog
3030 usually modules with the 'blackbox' attribute are ignored. with
3031 this option set only the modules with the 'blackbox' attribute
3032 are written to the output file.
3035 only write selected modules. modules must be selected entirely or