1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interpreted as the command string to be passed to ABC. The
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
29 for -liberty with -constr:
30 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
31 &nf
{D
}; &put; buffer; upsize
{D
}; dnsize
{D
}; stime -p
33 for -lut/-luts (only one LUT size):
34 strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2;
37 for -lut/-luts (different LUT sizes):
38 strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2
41 strash; ifraig; scorr; dc2; dretime; strash; dch -f;
45 strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
49 use different default scripts that are slightly faster (at the cost
52 for -liberty without -constr:
53 strash; dretime; map
{D
}
55 for -liberty with -constr:
56 strash; dretime; map
{D
}; buffer; upsize
{D
}; dnsize
{D
};
63 strash; dretime; cover -I
{I
} -P
{P
}
69 generate netlists for the specified cell library (using the liberty
73 pass this file with timing constraints to ABC. use with -liberty.
75 a constr file contains two lines:
76 set_driving_cell <cell_name>
77 set_load <floating_point_number>
79 the set_driving_cell statement defines which cell type is assumed to
80 drive the primary inputs and the set_load statement sets the load in
81 femtofarads for each primary output.
84 set delay target. the string
{D
} in the default scripts above is
85 replaced by this option when used, and an empty string otherwise.
86 this also replaces 'dretime' with 'dretime; retime -o
{D
}' in the
87 default scripts above.
90 maximum number of SOP inputs.
91 (replaces
{I
} in the default scripts above)
94 maximum number of SOP products.
95 (replaces
{P
} in the default scripts above)
98 maximum number of LUT inputs shared.
99 (replaces
{S
} in the default scripts above, default: -S
1)
102 generate netlist using luts of (max) the specified width.
105 generate netlist using luts of (max) the specified width <w2>. All
106 luts with width <= <w1> have constant cost. for luts larger than <w1>
107 the area cost doubles with each additional input bit. the delay cost
108 is still constant for all lut widths.
110 -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
111 generate netlist using luts. Use the specified costs for luts with
1,
115 map to sum-of-product cells and inverters
118 Map to the specified list of gate types. Supported gates types are:
119 AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,
120 NMUX, AOI3, OAI3, AOI4, OAI4.
121 (The NOT gate is always added to this list automatically.)
123 The following aliases can be used to reference common sets of gate types:
124 simple: AND OR XOR MUX
126 cmos3: NAND NOR AOI3 OAI3
127 cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4
128 cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR
129 gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT
130 aig: AND NAND OR NOR ANDNOT ORNOT
132 The alias 'all' represent the full set of all gate types.
134 Prefix a gate type with a '-' to remove it from the list. For example
135 the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.
137 The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.
140 also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
141 clock domains are automatically partitioned in clock domains and each
142 domain is passed through ABC independently.
144 -clk
[!
]<clock-signal-name>
[,
[!
]<enable-signal-name>
]
145 use only the specified clock domain. this is like -dff, but only FF
146 cells that belong to the specified clock domain are used.
149 set the "keep" attribute on flip-flop output wires. (and thus preserve
150 them, for example for equivalence checking.)
153 when this option is used, the temporary files created by this pass
154 are not removed. this is useful for debugging.
157 print the temp dir name in log. usually this is suppressed so that the
158 command output is identical across runs.
161 set a 'abcgroup' attribute on all objects created by ABC. The value of
162 this attribute is a unique integer for each ABC process started. This
163 is useful for debugging the partitioning of clock domains.
166 run the 'dress' command after all other ABC commands. This aims to
167 preserve naming by an equivalence check between the original and post-ABC
168 netlists (experimental).
170 When neither -liberty nor -lut is used, the Yosys standard cell library is
171 loaded into ABC before the ABC script is executed.
173 Note that this is a logic optimization pass within Yosys that is calling ABC
174 internally. This is not going to "run ABC on your design". It will instead run
175 ABC on logic snippets extracted from your design. You will not get any useful
176 output when passing an ABC script that writes a file. Instead write your full
177 design as BLIF file with write_blif and then load that into ABC externally if
178 you want to use ABC to convert your design into another format.
180 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
183 \section{abc9 -- use ABC9 for technology mapping
}
185 \begin{lstlisting
}[numbers=left,frame=single
]
186 abc9
[options
] [selection
]
188 This script pass performs a sequence of commands to facilitate the use of the ABC
189 tool
[1] for technology mapping of the current design to a target FPGA
190 architecture. Only fully-selected modules are supported.
192 -run <from_label>:<to_label>
193 only run the commands between the labels (see below). an empty
194 from label is synonymous to 'begin', and empty to label is
195 synonymous to the end of the command list.
198 use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
199 This can e.g. be used to call a specific version of ABC or a wrapper.
202 use the specified ABC script file instead of the default script.
204 if <file> starts with a plus sign (+), then the rest of the filename
205 string is interpreted as the command string to be passed to ABC. The
206 leading plus sign is removed and all commas (,) in the string are
207 replaced with blanks before the string is passed to ABC.
209 if no -script parameter is given, the following scripts are used:
210 &scorr; &sweep; &dc2; &dch -f; &ps; &if
{C
} {W
} {D
} {R
} -v; &mfs
213 use different default scripts that are slightly faster (at the cost
215 &if
{C
} {W
} {D
} {R
} -v
218 set delay target. the string
{D
} in the default scripts above is
219 replaced by this option when used, and an empty string otherwise
220 (indicating best possible delay).
223 generate netlist using luts of (max) the specified width.
226 generate netlist using luts of (max) the specified width <w2>. All
227 luts with width <= <w1> have constant cost. for luts larger than <w1>
228 the area cost doubles with each additional input bit. the delay cost
229 is still constant for all lut widths.
232 pass this file with lut library to ABC.
234 -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
235 generate netlist using luts. Use the specified costs for luts with
1,
239 when auto-generating the lut library, discard all luts equal to or
240 greater than this size (applicable when neither -lut nor -luts is
244 also pass $_ABC9_FF_ cells through to ABC. modules with many clock
245 domains are marked as such and automatically partitioned by ABC.
248 when this option is used, the temporary files created by this pass
249 are not removed. this is useful for debugging.
252 print the temp dir name in log. usually this is suppressed so that the
253 command output is identical across runs.
256 pass this file with box library to ABC.
258 Note that this is a logic optimization pass within Yosys that is calling ABC
259 internally. This is not going to "run ABC on your design". It will instead run
260 ABC on logic snippets extracted from your design. You will not get any useful
261 output when passing an ABC script that writes a file. Instead write your full
262 design as an XAIGER file with `write_xaiger' and then load that into ABC
263 externally if you want to use ABC to convert your design into another format.
265 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
270 scc -set_attr abc9_scc_id
{}
271 abc9_ops -mark_scc -prep_delays -prep_xaiger
[-dff
] (option for -dff)
272 abc9_ops -prep_lut <maxlut> (skip if -lut or -luts)
273 abc9_ops -prep_box
[-dff
] (skip if -box)
274 select -set abc9_holes A:abc9_holes
275 flatten -wb @abc9_holes
277 abc9_ops -prep_dff (only if -dff)
278 opt -purge @abc9_holes
283 foreach module in selection
284 abc9_ops -write_lut <abc-temp-dir>/input.lut (skip if '-lut' or '-luts')
285 abc9_ops -write_box <abc-temp-dir>/input.box
286 write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig
287 abc9_exe
[options
] -cwd <abc-temp-dir>
[-lut <abc-temp-dir>/input.lut
] -box <abc-temp-dir>/input.box
288 read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig
289 abc9_ops -reintegrate
292 \section{abc9
\_exe -- use ABC9 for technology mapping
}
294 \begin{lstlisting
}[numbers=left,frame=single
]
298 This pass uses the ABC tool
[1] for technology mapping of the top module
299 (according to the
(* top *) attribute or if only one module is currently selected)
300 to a target FPGA architecture.
303 use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
304 This can e.g. be used to call a specific version of ABC or a wrapper.
307 use the specified ABC script file instead of the default script.
309 if <file> starts with a plus sign (+), then the rest of the filename
310 string is interpreted as the command string to be passed to ABC. The
311 leading plus sign is removed and all commas (,) in the string are
312 replaced with blanks before the string is passed to ABC.
314 if no -script parameter is given, the following scripts are used:
315 &scorr; &sweep; &dc2; &dch -f; &ps; &if
{C
} {W
} {D
} {R
} -v; &mfs
318 use different default scripts that are slightly faster (at the cost
320 &if
{C
} {W
} {D
} {R
} -v
323 set delay target. the string
{D
} in the default scripts above is
324 replaced by this option when used, and an empty string otherwise
325 (indicating best possible delay).
328 generate netlist using luts of (max) the specified width.
331 generate netlist using luts of (max) the specified width <w2>. All
332 luts with width <= <w1> have constant cost. for luts larger than <w1>
333 the area cost doubles with each additional input bit. the delay cost
334 is still constant for all lut widths.
337 pass this file with lut library to ABC.
339 -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
340 generate netlist using luts. Use the specified costs for luts with
1,
344 print the temp dir name in log. usually this is suppressed so that the
345 command output is identical across runs.
348 pass this file with box library to ABC.
351 use this as the current working directory, inside which the 'input.xaig'
352 file is expected. temporary files will be created in this directory, and
353 the mapped result will be written to 'output.aig'.
355 Note that this is a logic optimization pass within Yosys that is calling ABC
356 internally. This is not going to "run ABC on your design". It will instead run
357 ABC on logic snippets extracted from your design. You will not get any useful
358 output when passing an ABC script that writes a file. Instead write your full
359 design as BLIF file with write_blif and then load that into ABC externally if
360 you want to use ABC to convert your design into another format.
362 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
365 \section{abc9
\_ops -- helper functions for ABC9
}
367 \begin{lstlisting
}[numbers=left,frame=single
]
368 abc9_ops
[options
] [selection
]
370 This pass contains a set of supporting operations for use during ABC technology
371 mapping, and is expected to be called in conjunction with other operations from
372 the `abc9' script pass. Only fully-selected modules are supported.
375 check that the design is valid, e.g.
(* abc9_box_id *) values are unique,
376 (* abc9_carry *) is only given for one input/output port, etc.
379 insert `$__ABC9_DELAY' blackbox cells into the design to account for
380 certain required times.
383 for an arbitrarily chosen cell in each unique SCC of each selected module
384 (tagged with an
(* abc9_scc_id = <int> *) attribute), temporarily mark all
385 wires driven by this cell's outputs with a
(* keep *) attribute in order
386 to break the SCC. this temporary attribute will be removed on -reintegrate.
389 prepare the design for XAIGER output. this includes computing the
390 topological ordering of ABC9 boxes, as well as preparing the
391 '<module-name>$holes' module that contains the logic behaviour of ABC9
395 consider flop cells (those instantiating modules marked with
(* abc9_flop *))
396 during -prep_
{delays,xaiger,box
}.
399 compute the clock domain and initial value of each flop in the design.
400 process the '$holes' module to support clock-enable functionality.
403 pre-compute the lut library by analysing all modules marked with
404 (* abc9_lut=<area> *).
407 write the pre-computed lut library to <dst>.
410 pre-compute the box library by analysing all modules marked with
414 write the pre-computed box library to <dst>.
417 for each selected module, re-intergrate the module '<module-name>$abc9'
418 by first recovering ABC9 boxes, and then stitching in the remaining primary
422 \section{add -- add objects to the design
}
424 \begin{lstlisting
}[numbers=left,frame=single
]
425 add <command>
[selection
]
427 This command adds objects to the design. It operates on all fully selected
428 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
431 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
433 Add a wire (input, inout, output port) with the given name and width. The
434 command will fail if the object exists already and has different properties
435 than the object to be created.
438 add -global_input <name> <width>
[selection
]
440 Like 'add -input', but also connect the signal between instances of the
444 add
{-assert|-assume|-live|-fair|-cover
} <name1>
[-if <name2>
]
446 Add an $assert, $assume, etc. cell connected to a wire named name1, with its
447 enable signal optionally connected to a wire named name2 (default:
1'b1).
452 Add module
[s
] with the specified name
[s
].
455 \section{aigmap -- map logic to and-inverter-graph circuit
}
457 \begin{lstlisting
}[numbers=left,frame=single
]
458 aigmap
[options
] [selection
]
460 Replace all logic cells with circuits made of only $_AND_ and
464 Enable creation of $_NAND_ cells
467 Overwrite replaced cells in the current selection with new $_AND_,
468 $_NOT_, and $_NAND_, cells
471 \section{alumacc -- extract ALU and MACC cells
}
473 \begin{lstlisting
}[numbers=left,frame=single
]
476 This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
480 \section{anlogic
\_eqn -- Anlogic: Calculate equations for luts
}
481 \label{cmd:anlogic_eqn
}
482 \begin{lstlisting
}[numbers=left,frame=single
]
483 anlogic_eqn
[selection
]
485 Calculate equations for luts since bitstream generator depends on it.
488 \section{anlogic
\_fixcarry -- Anlogic: fix carry chain
}
489 \label{cmd:anlogic_fixcarry
}
490 \begin{lstlisting
}[numbers=left,frame=single
]
491 anlogic_fixcarry
[options
] [selection
]
493 Add Anlogic adders to fix carry chain if needed.
496 \section{assertpmux -- adds asserts for parallel muxes
}
497 \label{cmd:assertpmux
}
498 \begin{lstlisting
}[numbers=left,frame=single
]
499 assertpmux
[options
] [selection
]
501 This command adds asserts to the design that assert that all parallel muxes
502 ($pmux cells) have a maximum of one of their inputs enable at any time.
505 do not enforce the pmux condition during the init state
508 usually the $pmux condition is only checked when the $pmux output
509 is used by the mux tree it drives. this option will deactivate this
510 additional constraint and check the $pmux condition always.
513 \section{async2sync -- convert async FF inputs to sync circuits
}
514 \label{cmd:async2sync
}
515 \begin{lstlisting
}[numbers=left,frame=single
]
516 async2sync
[options
] [selection
]
518 This command replaces async FF inputs with sync circuits emulating the same
519 behavior for when the async signals are actually synchronized to the clock.
521 This pass assumes negative hold time for the async FF inputs. For example when
522 a reset deasserts with the clock edge, then the FF output will still drive the
523 reset value in the next cycle regardless of the data-in value at the time of
526 Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.
529 \section{attrmap -- renaming attributes
}
531 \begin{lstlisting
}[numbers=left,frame=single
]
532 attrmap
[options
] [selection
]
534 This command renames attributes and/or maps key/value pairs to
535 other key/value pairs.
538 Match attribute names case-insensitively and set it to the specified
541 -rename <old_name> <new_name>
542 Rename attributes as specified
544 -map <old_name>=<old_value> <new_name>=<new_value>
545 Map key/value pairs as indicated.
547 -imap <old_name>=<old_value> <new_name>=<new_value>
548 Like -map, but use case-insensitive match for <old_value> when
549 it is a string value.
551 -remove <name>=<value>
552 Remove attributes matching this pattern.
555 Operate on module attributes instead of attributes on wires and cells.
557 For example, mapping Xilinx-style "keep" attributes to Yosys-style:
559 attrmap -tocase keep -imap keep="true" keep=
1 \
560 -imap keep="false" keep=
0 -remove keep=
0
563 \section{attrmvcp -- move or copy attributes from wires to driving cells
}
565 \begin{lstlisting
}[numbers=left,frame=single
]
566 attrmvcp
[options
] [selection
]
568 Move or copy attributes on wires to the cells driving them.
571 By default, attributes are moved. This will only add
572 the attribute to the cell, without removing it from
576 If no selected cell consumes the attribute, then it is
577 left on the wire by default. This option will cause the
578 attribute to be removed from the wire, even if no selected
582 By default, attriburtes are moved to the cell driving the
583 wire. With this option set it will be moved to the cell
584 driven by the wire instead.
587 Move or copy this attribute. This option can be used
591 \section{autoname -- automatically assign names to objects
}
593 \begin{lstlisting
}[numbers=left,frame=single
]
596 Assign auto-generated public names to objects with private names (the ones
600 \section{blackbox -- convert modules into blackbox modules
}
602 \begin{lstlisting
}[numbers=left,frame=single
]
603 blackbox
[options
] [selection
]
605 Convert modules into blackbox modules (remove contents and set the blackbox
609 \section{bugpoint -- minimize testcases
}
611 \begin{lstlisting
}[numbers=left,frame=single
]
614 This command minimizes testcases that crash Yosys. It removes an arbitrary part
615 of the design and recursively invokes Yosys with a given script, repeating these
616 steps while it can find a smaller design that still causes a crash. Once this
617 command finishes, it replaces the current design with the smallest testcase it
620 It is possible to specify the kinds of design part that will be removed. If none
621 are specified, all parts of design will be removed.
624 use this Yosys binary. if not specified, `yosys` is used.
627 use this script to crash Yosys. required.
630 only consider crashes that place this string in the log file.
633 run `proc_clean; clean -purge` after each minimization step. converges
634 faster, but produces larger testcases, and may fail to produce any
635 testcase at all if the crash is related to dangling wires.
638 run `proc_clean; clean -purge` before checking testcase and after
639 finishing. produces smaller and more useful testcases, but may fail to
640 produce any testcase at all if the crash is related to dangling wires.
643 try to remove modules.
646 try to remove module ports.
652 try to reconnect ports to 'x.
655 try to remove process assigns from cases.
658 try to remove process updates from syncs.
661 \section{cd -- a shortcut for 'select -module <name>'
}
663 \begin{lstlisting
}[numbers=left,frame=single
]
666 This is just a shortcut for 'select -module <modname>'.
671 When no module with the specified name is found, but there is a cell
672 with the specified name in the current module, then this is equivalent
677 Remove trailing substrings that start with '.' in current module name until
678 the name of a module in the current design is generated, then switch to that
679 module. Otherwise clear the current selection.
683 This is just a shortcut for 'select -clear'.
686 \section{check -- check for obvious problems in the design
}
688 \begin{lstlisting
}[numbers=left,frame=single
]
689 check
[options
] [selection
]
691 This pass identifies the following problems in the current design:
693 - combinatorial loops
695 - two or more conflicting drivers for one wire
697 - used wires that do not have a driver
702 Also check for wires which have the 'init' attribute set.
705 Also check for wires that have the 'init' attribute set and are not
706 driven by an FF cell type.
709 Also check for internal cells that have not been mapped to cells of the
713 Modify the -mapped behavior to still allow $_TBUF_ cells.
716 Produce a runtime error if any problems are found in the current design.
719 \section{chformal -- change formal constraints of the design
}
721 \begin{lstlisting
}[numbers=left,frame=single
]
722 chformal
[types
] [mode
] [options
] [selection
]
724 Make changes to the formal constraints of the design. The
[types
] options
725 the type of constraint to operate on. If none of the following options are given,
726 the command will operate on all constraint types:
728 -assert $assert cells, representing assert(...) constraints
729 -assume $assume cells, representing assume(...) constraints
730 -live $live cells, representing assert(s_eventually ...)
731 -fair $fair cells, representing assume(s_eventually ...)
732 -cover $cover cells, representing cover() statements
734 Exactly one of the following modes must be specified:
737 remove the cells and thus constraints from the design
740 bypass FFs that only delay the activation of a constraint
743 delay activation of the constraint by <N> clock cycles
746 ignore activation of the constraint in the first <N> clock cycles
752 change the roles of cells as indicated. these options can be combined
755 \section{chparam -- re-evaluate modules with new parameters
}
757 \begin{lstlisting
}[numbers=left,frame=single
]
758 chparam
[ -set name value
]...
[selection
]
760 Re-evaluate the selected modules with new parameters. String values must be
761 passed in double quotes (").
764 chparam -list
[selection
]
766 List the available parameters of the selected modules.
769 \section{chtype -- change type of cells in the design
}
771 \begin{lstlisting
}[numbers=left,frame=single
]
772 chtype
[options
] [selection
]
774 Change the types of cells in the design.
777 set the cell type to the given type
779 -map <old_type> <new_type>
780 change cells types that match <old_type> to <new_type>
783 \section{clean -- remove unused cells and wires
}
785 \begin{lstlisting
}[numbers=left,frame=single
]
786 clean
[options
] [selection
]
788 This is identical to 'opt_clean', but less verbose.
790 When commands are separated using the ';;' token, this command will be executed
791 between the commands.
793 When commands are separated using the ';;;' token, this command will be executed
794 in -purge mode between the commands.
797 \section{clk2fflogic -- convert clocked FFs to generic \$ff cells
}
798 \label{cmd:clk2fflogic
}
799 \begin{lstlisting
}[numbers=left,frame=single
]
800 clk2fflogic
[options
] [selection
]
802 This command replaces clocked flip-flops with generic $ff cells that use the
803 implicit global clock. This is useful for formal verification of designs with
807 \section{clkbufmap -- insert global buffers on clock networks
}
808 \label{cmd:clkbufmap
}
809 \begin{lstlisting
}[numbers=left,frame=single
]
810 clkbufmap
[options
] [selection
]
812 Inserts global buffers between nets connected to clock inputs and their drivers.
814 In the absence of any selection, all wires without the 'clkbuf_inhibit'
815 attribute will be considered for global buffer insertion.
816 Alternatively, to consider all wires without the 'buffer_type' attribute set to
817 'none' or 'bufr' one would specify:
818 'w:* a:buffer_type=none a:buffer_type=bufr
%u %d'
821 -buf <celltype> <portname_out>:<portname_in>
822 Specifies the cell type to use for the global buffers
823 and its port names. The first port will be connected to
824 the clock network sinks, and the second will be connected
825 to the actual clock source. This option is required.
827 -inpad <celltype> <portname_out>:<portname_in>
828 If specified, a PAD cell of the given type is inserted on
829 clock nets that are also top module's inputs (in addition
830 to the global buffer).
833 \section{connect -- create or remove connections
}
835 \begin{lstlisting
}[numbers=left,frame=single
]
836 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
838 Create a connection. This is equivalent to adding the statement 'assign
839 <lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
840 drivers for <lhs-expr> are unconnected. This can be overwritten by using
844 connect
[-nomap
] -unset <expr>
846 Unconnect all existing drivers for the specified expression.
849 connect
[-nomap
] -port <cell> <port> <expr>
851 Connect the specified cell port to the specified cell port.
854 Per default signal alias names are resolved and all signal names are mapped
855 the the signal name of the primary driver. Using the -nomap option deactivates
858 The connect command operates in one module only. Either only one module must
859 be selected or an active module must be set using the 'cd' command.
861 This command does not operate on module with processes.
864 \section{connect
\_rpc -- connect to RPC frontend
}
865 \label{cmd:connect_rpc
}
866 \begin{lstlisting
}[numbers=left,frame=single
]
867 connect_rpc -exec <command>
[args...
]
868 connect_rpc -path <path>
870 Load modules using an out-of-process frontend.
872 -exec <command>
[args...
]
873 run <command> with arguments
[args...
]. send requests on stdin, read
874 responses from stdout.
877 connect to Unix domain socket at <path>. (Unix)
878 connect to bidirectional byte-type named pipe at <path>. (Windows)
880 A simple JSON-based, newline-delimited protocol is used for communicating with
881 the frontend. Yosys requests data from the frontend by sending exactly
1 line
882 of JSON. Frontend responds with data or error message by replying with exactly
883 1 line of JSON as well.
885 ->
{"method": "modules"
}
886 <-
{"modules":
["<module-name>", ...
]}
887 <-
{"error": "<error-message>"
}
888 request for the list of modules that can be derived by this frontend.
889 the 'hierarchy' command will call back into this frontend if a cell
890 with type <module-name> is instantiated in the design.
892 ->
{"method": "derive", "module": "<module-name">, "parameters":
{
893 "<param-name>":
{"type": "
[unsigned|signed|string|real
]",
894 "value": "<param-value>"
}, ...
}}
895 <-
{"frontend": "
[ilang|verilog|...
]","source": "<source>"
}}
896 <-
{"error": "<error-message>"
}
897 request for the module <module-name> to be derived for a specific set of
898 parameters. <param-name> starts with \ for named parameters, and with $
899 for unnamed parameters, which are numbered starting at
1.<param-value>
900 for integer parameters is always specified as a binary string of unlimited
901 precision. the <source> returned by the frontend is hygienically parsed
902 by a built-in Yosys <frontend>, allowing the RPC frontend to return any
903 convenient representation of the module. the derived module is cached,
904 so the response should be the same whenever the same set of parameters
908 \section{connwrappers -- match width of input-output port pairs
}
909 \label{cmd:connwrappers
}
910 \begin{lstlisting
}[numbers=left,frame=single
]
911 connwrappers
[options
] [selection
]
913 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
914 in wrapper cells with a (larger) constant port size. I.e. the upper bits
915 of the wrapper output are signed/unsigned bit extended. This command uses this
916 knowledge to rewire the inputs of the driven cells to match the output of
919 -signed <cell_type> <port_name> <width_param>
920 -unsigned <cell_type> <port_name> <width_param>
921 consider the specified signed/unsigned wrapper output
923 -port <cell_type> <port_name> <width_param> <sign_param>
924 use the specified parameter to decide if signed or unsigned
926 The options -signed, -unsigned, and -port can be specified multiple times.
929 \section{coolrunner2
\_fixup -- insert necessary buffer cells for CoolRunner-II architecture
}
930 \label{cmd:coolrunner2_fixup
}
931 \begin{lstlisting
}[numbers=left,frame=single
]
932 coolrunner2_fixup
[options
] [selection
]
934 Insert necessary buffer cells for CoolRunner-II architecture.
937 \section{coolrunner2
\_sop -- break \$sop cells into ANDTERM/ORTERM cells
}
938 \label{cmd:coolrunner2_sop
}
939 \begin{lstlisting
}[numbers=left,frame=single
]
940 coolrunner2_sop
[options
] [selection
]
942 Break $sop cells into ANDTERM/ORTERM cells.
945 \section{copy -- copy modules in the design
}
947 \begin{lstlisting
}[numbers=left,frame=single
]
948 copy old_name new_name
950 Copy the specified module. Note that selection patterns are not supported
954 \section{cover -- print code coverage counters
}
956 \begin{lstlisting
}[numbers=left,frame=single
]
957 cover
[options
] [pattern
]
959 Print the code coverage counters collected using the cover() macro in the Yosys
960 C++ code. This is useful to figure out what parts of Yosys are utilized by a
964 Do not print output to the normal destination (console and/or log file)
967 Write output to this file, truncate if exists.
970 Write output to this file, append if exists.
973 Write output to a newly created file in the specified directory.
975 When one or more pattern (shell wildcards) are specified, then only counters
976 matching at least one pattern are printed.
979 It is also possible to instruct Yosys to print the coverage counters on program
980 exit to a file using environment variables:
982 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
984 This will create a file (with an auto-generated name) in this
985 directory and write the coverage counters to it.
987 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
989 This will append the coverage counters to the specified file.
992 Hint: Use the following AWK command to consolidate Yosys coverage files:
994 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
995 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
998 Coverage counters are only available in Yosys for Linux.
1001 \section{cutpoint -- adds formal cut points to the design
}
1002 \label{cmd:cutpoint
}
1003 \begin{lstlisting
}[numbers=left,frame=single
]
1004 cutpoint
[options
] [selection
]
1006 This command adds formal cut points to the design.
1009 set cupoint nets to undef (x). the default behavior is to create a
1010 $anyseq cell and drive the cutpoint net from that
1013 \section{debug -- run command with debug log messages enabled
}
1015 \begin{lstlisting
}[numbers=left,frame=single
]
1018 Execute the specified command with debug log messages enabled
1021 \section{delete -- delete objects in the design
}
1023 \begin{lstlisting
}[numbers=left,frame=single
]
1026 Deletes the selected objects. This will also remove entire modules, if the
1027 whole module is selected.
1030 delete
{-input|-output|-port
} [selection
]
1032 Does not delete any object but removes the input and/or output flag on the
1033 selected wires, thus 'deleting' module ports.
1036 \section{deminout -- demote inout ports to input or output
}
1037 \label{cmd:deminout
}
1038 \begin{lstlisting
}[numbers=left,frame=single
]
1039 deminout
[options
] [selection
]
1041 "Demote" inout ports to input or output ports, if possible.
1044 \section{design -- save, restore and reset current design
}
1046 \begin{lstlisting
}[numbers=left,frame=single
]
1049 Clear the current design.
1054 Save the current design under the given name.
1057 design -stash <name>
1059 Save the current design under the given name and then clear the current design.
1064 Push the current design to the stack and then clear the current design.
1069 Push the current design to the stack without clearing the current design.
1074 Reset the current design and pop the last design from the stack.
1079 Reset the current design and load the design previously saved under the given
1083 design -copy-from <name>
[-as <new_mod_name>
] <selection>
1085 Copy modules from the specified design into the current one. The selection is
1086 evaluated in the other design.
1089 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
1091 Copy modules from the current design into the specified one.
1094 design -import <name>
[-as <new_top_name>
] [selection
]
1096 Import the specified design into the current design. The source design must
1097 either have a selected top module or the selection must contain exactly one
1098 module that is then used as top module for this command.
1103 The Verilog front-end remembers defined macros and top-level declarations
1104 between calls to 'read_verilog'. This command resets this memory.
1107 \section{determine
\_init -- Determine the init value of cells
}
1108 \label{cmd:determine_init
}
1109 \begin{lstlisting
}[numbers=left,frame=single
]
1110 determine_init
[selection
]
1112 Determine the init value of cells that doesn't allow unknown init value.
1115 \section{dff2dffe -- transform \$dff cells to \$dffe cells
}
1116 \label{cmd:dff2dffe
}
1117 \begin{lstlisting
}[numbers=left,frame=single
]
1118 dff2dffe
[options
] [selection
]
1120 This pass transforms $dff cells driven by a tree of multiplexers with one or
1121 more feedback paths to $dffe cells. It also works on gate-level cells such as
1122 $_DFF_P_, $_DFF_N_ and $_MUX_.
1125 operate in the opposite direction: replace $dffe cells with combinations
1126 of $dff and $mux cells. the options below are ignored in unmap mode.
1129 Same as -unmap but only unmap $dffe where the clock enable port
1130 signal is used by less $dffe than the specified number
1132 -direct <internal_gate_type> <external_gate_type>
1133 map directly to external gate type. <internal_gate_type> can
1134 be any internal gate-level FF cell (except $_DFFE_??_). the
1135 <external_gate_type> is the cell type name for a cell with an
1136 identical interface to the <internal_gate_type>, except it
1137 also has an high-active enable port 'E'.
1138 Usually <external_gate_type> is an intermediate cell type
1139 that is then translated to the final type using 'techmap'.
1141 -direct-match <pattern>
1142 like -direct for all DFF cell types matching the expression.
1143 this will use $__DFFE_* as <external_gate_type> matching the
1144 internal gate type $_DFF_*_, and $__DFFSE_* for those matching
1145 $_DFFS_*_, except for $_DFF_
[NP
]_, which is converted to
1149 \section{dff2dffs -- process sync set/reset with SR over CE priority
}
1150 \label{cmd:dff2dffs
}
1151 \begin{lstlisting
}[numbers=left,frame=single
]
1152 dff2dffs
[options
] [selection
]
1154 Merge synchronous set/reset $_MUX_ cells to create $__DFFS_
[NP
][NP
][01], to be run before
1155 dff2dffe for SR over CE priority.
1158 Disallow merging synchronous set/reset that has polarity opposite of the
1159 output wire's init attribute (if any).
1162 \section{dffinit -- set INIT param on FF cells
}
1164 \begin{lstlisting
}[numbers=left,frame=single
]
1165 dffinit
[options
] [selection
]
1167 This pass sets an FF cell parameter to the the initial value of the net it
1168 drives. (This is primarily used in FPGA flows.)
1170 -ff <cell_name> <output_port> <init_param>
1171 operate on the specified cell type. this option can be used
1175 use the string values "high" and "low" to represent a single-bit
1176 initial value of
1 or
0. (multi-bit values are not supported in this
1179 -strinit <string for high> <string for low>
1180 use string values in the command line to represent a single-bit
1181 initial value of
1 or
0. (multi-bit values are not supported in this
1185 fail if the FF cell has already a defined initial value set in other
1186 passes and the initial value of the net it drives is not equal to
1187 the already defined initial value.
1190 \section{dfflibmap -- technology mapping of flip-flops
}
1191 \label{cmd:dfflibmap
}
1192 \begin{lstlisting
}[numbers=left,frame=single
]
1193 dfflibmap
[-prepare
] -liberty <file>
[selection
]
1195 Map internal flip-flop cells to the flip-flop cells in the technology
1196 library specified in the given liberty file.
1198 This pass may add inverters as needed. Therefore it is recommended to
1199 first run this pass and then map the logic paths to the target technology.
1201 When called with -prepare, this command will convert the internal FF cells
1202 to the internal cell types that best match the cells found in the given
1206 \section{dump -- print parts of the design in ilang format
}
1208 \begin{lstlisting
}[numbers=left,frame=single
]
1209 dump
[options
] [selection
]
1211 Write the selected parts of the design to the console or specified file in
1215 also dump the module headers, even if only parts of a single
1219 only dump the module headers if the entire module is selected
1222 write to the specified file.
1225 like -outfile but append instead of overwrite
1228 \section{echo -- turning echoing back of commands on and off
}
1230 \begin{lstlisting
}[numbers=left,frame=single
]
1233 Print all commands to log before executing them.
1238 Do not print all commands to log before executing them. (default)
1241 \section{ecp5
\_ffinit -- ECP5: handle FF init values
}
1242 \label{cmd:ecp5_ffinit
}
1243 \begin{lstlisting
}[numbers=left,frame=single
]
1244 ecp5_ffinit
[options
] [selection
]
1246 Remove init values for FF output signals when equal to reset value.
1247 If reset is not used, set the reset value to the init value, otherwise
1248 unmap out the reset (if not an async reset).
1251 \section{ecp5
\_gsr -- ECP5: handle GSR
}
1252 \label{cmd:ecp5_gsr
}
1253 \begin{lstlisting
}[numbers=left,frame=single
]
1254 ecp5_gsr
[options
] [selection
]
1256 Trim active low async resets connected to GSR and resolve GSR parameter,
1257 if a GSR or SGSR primitive is used in the design.
1259 If any cell has the GSR parameter set to "AUTO", this will be resolved
1260 to "ENABLED" if a GSR primitive is present and the
(* nogsr *) attribute
1261 is not set, otherwise it will be resolved to "DISABLED".
1264 \section{edgetypes -- list all types of edges in selection
}
1265 \label{cmd:edgetypes
}
1266 \begin{lstlisting
}[numbers=left,frame=single
]
1267 edgetypes
[options
] [selection
]
1269 This command lists all unique types of 'edges' found in the selection. An 'edge'
1270 is a
4-tuple of source and sink cell type and port name.
1273 \section{efinix
\_fixcarry -- Efinix: fix carry chain
}
1274 \label{cmd:efinix_fixcarry
}
1275 \begin{lstlisting
}[numbers=left,frame=single
]
1276 efinix_fixcarry
[options
] [selection
]
1278 Add Efinix adders to fix carry chain if needed.
1281 \section{efinix
\_gbuf -- Efinix: insert global clock buffers
}
1282 \label{cmd:efinix_gbuf
}
1283 \begin{lstlisting
}[numbers=left,frame=single
]
1284 efinix_gbuf
[options
] [selection
]
1286 Add Efinix global clock buffers to top module as needed.
1289 \section{equiv
\_add -- add a \$equiv cell
}
1290 \label{cmd:equiv_add
}
1291 \begin{lstlisting
}[numbers=left,frame=single
]
1292 equiv_add
[-try
] gold_sig gate_sig
1294 This command adds an $equiv cell for the specified signals.
1297 equiv_add
[-try
] -cell gold_cell gate_cell
1299 This command adds $equiv cells for the ports of the specified cells.
1302 \section{equiv
\_induct -- proving \$equiv cells using temporal induction
}
1303 \label{cmd:equiv_induct
}
1304 \begin{lstlisting
}[numbers=left,frame=single
]
1305 equiv_induct
[options
] [selection
]
1307 Uses a version of temporal induction to prove $equiv cells.
1309 Only selected $equiv cells are proven and only selected cells are used to
1313 enable modelling of undef states
1316 the max. number of time steps to be considered (default =
4)
1318 This command is very effective in proving complex sequential circuits, when
1319 the internal state of the circuit quickly propagates to $equiv cells.
1321 However, this command uses a weak definition of 'equivalence': This command
1322 proves that the two circuits will not diverge after they produce equal
1323 outputs (observable points via $equiv) for at least <N> cycles (the <N>
1324 specified via -seq).
1326 Combined with simulation this is very powerful because simulation can give
1327 you confidence that the circuits start out synced for at least <N> cycles
1331 \section{equiv
\_make -- prepare a circuit for equivalence checking
}
1332 \label{cmd:equiv_make
}
1333 \begin{lstlisting
}[numbers=left,frame=single
]
1334 equiv_make
[options
] gold_module gate_module equiv_module
1336 This creates a module annotated with $equiv cells from two presumably
1337 equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
1338 to work with the created equivalent checking module.
1341 Also match cells and wires with $... names.
1344 Do not match cells or signals that match the names in the file.
1347 Match FSM encodings using the description from the file.
1348 See 'help fsm_recode' for details.
1350 Note: The circuit created by this command is not a miter (with something like
1351 a trigger output), but instead uses $equiv cells to encode the equivalence
1352 checking problem. Use 'miter -equiv' if you want to create a miter circuit.
1355 \section{equiv
\_mark -- mark equivalence checking regions
}
1356 \label{cmd:equiv_mark
}
1357 \begin{lstlisting
}[numbers=left,frame=single
]
1358 equiv_mark
[options
] [selection
]
1360 This command marks the regions in an equivalence checking module. Region
0 is
1361 the proven part of the circuit. Regions with higher numbers are connected
1362 unproven subcricuits. The integer attribute 'equiv_region' is set on all
1366 \section{equiv
\_miter -- extract miter from equiv circuit
}
1367 \label{cmd:equiv_miter
}
1368 \begin{lstlisting
}[numbers=left,frame=single
]
1369 equiv_miter
[options
] miter_module
[selection
]
1371 This creates a miter module for further analysis of the selected $equiv cells.
1374 Create a trigger output
1377 Create cmp_* outputs for individual unproven $equiv cells
1380 Create a $assert cell for each unproven $equiv cell
1383 Create compare logic that handles undefs correctly
1386 \section{equiv
\_opt -- prove equivalence for optimized circuit
}
1387 \label{cmd:equiv_opt
}
1388 \begin{lstlisting
}[numbers=left,frame=single
]
1389 equiv_opt
[options
] [command
]
1391 This command uses temporal induction to check circuit equivalence before and
1392 after an optimization pass.
1394 -run <from_label>:<to_label>
1395 only run the commands between the labels (see below). an empty
1396 from label is synonymous to the start of the command list, and empty to
1397 label is synonymous to the end of the command list.
1400 expand the modules in this file before proving equivalence. this is
1401 useful for handling architecture-specific primitives.
1404 Do not match cells or signals that match the names in the file
1405 (passed to equiv_make).
1408 produce an error if the circuits are not equivalent.
1411 run clk2fflogic before equivalence checking.
1414 run async2sync before equivalence checking.
1417 enable modelling of undef states during equiv_induct.
1419 The following commands are executed by this verification command:
1425 design -stash postopt
1428 design -copy-from preopt -as gold A:top
1429 design -copy-from postopt -as gate A:top
1431 techmap: (only with -map)
1432 techmap -wb -D EQUIV -autoproc -map <filename> ...
1435 clk2fflogic (only with -multiclock)
1436 async2sync (only with -async2sync)
1437 equiv_make -blacklist <filename> ... gold gate equiv
1438 equiv_induct
[-undef
] equiv
1439 equiv_status
[-assert
] equiv
1445 \section{equiv
\_purge -- purge equivalence checking module
}
1446 \label{cmd:equiv_purge
}
1447 \begin{lstlisting
}[numbers=left,frame=single
]
1448 equiv_purge
[options
] [selection
]
1450 This command removes the proven part of an equivalence checking module, leaving
1451 only the unproven segments in the design. This will also remove and add module
1455 \section{equiv
\_remove -- remove \$equiv cells
}
1456 \label{cmd:equiv_remove
}
1457 \begin{lstlisting
}[numbers=left,frame=single
]
1458 equiv_remove
[options
] [selection
]
1460 This command removes the selected $equiv cells. If neither -gold nor -gate is
1461 used then only proven cells are removed.
1470 \section{equiv
\_simple -- try proving simple \$equiv instances
}
1471 \label{cmd:equiv_simple
}
1472 \begin{lstlisting
}[numbers=left,frame=single
]
1473 equiv_simple
[options
] [selection
]
1475 This command tries to prove $equiv cells using a simple direct SAT approach.
1481 enable modelling of undef states
1484 create shorter input cones that stop at shared nodes. This yields
1485 simpler SAT problems but sometimes fails to prove equivalence.
1488 disabling grouping of $equiv cells by output wire
1491 the max. number of time steps to be considered (default =
1)
1494 \section{equiv
\_status -- print status of equivalent checking module
}
1495 \label{cmd:equiv_status
}
1496 \begin{lstlisting
}[numbers=left,frame=single
]
1497 equiv_status
[options
] [selection
]
1499 This command prints status information for all selected $equiv cells.
1502 produce an error if any unproven $equiv cell is found
1505 \section{equiv
\_struct -- structural equivalence checking
}
1506 \label{cmd:equiv_struct
}
1507 \begin{lstlisting
}[numbers=left,frame=single
]
1508 equiv_struct
[options
] [selection
]
1510 This command adds additional $equiv cells based on the assumption that the
1511 gold and gate circuit are structurally equivalent. Note that this can introduce
1512 bad $equiv cells in cases where the netlists are not structurally equivalent,
1513 for example when analyzing circuits with cells with commutative inputs. This
1514 command will also de-duplicate gates.
1517 by default this command performans forward sweeps until nothing can
1518 be merged by forwards sweeps, then backward sweeps until forward
1519 sweeps are effective again. with this option set only forward sweeps
1523 add the specified cell type to the list of cell types that are only
1524 merged in forward sweeps and never in backward sweeps. $equiv is in
1525 this list automatically.
1528 by default, the internal RTL and gate cell types are ignored. add
1529 this option to also process those cell types with this command.
1532 maximum number of iterations to run before aborting
1535 \section{eval -- evaluate the circuit given an input
}
1537 \begin{lstlisting
}[numbers=left,frame=single
]
1538 eval
[options
] [selection
]
1540 This command evaluates the value of a signal given the value of all required
1543 -set <signal> <value>
1544 set the specified signal to the specified value.
1547 set all unspecified source signals to undef (x)
1550 create a truth table using the specified input signals
1553 show the value for the specified signal. if no -show option is passed
1554 then all output ports of the current module are used.
1557 \section{exec -- execute commands in the operating system shell
}
1559 \begin{lstlisting
}[numbers=left,frame=single
]
1560 exec
[options
] --
[command
]
1562 Execute a command in the operating system shell. All supplied arguments are
1563 concatenated and passed as a command to popen(
3). Whitespace is not guaranteed
1564 to be preserved, even if quoted. stdin and stderr are not connected, while stdout is
1565 logged unless the "-q" option is specified.
1569 Suppress stdout and stderr from subprocess
1571 -expect-return <int>
1572 Generate an error if popen() does not return specified value.
1573 May only be specified once; the final specified value is controlling
1574 if specified multiple times.
1576 -expect-stdout <regex>
1577 Generate an error if the specified regex does not match any line
1578 in subprocess's stdout. May be specified multiple times.
1580 -not-expect-stdout <regex>
1581 Generate an error if the specified regex matches any line
1582 in subprocess's stdout. May be specified multiple times.
1585 Example: exec -q -expect-return
0 -- echo "bananapie" | grep "nana"
1588 \section{expose -- convert internal signals to module ports
}
1590 \begin{lstlisting
}[numbers=left,frame=single
]
1591 expose
[options
] [selection
]
1593 This command exposes all selected internal signals of a module as additional
1597 only consider wires that are directly driven by register cell.
1600 when exposing a wire, create an input/output pair and cut the internal
1601 signal path at that wire.
1604 when exposing a wire, create an input port and disconnect the internal
1608 only expose those signals that are shared among the selected modules.
1609 this is useful for preparing modules for equivalence checking.
1612 also turn connections to instances of other modules to additional
1613 inputs and outputs and remove the module instances.
1616 turn flip-flops to sets of inputs and outputs.
1619 when creating new wire/port names, the original object name is suffixed
1620 with this separator (default: '.') and the port name or a type
1621 designator for the exposed signal.
1624 \section{extract -- find subcircuits and replace them with cells
}
1626 \begin{lstlisting
}[numbers=left,frame=single
]
1627 extract -map <map_file>
[options
] [selection
]
1628 extract -mine <out_file>
[options
] [selection
]
1630 This pass looks for subcircuits that are isomorphic to any of the modules
1631 in the given map file and replaces them with instances of this modules. The
1632 map file can be a Verilog source file
(*.v) or an ilang file (*.il).
1635 use the modules in this file as reference. This option can be used
1639 use the modules in this in-memory design as reference. This option can
1640 be used multiple times.
1643 print debug output while analyzing
1646 also find instances with constant drivers. this may be much
1647 slower than the normal operation.
1650 normally builtin port swapping rules for internal cells are used per
1651 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
1652 when this option is used.
1654 -compat <needle_type> <haystack_type>
1655 Per default, the cells in the map file (needle) must have the
1656 type as the cells in the active design (haystack). This option
1657 can be used to register additional pairs of types that should
1658 match. This option can be used multiple times.
1660 -swap <needle_type> <port1>,<port2>[,...]
1661 Register a set of swappable ports for a needle cell type.
1662 This option can be used multiple times.
1664 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
1665 Register a valid permutation of swappable ports for a needle
1666 cell type. This option can be used multiple times.
1668 -cell_attr <attribute_name>
1669 Attributes on cells with the given name must match.
1671 -wire_attr <attribute_name>
1672 Attributes on wires with the given name must match.
1675 Do not use parameters when matching cells.
1677 -ignore_param <cell_type> <parameter_name>
1678 Do not use this parameter when matching cells.
1680 This pass does not operate on modules with unprocessed processes in it.
1681 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
1683 This pass can also be used for mining for frequent subcircuits. In this mode
1684 the following options are to be used instead of the -map option.
1687 mine for frequent subcircuits and write them to the given ilang file
1689 -mine_cells_span <min> <max>
1690 only mine for subcircuits with the specified number of cells
1693 -mine_min_freq <num>
1694 only mine for subcircuits with at least the specified number of matches
1697 -mine_limit_matches_per_module <num>
1698 when calculating the number of matches for a subcircuit, don't count
1699 more than the specified number of matches per module
1701 -mine_max_fanout <num>
1702 don't consider internal signals with more than <num> connections
1704 The modules in the map file may have the attribute 'extract_order' set to an
1705 integer value. Then this value is used to determine the order in which the pass
1706 tries to map the modules to the design (ascending, default value is 0).
1708 See 'help techmap' for a pass that does the opposite thing.
1711 \section{extract\_counter -- Extract GreenPak4 counter cells}
1712 \label{cmd:extract_counter}
1713 \begin{lstlisting}[numbers=left,frame=single]
1714 extract_counter [options] [selection]
1716 This pass converts non-resettable or async resettable down counters to
1717 counter cells. Use a target-specific 'techmap' map file to convert those cells
1718 to the actual target cells.
1721 Only extract counters up to N bits wide (default 64)
1724 Only extract counters at least N bits wide (default 2)
1727 Allow counters to have async reset (default yes)
1730 Look for up-counters, down-counters, or both (default down)
1733 Only allow parallel output from the counter to the listed cell types
1734 (if not specified, parallel outputs are not restricted)
1737 \section{extract\_fa -- find and extract full/half adders}
1738 \label{cmd:extract_fa}
1739 \begin{lstlisting}[numbers=left,frame=single]
1740 extract_fa [options] [selection]
1742 This pass extracts full/half adders from a gate-level design.
1745 Enable cell types (fa=full adder, ha=half adder)
1746 All types are enabled if none of this options is used
1749 Set maximum depth for extracted logic cones (default=20)
1752 Set maximum breadth for extracted logic cones (default=6)
1758 \section{extract\_reduce -- converts gate chains into \$reduce\_* cells}
1759 \label{cmd:extract_reduce}
1760 \begin{lstlisting}[numbers=left,frame=single]
1761 extract_reduce [options] [selection]
1763 converts gate chains into $reduce_* cells
1765 This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them
1766 with their corresponding $reduce_* cells. Because this command only operates on
1767 these cell types, it is recommended to map the design to only these cell types
1768 using the `abc -g` command. Note that, in some cases, it may be more effective
1769 to map the design to only $_AND_ cells, run extract_reduce, map the remaining
1770 parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.
1773 Allows matching of cells that have loads outside the chain. These cells
1774 will be replicated and folded into the $reduce_* cell, but the original
1775 cell will remain, driving its original loads.
1778 \section{extractinv -- extract explicit inverter cells for invertible cell pins}
1779 \label{cmd:extractinv}
1780 \begin{lstlisting}[numbers=left,frame=single]
1781 extractinv [options] [selection]
1783 Searches the design for all cells with invertible pins controlled by a cell
1784 parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.
1785 If the parameter was set to 1, inserts an explicit inverter cell in front of
1786 the pin instead. Normally used for output to ISE, which does not support the
1787 inversion parameters.
1789 To mark a cell port as invertible, use (* invertible_pin = "param_name" *)
1790 on the wire in the blackbox module. The parameter value should have
1791 the same width as the port, and will be effectively XORed with it.
1793 -inv <celltype> <portname_out>:<portname_in>
1794 Specifies the cell type to use for the inverters and its port names.
1795 This option is required.
1798 \section{flatten -- flatten design
}
1800 \begin{lstlisting
}[numbers=left,frame=single
]
1801 flatten
[options
] [selection
]
1803 This pass flattens the design by replacing cells by their implementation. This
1804 pass is very similar to the 'techmap' pass. The only difference is that this
1805 pass is using the current design as mapping library.
1807 Cells and/or modules with the 'keep_hierarchy' attribute set will not be
1808 flattened by this command.
1811 Ignore the 'whitebox' attribute on cell implementations.
1814 \section{flowmap -- pack LUTs with FlowMap
}
1816 \begin{lstlisting
}[numbers=left,frame=single
]
1817 flowmap
[options
] [selection
]
1819 This pass uses the FlowMap technology mapping algorithm to pack logic gates
1820 into k-LUTs with optimal depth. It allows mapping any circuit elements that can
1821 be evaluated with the `eval` pass, including cells with multiple output ports
1822 and multi-bit input and output ports.
1825 perform technology mapping for a k-LUT architecture. if not specified,
1829 only produce n-input or larger LUTs. if not specified, defaults to
1.
1831 -cells <cell>
[,<cell>,...
]
1832 map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,
1833 $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.
1836 perform depth relaxation and area minimization.
1838 -r-alpha n, -r-beta n, -r-gamma n
1839 parameters of depth relaxation heuristic potential function.
1840 if not specified, alpha=
8, beta=
2, gamma=
1.
1843 optimize for area by trading off at most n logic levels for fewer LUTs.
1844 n may be zero, to optimize for area without increasing depth.
1848 dump intermediate graphs.
1851 explain decisions performed during depth relaxation.
1854 \section{fmcombine -- combine two instances of a cell into one
}
1855 \label{cmd:fmcombine
}
1856 \begin{lstlisting
}[numbers=left,frame=single
]
1857 fmcombine
[options
] module_name gold_cell gate_cell
1859 This pass takes two cells, which are instances of the same module, and replaces
1860 them with one instance of a special 'combined' module, that effectively
1861 contains two copies of the original module, plus some formal properties.
1863 This is useful for formal test benches that check what differences in behavior
1864 a slight difference in input causes in a module.
1867 Insert assumptions that initially all FFs in both circuits have the
1868 same initial values.
1871 Do not duplicate $anyseq/$anyconst cells.
1874 Insert forward hint assumptions into the combined module.
1877 Insert backward hint assumptions into the combined module.
1878 (Backward hints are logically equivalend to fordward hits, but
1879 some solvers are faster with bwd hints, or even both -bwd and -fwd.)
1882 Don't insert hint assumptions into the combined module.
1883 (This should not provide any speedup over the original design, but
1884 strangely sometimes it does.)
1886 If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.
1889 \section{fminit -- set init values/sequences for formal
}
1891 \begin{lstlisting
}[numbers=left,frame=single
]
1892 fminit
[options
] <selection>
1894 This pass creates init constraints (for example for reset sequences) in a formal
1897 -seq <signal> <sequence>
1898 Set sequence using comma-separated list of values, use 'z for
1899 unconstrained bits. The last value is used for the remainder of the
1902 -set <signal> <value>
1903 Add constant value constraint
1907 Set clock for init sequences
1910 \section{freduce -- perform functional reduction
}
1912 \begin{lstlisting
}[numbers=left,frame=single
]
1913 freduce
[options
] [selection
]
1915 This pass performs functional reduction in the circuit. I.e. if two nodes are
1916 equivalent, they are merged to one node and one of the redundant drivers is
1917 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
1920 enable verbose or very verbose output
1923 enable explicit handling of inverted signals
1926 stop after <n> reduction operations. this is mostly used for
1927 debugging the freduce command itself.
1930 dump the design to <prefix>_<module>_<num>.il after each reduction
1931 operation. this is mostly used for debugging the freduce command.
1933 This pass is undef-aware, i.e. it considers don't-care values for detecting
1936 All selected wires are considered for rewiring. The selected cells cover the
1937 circuit that is analyzed.
1940 \section{fsm -- extract and optimize finite state machines
}
1942 \begin{lstlisting
}[numbers=left,frame=single
]
1943 fsm
[options
] [selection
]
1945 This pass calls all the other fsm_* passes in a useful order. This performs
1946 FSM extraction and optimization. It also calls opt_clean as needed:
1948 fsm_detect unless got option -nodetect
1955 fsm_expand if got option -expand
1956 opt_clean if got option -expand
1957 fsm_opt if got option -expand
1959 fsm_recode unless got option -norecode
1963 fsm_export if got option -export
1964 fsm_map unless got option -nomap
1968 -expand, -norecode, -export, -nomap
1969 enable or disable passes as indicated above
1972 call expand with -full option
1975 -fm_set_fsm_file file
1977 passed through to fsm_recode pass
1980 \section{fsm
\_detect -- finding FSMs in design
}
1981 \label{cmd:fsm_detect
}
1982 \begin{lstlisting
}[numbers=left,frame=single
]
1983 fsm_detect
[selection
]
1985 This pass detects finite state machines by identifying the state signal.
1986 The state signal is then marked by setting the attribute 'fsm_encoding'
1987 on the state signal to "auto".
1989 Existing 'fsm_encoding' attributes are not changed by this pass.
1991 Signals can be protected from being detected by this pass by setting the
1992 'fsm_encoding' attribute to "none".
1995 \section{fsm
\_expand -- expand FSM cells by merging logic into it
}
1996 \label{cmd:fsm_expand
}
1997 \begin{lstlisting
}[numbers=left,frame=single
]
1998 fsm_expand
[-full
] [selection
]
2000 The fsm_extract pass is conservative about the cells that belong to a finite
2001 state machine. This pass can be used to merge additional auxiliary gates into
2002 the finite state machine.
2004 By default, fsm_expand is still a bit conservative regarding merging larger
2005 word-wide cells. Call with -full to consider all cells for merging.
2008 \section{fsm
\_export -- exporting FSMs to KISS2 files
}
2009 \label{cmd:fsm_export
}
2010 \begin{lstlisting
}[numbers=left,frame=single
]
2011 fsm_export
[-noauto
] [-o filename
] [-origenc
] [selection
]
2013 This pass creates a KISS2 file for every selected FSM. For FSMs with the
2014 'fsm_export' attribute set, the attribute value is used as filename, otherwise
2015 the module and cell name is used as filename. If the parameter '-o' is given,
2016 the first exported FSM is written to the specified filename. This overwrites
2017 the setting as specified with the 'fsm_export' attribute. All other FSMs are
2018 exported to the default name as mentioned above.
2021 only export FSMs that have the 'fsm_export' attribute set
2024 filename of the first exported FSM
2027 use binary state encoding as state names instead of s0, s1, ...
2030 \section{fsm
\_extract -- extracting FSMs in design
}
2031 \label{cmd:fsm_extract
}
2032 \begin{lstlisting
}[numbers=left,frame=single
]
2033 fsm_extract
[selection
]
2035 This pass operates on all signals marked as FSM state signals using the
2036 'fsm_encoding' attribute. It consumes the logic that creates the state signal
2037 and uses the state signal to generate control signal and replaces it with an
2040 The generated FSM cell still generates the original state signal with its
2041 original encoding. The 'fsm_opt' pass can be used in combination with the
2042 'opt_clean' pass to eliminate this signal.
2045 \section{fsm
\_info -- print information on finite state machines
}
2046 \label{cmd:fsm_info
}
2047 \begin{lstlisting
}[numbers=left,frame=single
]
2048 fsm_info
[selection
]
2050 This pass dumps all internal information on FSM cells. It can be useful for
2051 analyzing the synthesis process and is called automatically by the 'fsm'
2052 pass so that this information is included in the synthesis log file.
2055 \section{fsm
\_map -- mapping FSMs to basic logic
}
2057 \begin{lstlisting
}[numbers=left,frame=single
]
2060 This pass translates FSM cells to flip-flops and logic.
2063 \section{fsm
\_opt -- optimize finite state machines
}
2065 \begin{lstlisting
}[numbers=left,frame=single
]
2068 This pass optimizes FSM cells. It detects which output signals are actually
2069 not used and removes them from the FSM. This pass is usually used in
2070 combination with the 'opt_clean' pass (see also 'help fsm').
2073 \section{fsm
\_recode -- recoding finite state machines
}
2074 \label{cmd:fsm_recode
}
2075 \begin{lstlisting
}[numbers=left,frame=single
]
2076 fsm_recode
[options
] [selection
]
2078 This pass reassign the state encodings for FSM cells. At the moment only
2079 one-hot encoding and binary encoding is supported.
2081 specify the encoding scheme used for FSMs without the
2082 'fsm_encoding' attribute or with the attribute set to `auto'.
2084 -fm_set_fsm_file <file>
2085 generate a file containing the mapping from old to new FSM encoding
2086 in form of Synopsys Formality set_fsm_* commands.
2089 write the mappings from old to new FSM encoding to a file in the
2092 .fsm <module_name> <state_signal>
2093 .map <old_bitpattern> <new_bitpattern>
2096 \section{greenpak4
\_dffinv -- merge greenpak4 inverters and DFF/latches
}
2097 \label{cmd:greenpak4_dffinv
}
2098 \begin{lstlisting
}[numbers=left,frame=single
]
2099 greenpak4_dffinv
[options
] [selection
]
2101 Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.
2104 \section{help -- display help messages
}
2106 \begin{lstlisting
}[numbers=left,frame=single
]
2107 help ................ list all commands
2108 help <command> ...... print help message for given command
2109 help -all ........... print complete command reference
2111 help -cells .......... list all cell types
2112 help <celltype> ..... print help message for given cell type
2113 help <celltype>+ .... print verilog code for given cell type
2116 \section{hierarchy -- check, expand and clean up design hierarchy
}
2117 \label{cmd:hierarchy
}
2118 \begin{lstlisting
}[numbers=left,frame=single
]
2119 hierarchy
[-check
] [-top <module>
]
2120 hierarchy -generate <cell-types> <port-decls>
2122 In parametric designs, a module might exists in several variations with
2123 different parameter values. This pass looks at all modules in the current
2124 design an re-runs the language frontends for the parametric modules as
2125 needed. It also resolves assignments to wired logic data types (wand/wor),
2126 resolves positional module parameters, unroll array instances, and more.
2129 also check the design hierarchy. this generates an error when
2130 an unknown module is used as cell type.
2133 like -check, but also throw an error if blackbox modules are
2134 instantiated, and throw an error if the design has no top module.
2137 by default the hierarchy command will not remove library (blackbox)
2138 modules. use this option to also remove unused blackbox modules.
2141 search for files named <module_name>.v in the specified directory
2142 for unknown modules and automatically run read_verilog for each
2146 per default this pass also converts positional arguments in cells
2147 to arguments using port names. This option disables this behavior.
2150 per default this pass adjusts the port width on cells that are
2151 module instances when the width does not match the module port. This
2152 option disables this behavior.
2155 do not resolve input port default values
2158 per default this pass sets the "keep" attribute on all modules
2159 that directly or indirectly contain one or more formal properties.
2160 This option disables this behavior.
2163 use the specified top module to build the design hierarchy. Modules
2164 outside this tree (unused modules) are removed.
2166 when the -top option is used, the 'top' attribute will be set on the
2167 specified top module. otherwise a module with the 'top' attribute set
2168 will implicitly be used as top module, if such a module exists.
2171 automatically determine the top of the design hierarchy and mark it.
2174 elaborate the top module using this parameter value. Modules on which
2175 this parameter does not exist may cause a warning message to be output.
2176 This option can be specified multiple times to override multiple
2177 parameters. String values must be passed in double quotes (").
2179 In -generate mode this pass generates blackbox modules for the given cell
2180 types (wildcards supported). For this the design is searched for cells that
2181 match the given types and then the given port declarations are used to
2182 determine the direction of the ports. The syntax for a port declaration is:
2184 {i|o|io
}[@<num>
]:<portname>
2186 Input ports are specified with the 'i' prefix, output ports with the 'o'
2187 prefix and inout ports with the 'io' prefix. The optional <num> specifies
2188 the position of the port in the parameter list (needed when instantiated
2189 using positional arguments). When <num> is not specified, the <portname> can
2190 also contain wildcard characters.
2192 This pass ignores the current selection and always operates on all modules
2193 in the current design.
2196 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers
}
2198 \begin{lstlisting
}[numbers=left,frame=single
]
2199 hilomap
[options
] [selection
]
2201 Map constants to 'tielo' and 'tiehi' driver cells.
2203 -hicell <celltype> <portname>
2204 Replace constant hi bits with this cell.
2206 -locell <celltype> <portname>
2207 Replace constant lo bits with this cell.
2210 Create only one hi/lo cell and connect all constant bits
2211 to that cell. Per default a separate cell is created for
2215 \section{history -- show last interactive commands
}
2217 \begin{lstlisting
}[numbers=left,frame=single
]
2220 This command prints all commands in the shell history buffer. This are
2221 all commands executed in an interactive session, but not the commands
2222 from executed scripts.
2225 \section{ice40
\_braminit -- iCE40: perform SB
\_RAM40\_4K initialization from file
}
2226 \label{cmd:ice40_braminit
}
2227 \begin{lstlisting
}[numbers=left,frame=single
]
2230 This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE
2231 parameter and converts it into the required INIT_x attributes
2234 \section{ice40
\_dsp -- iCE40: map multipliers
}
2235 \label{cmd:ice40_dsp
}
2236 \begin{lstlisting
}[numbers=left,frame=single
]
2237 ice40_dsp
[options
] [selection
]
2239 Map multipliers ($mul/SB_MAC16) and multiply-accumulate ($mul/SB_MAC16 + $add)
2240 cells into iCE40 DSP resources.
2241 Currently, only the
16x16 multiply mode is supported and not the
2 x
8x8 mode.
2243 Pack input registers (A, B,
{C,D
}; with optional hold), pipeline registers
2244 (
{F,J,K,G
}, H), output registers (O -- full
32-bits or lower
16-bits only; with
2245 optional hold), and post-adder into into the SB_MAC16 resource.
2247 Multiply-accumulate operations using the post-adder with feedback on the
{C,D
}
2248 input will be folded into the DSP. In this scenario only, resetting the
2249 the accumulator to an arbitrary value can be inferred to use the
{C,D
} input.
2252 \section{ice40
\_ffinit -- iCE40: handle FF init values
}
2253 \label{cmd:ice40_ffinit
}
2254 \begin{lstlisting
}[numbers=left,frame=single
]
2255 ice40_ffinit
[options
] [selection
]
2257 Remove zero init values for FF output signals. Add inverters to implement
2258 nonzero init values.
2261 \section{ice40
\_ffssr -- iCE40: merge synchronous set/reset into FF cells
}
2262 \label{cmd:ice40_ffssr
}
2263 \begin{lstlisting
}[numbers=left,frame=single
]
2264 ice40_ffssr
[options
] [selection
]
2266 Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.
2269 \section{ice40
\_opt -- iCE40: perform simple optimizations
}
2270 \label{cmd:ice40_opt
}
2271 \begin{lstlisting
}[numbers=left,frame=single
]
2272 ice40_opt
[options
] [selection
]
2274 This command executes the following script:
2277 <ice40 specific optimizations>
2278 opt_expr -mux_undef -undriven
[-full
]
2282 while <changed design>
2285 \section{ice40
\_wrapcarry -- iCE40: wrap carries
}
2286 \label{cmd:ice40_wrapcarry
}
2287 \begin{lstlisting
}[numbers=left,frame=single
]
2288 ice40_wrapcarry
[selection
]
2290 Wrap manually instantiated SB_CARRY cells, along with their associated SB_LUT4s,
2291 into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology
2294 Attributes on both cells will have their names prefixed with 'SB_CARRY.' or
2295 'SB_LUT4.' and attached to the wrapping cell.
2296 A
(* keep *) attribute on either cell will be logically OR-ed together.
2299 unwrap $__ICE40_CARRY_WRAPPER cells back into SB_CARRYs and SB_LUT4s,
2300 including restoring their attributes.
2303 \section{insbuf -- insert buffer cells for connected wires
}
2305 \begin{lstlisting
}[numbers=left,frame=single
]
2306 insbuf
[options
] [selection
]
2308 Insert buffer cells into the design for directly connected wires.
2310 -buf <celltype> <in-portname> <out-portname>
2311 Use the given cell type instead of $_BUF_. (Notice that the next
2312 call to "clean" will remove all $_BUF_ in the design.)
2315 \section{iopadmap -- technology mapping of i/o pads (or buffers)
}
2316 \label{cmd:iopadmap
}
2317 \begin{lstlisting
}[numbers=left,frame=single
]
2318 iopadmap
[options
] [selection
]
2320 Map module inputs/outputs to PAD cells from a library. This pass
2321 can only map to very simple PAD cells. Use 'techmap' to further map
2322 the resulting cells to more sophisticated PAD cells.
2324 -inpad <celltype> <portname>
[:<portname>
]
2325 Map module input ports to the given cell type with the
2326 given output port name. if a
2nd portname is given, the
2327 signal is passed through the pad call, using the
2nd
2328 portname as the port facing the module port.
2330 -outpad <celltype> <portname>
[:<portname>
]
2331 -inoutpad <celltype> <portname>
[:<portname>
]
2332 Similar to -inpad, but for output and inout ports.
2334 -toutpad <celltype> <portname>:<portname>
[:<portname>
]
2335 Merges $_TBUF_ cells into the output pad cell. This takes precedence
2336 over the other -outpad cell. The first portname is the enable input
2337 of the tristate driver.
2339 -tinoutpad <celltype> <portname>:<portname>:<portname>
[:<portname>
]
2340 Merges $_TBUF_ cells into the inout pad cell. This takes precedence
2341 over the other -inoutpad cell. The first portname is the enable input
2342 of the tristate driver and the
2nd portname is the internal output
2343 buffering the external signal.
2345 -ignore <celltype> <portname>
[:<portname>
]*
2346 Skips mapping inputs/outputs that are already connected to given
2347 ports of the given cell. Can be used multiple times. This is in
2348 addition to the cells specified as mapping targets.
2350 -widthparam <param_name>
2351 Use the specified parameter name to set the port width.
2353 -nameparam <param_name>
2354 Use the specified parameter to set the port name.
2357 create individual bit-wide buffers even for ports that
2358 are wider. (the default behavior is to create word-wide
2359 buffers using -widthparam to set the word size on the cell.)
2361 Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.
2364 \section{json -- write design in JSON format
}
2366 \begin{lstlisting
}[numbers=left,frame=single
]
2367 json
[options
] [selection
]
2369 Write a JSON netlist of all selected objects.
2372 write to the specified file.
2375 also include AIG models for the different gate types
2378 emit
32-bit or smaller fully-defined parameter values directly
2379 as JSON numbers (for compatibility with old parsers)
2381 See 'help write_json' for a description of the JSON format used.
2384 \section{log -- print text and log files
}
2386 \begin{lstlisting
}[numbers=left,frame=single
]
2389 Print the given string to the screen and/or the log file. This is useful for TCL
2390 scripts, because the TCL command "puts" only goes to stdout but not to
2394 Print the output to stdout too. This is useful when all Yosys is executed
2395 with a script and the -q (quiet operation) argument to notify the user.
2398 Print the output to stderr too.
2401 Don't use the internal log() command. Use either -stdout or -stderr,
2402 otherwise no output will be generated at all.
2405 do not append a newline
2408 \section{logger -- set logger properties
}
2410 \begin{lstlisting
}[numbers=left,frame=single
]
2413 This command sets global logger properties, also available using command line
2417 enable/disable display of timestamp in log output.
2420 enable/disable logging errors to stderr.
2423 print a warning for all log messages matching the regex.
2426 if a warning message matches the regex, it is printed as regular
2430 if a warning message matches the regex, it is printed as error
2431 message instead and the tool terminates with a nonzero return code.
2434 globally enable/disable debug log messages.
2436 -experimental <feature>
2437 do not print warnings for the specified experimental feature
2439 -expect <type> <regex> <expected_count>
2440 expect log,warning or error to appear. In case of error return code is
0.
2443 gives error in case there is at least one warning that is not expected.
2446 \section{ls -- list modules or objects in modules
}
2448 \begin{lstlisting
}[numbers=left,frame=single
]
2451 When no active module is selected, this prints a list of modules.
2453 When an active module is selected, this prints a list of objects in the module.
2456 \section{ltp -- print longest topological path
}
2458 \begin{lstlisting
}[numbers=left,frame=single
]
2459 ltp
[options
] [selection
]
2461 This command prints the longest topological path in the design. (Only considers
2462 paths within a single module, so the design must be flattened.)
2465 automatically exclude FF cell types
2468 \section{lut2mux -- convert \$lut to \$
\_MUX\_}
2470 \begin{lstlisting
}[numbers=left,frame=single
]
2471 lut2mux
[options
] [selection
]
2473 This pass converts $lut cells to $_MUX_ gates.
2476 \section{maccmap -- mapping macc cells
}
2478 \begin{lstlisting
}[numbers=left,frame=single
]
2479 maccmap
[-unmap
] [selection
]
2481 This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
2482 is used then the $macc cell is mapped to $add, $sub, etc. cells instead.
2485 \section{memory -- translate memories to basic cells
}
2487 \begin{lstlisting
}[numbers=left,frame=single
]
2488 memory
[-nomap
] [-nordff
] [-memx
] [-bram <bram_rules>
] [selection
]
2490 This pass calls all the other memory_* passes in a useful order:
2493 memory_dff
[-nordff
] (-memx implies -nordff)
2497 memory_memx (when called with -memx)
2499 memory_bram -rules <bram_rules> (when called with -bram)
2500 memory_map (skipped if called with -nomap)
2502 This converts memories to word-wide DFFs and address decoders
2503 or multiport memory blocks if called with the -nomap option.
2506 \section{memory
\_bram -- map memories to block rams
}
2507 \label{cmd:memory_bram
}
2508 \begin{lstlisting
}[numbers=left,frame=single
]
2509 memory_bram -rules <rule_file>
[selection
]
2511 This pass converts the multi-port $mem memory cells into block ram instances.
2512 The given rules file describes the available resources and how they should be
2515 The rules file contains configuration options, a set of block ram description
2516 and a sequence of match rules.
2518 The option 'attr_icase' configures how attribute values are matched. The value
0
2519 means case-sensitive,
1 means case-insensitive.
2521 A block ram description looks like this:
2523 bram RAMB1024X32 # name of BRAM cell
2524 init
1 # set to '
1' if BRAM can be initialized
2525 abits
10 # number of address bits
2526 dbits
32 # number of data bits
2527 groups
2 # number of port groups
2528 ports
1 1 # number of ports in each group
2529 wrmode
1 0 # set to '
1' if this groups is write ports
2530 enable
4 1 # number of enable bits
2531 transp
0 2 # transparent (for read ports)
2532 clocks
1 2 # clock configuration
2533 clkpol
2 2 # clock polarity configuration
2536 For the option 'transp' the value
0 means non-transparent,
1 means transparent
2537 and a value greater than
1 means configurable. All groups with the same
2538 value greater than
1 share the same configuration bit.
2540 For the option 'clocks' the value
0 means non-clocked, and a value greater
2541 than
0 means clocked. All groups with the same value share the same clock
2544 For the option 'clkpol' the value
0 means negative edge,
1 means positive edge
2545 and a value greater than
1 means configurable. All groups with the same value
2546 greater than
1 share the same configuration bit.
2548 Using the same bram name in different bram blocks will create different variants
2549 of the bram. Verilog configuration parameters for the bram are created as needed.
2551 It is also possible to create variants by repeating statements in the bram block
2552 and appending '@<label>' to the individual statements.
2554 A match rule looks like this:
2557 max waste
16384 # only use this bram if <=
16k ram bits are unused
2558 min efficiency
80 # only use this bram if efficiency is at least
80%
2561 It is possible to match against the following values with min/max rules:
2563 words ........ number of words in memory in design
2564 abits ........ number of address bits on memory in design
2565 dbits ........ number of data bits on memory in design
2566 wports ....... number of write ports on memory in design
2567 rports ....... number of read ports on memory in design
2568 ports ........ number of ports on memory in design
2569 bits ......... number of bits in memory in design
2570 dups .......... number of duplications for more read ports
2572 awaste ....... number of unused address slots for this match
2573 dwaste ....... number of unused data bits for this match
2574 bwaste ....... number of unused bram bits for this match
2575 waste ........ total number of unused bram bits (bwaste*dups)
2576 efficiency ... total percentage of used and non-duplicated bits
2578 acells ....... number of cells in 'address-direction'
2579 dcells ....... number of cells in 'data-direction'
2580 cells ........ total number of cells (acells*dcells*dups)
2582 A match containing the command 'attribute' followed by a list of space
2583 separated 'name
[=string_value
]' values requires that the memory contains any
2584 one of the given attribute name and string values (where specified), or name
2585 and integer
1 value (if no string_value given, since Verilog will interpret
2586 '
(* attr *)' as '
(* attr=1 *)').
2587 A name prefixed with '!' indicates that the attribute must not exist.
2589 The interface for the created bram instances is derived from the bram
2590 description. Use 'techmap' to convert the created bram instances into
2591 instances of the actual bram cells of your target architecture.
2593 A match containing the command 'or_next_if_better' is only used if it
2594 has a higher efficiency than the next match (and the one after that if
2595 the next also has 'or_next_if_better' set, and so forth).
2597 A match containing the command 'make_transp' will add external circuitry
2598 to simulate 'transparent read', if necessary.
2600 A match containing the command 'make_outreg' will add external flip-flops
2601 to implement synchronous read ports, if necessary.
2603 A match containing the command 'shuffle_enable A' will re-organize
2604 the data bits to accommodate the enable pattern of port A.
2607 \section{memory
\_collect -- creating multi-port memory cells
}
2608 \label{cmd:memory_collect
}
2609 \begin{lstlisting
}[numbers=left,frame=single
]
2610 memory_collect
[selection
]
2612 This pass collects memories and memory ports and creates generic multiport
2616 \section{memory
\_dff -- merge input/output DFFs into memories
}
2617 \label{cmd:memory_dff
}
2618 \begin{lstlisting
}[numbers=left,frame=single
]
2619 memory_dff
[options
] [selection
]
2621 This pass detects DFFs at memory ports and merges them into the memory port.
2622 I.e. it consumes an asynchronous memory port and the flip-flops at its
2623 interface and yields a synchronous memory port.
2626 do not merge registers on read ports
2629 \section{memory
\_map -- translate multiport memories to basic cells
}
2630 \label{cmd:memory_map
}
2631 \begin{lstlisting
}[numbers=left,frame=single
]
2632 memory_map
[options
] [selection
]
2634 This pass converts multiport memory cells as generated by the memory_collect
2635 pass to word-wide DFFs and address decoders.
2638 do not map memories that have attribute <name> set.
2640 -attr <name>
[=<value>
]
2641 for memories that have attribute <name> set, only map them if its value
2642 is a string <value> (if specified), or an integer
1 (otherwise). if this
2643 option is specified multiple times, map the memory if the attribute is
2644 to any of the values.
2647 for -attr, ignore case of <value>.
2650 \section{memory
\_memx -- emulate vlog sim behavior for mem ports
}
2651 \label{cmd:memory_memx
}
2652 \begin{lstlisting
}[numbers=left,frame=single
]
2653 memory_memx
[selection
]
2655 This pass adds additional circuitry that emulates the Verilog simulation
2656 behavior for out-of-bounds memory reads and writes.
2659 \section{memory
\_nordff -- extract read port FFs from memories
}
2660 \label{cmd:memory_nordff
}
2661 \begin{lstlisting
}[numbers=left,frame=single
]
2662 memory_nordff
[options
] [selection
]
2664 This pass extracts FFs from memory read ports. This results in a netlist
2665 similar to what one would get from calling memory_dff with -nordff.
2668 \section{memory
\_share -- consolidate memory ports
}
2669 \label{cmd:memory_share
}
2670 \begin{lstlisting
}[numbers=left,frame=single
]
2671 memory_share
[selection
]
2673 This pass merges share-able memory ports into single memory ports.
2675 The following methods are used to consolidate the number of memory ports:
2677 - When write ports are connected to async read ports accessing the same
2678 address, then this feedback path is converted to a write port with
2679 byte/part enable signals.
2681 - When multiple write ports access the same address then this is converted
2682 to a single write port with a more complex data and/or enable logic path.
2684 - When multiple write ports are never accessed at the same time (a SAT
2685 solver is used to determine this), then the ports are merged into a single
2688 Note that in addition to the algorithms implemented in this pass, the $memrd
2689 and $memwr cells are also subject to generic resource sharing passes (and other
2690 optimizations) such as "share" and "opt_merge".
2693 \section{memory
\_unpack -- unpack multi-port memory cells
}
2694 \label{cmd:memory_unpack
}
2695 \begin{lstlisting
}[numbers=left,frame=single
]
2696 memory_unpack
[selection
]
2698 This pass converts the multi-port $mem memory cells into individual $memrd and
2699 $memwr cells. It is the counterpart to the memory_collect pass.
2702 \section{miter -- automatically create a miter circuit
}
2704 \begin{lstlisting
}[numbers=left,frame=single
]
2705 miter -equiv
[options
] gold_name gate_name miter_name
2707 Creates a miter circuit for equivalence checking. The gold- and gate- modules
2708 must have the same interfaces. The miter circuit will have all inputs of the
2709 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
2710 output that goes high if an output mismatch between the two source modules is
2714 a undef (x) bit in the gold module output will match any value in
2715 the gate module output.
2718 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
2719 on the miter circuit.
2722 also create a cmp_* output for each gold/gate output pair.
2725 also create an 'assert' cell that checks if trigger is always low.
2728 call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.
2731 miter -assert
[options
] module
[miter_name
]
2733 Creates a miter circuit for property checking. All input ports are kept,
2734 output ports are discarded. An additional output 'trigger' is created that
2735 goes high when an assert is violated. Without a miter_name, the existing
2739 keep module output ports.
2742 call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.
2745 \section{mutate -- generate or apply design mutations
}
2747 \begin{lstlisting
}[numbers=left,frame=single
]
2748 mutate -list N
[options
] [selection
]
2750 Create a list of N mutations using an even sampling.
2753 Write list to this file instead of console output
2756 Write a list of all src tags found in the design to the specified file
2759 RNG seed for selecting mutations
2762 Include a "none" mutation in the output
2764 -ctrl name width value
2765 Add -ctrl options to the output. Use 'value' for first mutation, then
2766 simply count up from there.
2777 Filter list of mutation candidates to those matching
2778 the given parameters.
2781 Set a configuration option. Options available:
2782 weight_pq_w weight_pq_b weight_pq_c weight_pq_s
2783 weight_pq_mw weight_pq_mb weight_pq_mc weight_pq_ms
2784 weight_cover pick_cover_prcnt
2787 mutate -mode MODE
[options
]
2789 Apply the given mutation.
2791 -ctrl name width value
2792 Add a control signal with the given name and width. The mutation is
2793 activated if the control signal equals the given value.
2800 Mutation parameters, as generated by 'mutate -list N'.
2805 Ignored. (They are generated by -list for documentation purposes.)
2808 \section{muxcover -- cover trees of MUX cells with wider MUXes
}
2809 \label{cmd:muxcover
}
2810 \begin{lstlisting
}[numbers=left,frame=single
]
2811 muxcover
[options
] [selection
]
2813 Cover trees of $_MUX_ cells with $_MUX
{4,
8,
16}_ cells
2815 -mux4
[=cost
], -mux8
[=cost
], -mux16
[=cost
]
2816 Cover $_MUX_ trees using the specified types of MUXes (with optional
2817 integer costs). If none of these options are given, the effect is the
2818 same as if all of them are.
2819 Default costs: $_MUX4_ =
220, $_MUX8_ =
460,
2823 Use the specified cost for $_MUX_ cells when making covering decisions.
2824 Default cost: $_MUX_ =
100
2827 Use the specified cost for $_MUX_ cells used in decoders.
2831 Do not insert decoder logic. This reduces the number of possible
2832 substitutions, but guarantees that the resulting circuit is not
2833 less efficient than the original circuit.
2836 Do not consider mappings that use $_MUX<N>_ to select from less
2837 than <N> different signals.
2840 \section{muxpack -- \$mux/\$pmux cascades to \$pmux
}
2842 \begin{lstlisting
}[numbers=left,frame=single
]
2845 This pass converts cascaded chains of $pmux cells (e.g. those create from case
2846 constructs) and $mux cells (e.g. those created by if-else constructs) into
2849 This optimisation is conservative --- it will only pack $mux or $pmux cells
2850 whose select lines are driven by '$eq' cells with other such cells if it can be
2851 certain that their select inputs are mutually exclusive.
2854 \section{nlutmap -- map to LUTs of different sizes
}
2856 \begin{lstlisting
}[numbers=left,frame=single
]
2857 nlutmap
[options
] [selection
]
2859 This pass uses successive calls to 'abc' to map to an architecture. That
2860 provides a small number of differently sized LUTs.
2862 -luts N_1,N_2,N_3,...
2863 The number of LUTs with
1,
2,
3, ... inputs that are
2864 available in the target architecture.
2867 Create an error if not all logic can be mapped
2869 Excess logic that does not fit into the specified LUTs is mapped back
2870 to generic logic gates ($_AND_, etc.).
2873 \section{onehot -- optimize \$eq cells for onehot signals
}
2875 \begin{lstlisting
}[numbers=left,frame=single
]
2876 onehot
[options
] [selection
]
2878 This pass optimizes $eq cells that compare one-hot signals against constants
2884 \section{opt -- perform simple optimizations
}
2886 \begin{lstlisting
}[numbers=left,frame=single
]
2887 opt
[options
] [selection
]
2889 This pass calls all the other opt_* passes in a useful order. This performs
2890 a series of trivial optimizations and cleanups. This pass executes the other
2891 passes in the following order:
2893 opt_expr
[-mux_undef
] [-mux_bool
] [-undriven
] [-clkinv
] [-fine
] [-full
] [-keepdc
]
2894 opt_merge
[-share_all
] -nomux
2898 opt_reduce
[-fine
] [-full
]
2899 opt_merge
[-share_all
]
2900 opt_share (-full only)
2901 opt_rmdff
[-keepdc
] [-sat
]
2903 opt_expr
[-mux_undef
] [-mux_bool
] [-undriven
] [-clkinv
] [-fine
] [-full
] [-keepdc
]
2904 while <changed design>
2906 When called with -fast the following script is used instead:
2909 opt_expr
[-mux_undef
] [-mux_bool
] [-undriven
] [-clkinv
] [-fine
] [-full
] [-keepdc
]
2910 opt_merge
[-share_all
]
2911 opt_rmdff
[-keepdc
] [-sat
]
2913 while <changed design in opt_rmdff>
2915 Note: Options in square brackets (such as
[-keepdc
]) are passed through to
2916 the opt_* commands when given to 'opt'.
2919 \section{opt
\_clean -- remove unused cells and wires
}
2920 \label{cmd:opt_clean
}
2921 \begin{lstlisting
}[numbers=left,frame=single
]
2922 opt_clean
[options
] [selection
]
2924 This pass identifies wires and cells that are unused and removes them. Other
2925 passes often remove cells but leave the wires in the design or reconnect the
2926 wires but leave the old cells in the design. This pass can be used to clean up
2927 after the passes that do the actual work.
2929 This pass only operates on completely selected modules without processes.
2932 also remove internal nets if they have a public name
2935 \section{opt
\_demorgan -- Optimize reductions with DeMorgan equivalents
}
2936 \label{cmd:opt_demorgan
}
2937 \begin{lstlisting
}[numbers=left,frame=single
]
2938 opt_demorgan
[selection
]
2940 This pass pushes inverters through $reduce_* cells if this will reduce the
2941 overall gate count of the circuit
2944 \section{opt
\_expr -- perform const folding and simple expression rewriting
}
2945 \label{cmd:opt_expr
}
2946 \begin{lstlisting
}[numbers=left,frame=single
]
2947 opt_expr
[options
] [selection
]
2949 This pass performs const folding on internal cell types with constant inputs.
2950 It also performs some simple expression rewriting.
2953 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
2956 replace $mux cells with inverters or buffers when possible
2959 replace undriven nets with undef (x) constants
2962 optimize clock inverters by changing FF types
2965 perform fine-grain optimizations
2968 alias for -mux_undef -mux_bool -undriven -fine
2971 some optimizations change the behavior of the circuit with respect to
2972 don't-care bits. for example in 'a+
0' a single x-bit in 'a' will cause
2973 all result bits to be set to x. this behavior changes when 'a+
0' is
2974 replaced by 'a'. the -keepdc option disables all such optimizations.
2977 \section{opt
\_lut -- optimize LUT cells
}
2979 \begin{lstlisting
}[numbers=left,frame=single
]
2980 opt_lut
[options
] [selection
]
2982 This pass combines cascaded $lut cells with unused inputs.
2984 -dlogic <type>:<cell-port>=<LUT-input>
[:<cell-port>=<LUT-input>...
]
2985 preserve connections to dedicated logic cell <type> that has ports
2986 <cell-port> connected to LUT inputs <LUT-input>. this includes
2987 the case where both LUT and dedicated logic input are connected to
2991 only perform the first N combines, then stop. useful for debugging.
2994 \section{opt
\_lut\_ins -- discard unused LUT inputs
}
2995 \label{cmd:opt_lut_ins
}
2996 \begin{lstlisting
}[numbers=left,frame=single
]
2997 opt_lut_ins
[options
] [selection
]
2999 This pass removes unused inputs from LUT cells (that is, inputs that can not
3000 influence the output signal given this LUT's value). While such LUTs cannot
3001 be directly emitted by ABC, they can be a result of various post-ABC
3002 transformations, such as mapping wide LUTs (not all sub-LUTs will use the
3003 full set of inputs) or optimizations such as xilinx_dffopt.
3006 Instead of generic $lut cells, operate on LUT cells specific
3007 to the given technology. Valid values are: xilinx, ecp5, gowin.
3010 \section{opt
\_mem -- optimize memories
}
3012 \begin{lstlisting
}[numbers=left,frame=single
]
3013 opt_mem
[options
] [selection
]
3015 This pass performs various optimizations on memories in the design.
3018 \section{opt
\_merge -- consolidate identical cells
}
3019 \label{cmd:opt_merge
}
3020 \begin{lstlisting
}[numbers=left,frame=single
]
3021 opt_merge
[options
] [selection
]
3023 This pass identifies cells with identical type and input signals. Such cells
3024 are then merged to one cell.
3027 Do not merge MUX cells.
3030 Operate on all cell types, not just built-in types.
3033 \section{opt
\_muxtree -- eliminate dead trees in multiplexer trees
}
3034 \label{cmd:opt_muxtree
}
3035 \begin{lstlisting
}[numbers=left,frame=single
]
3036 opt_muxtree
[selection
]
3038 This pass analyzes the control signals for the multiplexer trees in the design
3039 and identifies inputs that can never be active. It then removes this dead
3040 branches from the multiplexer trees.
3042 This pass only operates on completely selected modules without processes.
3045 \section{opt
\_reduce -- simplify large MUXes and AND/OR gates
}
3046 \label{cmd:opt_reduce
}
3047 \begin{lstlisting
}[numbers=left,frame=single
]
3048 opt_reduce
[options
] [selection
]
3050 This pass performs two interlinked optimizations:
3052 1. it consolidates trees of large AND gates or OR gates and eliminates
3055 2. it identifies duplicated inputs to MUXes and replaces them with a single
3056 input with the original control signals OR'ed together.
3059 perform fine-grain optimizations
3065 \section{opt
\_rmdff -- remove DFFs with constant inputs
}
3066 \label{cmd:opt_rmdff
}
3067 \begin{lstlisting
}[numbers=left,frame=single
]
3068 opt_rmdff
[-keepdc
] [-sat
] [selection
]
3070 This pass identifies flip-flops with constant inputs and replaces them with
3074 additionally invoke SAT solver to detect and remove flip-flops (with
3075 non-constant inputs) that can also be replaced with a constant driver
3078 \section{opt
\_share -- merge mutually exclusive cells of the same type that share an input signal
}
3079 \label{cmd:opt_share
}
3080 \begin{lstlisting
}[numbers=left,frame=single
]
3081 opt_share
[selection
]
3083 This pass identifies mutually exclusive cells of the same type that:
3084 (a) share an input signal,
3085 (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell,
3087 allowing the cell to be merged and the multiplexer to be moved from
3088 multiplexing its output to multiplexing the non-shared input signals.
3091 \section{paramap -- renaming cell parameters
}
3093 \begin{lstlisting
}[numbers=left,frame=single
]
3094 paramap
[options
] [selection
]
3096 This command renames cell parameters and/or maps key/value pairs to
3097 other key/value pairs.
3100 Match attribute names case-insensitively and set it to the specified
3103 -rename <old_name> <new_name>
3104 Rename attributes as specified
3106 -map <old_name>=<old_value> <new_name>=<new_value>
3107 Map key/value pairs as indicated.
3109 -imap <old_name>=<old_value> <new_name>=<new_value>
3110 Like -map, but use case-insensitive match for <old_value> when
3111 it is a string value.
3113 -remove <name>=<value>
3114 Remove attributes matching this pattern.
3116 For example, mapping Diamond-style ECP5 "init" attributes to Yosys-style:
3118 paramap -tocase INIT t:LUT4
3121 \section{peepopt -- collection of peephole optimizers
}
3123 \begin{lstlisting
}[numbers=left,frame=single
]
3124 peepopt
[options
] [selection
]
3126 This pass applies a collection of peephole optimizers to the current design.
3129 \section{plugin -- load and list loaded plugins
}
3131 \begin{lstlisting
}[numbers=left,frame=single
]
3134 Load and list loaded plugins.
3136 -i <plugin_filename>
3137 Load (install) the specified plugin.
3140 Register the specified alias name for the loaded plugin
3146 \section{pmux2shiftx -- transform \$pmux cells to \$shiftx cells
}
3147 \label{cmd:pmux2shiftx
}
3148 \begin{lstlisting
}[numbers=left,frame=single
]
3149 pmux2shiftx
[options
] [selection
]
3151 This pass transforms $pmux cells to $shiftx cells.
3156 -min_density <percentage>
3157 specifies the minimum density for the shifter
3161 specified the minimum number of choices for a control signal
3164 -onehot ignore|pmux|shiftx
3165 select strategy for one-hot encoded control signals
3169 disable $sub inference for "range decoders"
3172 \section{pmuxtree -- transform \$pmux cells to trees of \$mux cells
}
3173 \label{cmd:pmuxtree
}
3174 \begin{lstlisting
}[numbers=left,frame=single
]
3175 pmuxtree
[selection
]
3177 This pass transforms $pmux cells to trees of $mux cells.
3180 \section{portlist -- list (top-level) ports
}
3181 \label{cmd:portlist
}
3182 \begin{lstlisting
}[numbers=left,frame=single
]
3183 portlist
[options
] [selection
]
3185 This command lists all module ports found in the selected modules.
3187 If no selection is provided then it lists the ports on the top module.
3190 print verilog blackbox module definitions instead of port lists
3193 \section{prep -- generic synthesis script
}
3195 \begin{lstlisting
}[numbers=left,frame=single
]
3198 This command runs a conservative RTL synthesis. A typical application for this
3199 is the preparation stage of a verification flow. This command does not operate
3200 on partly selected designs.
3203 use the specified module as top module (default='top')
3206 automatically determine the top of the design hierarchy
3209 flatten the design before synthesis. this will pass '-auto-top' to
3210 'hierarchy' if no top module is specified.
3213 passed to 'proc'. uses verilog simulation behavior for verilog if/case
3214 undef handling. this also prevents 'wreduce' from being run.
3217 simulate verilog simulation behavior for out-of-bounds memory accesses
3218 using the 'memory_memx' pass.
3221 do not run any of the memory_* passes
3224 do not pass -nordff to 'memory_dff'. This enables merging of FFs into
3228 do not call opt_* with -keepdc
3230 -run <from_label>
[:<to_label>
]
3231 only run the commands between the labels (see below). an empty
3232 from label is synonymous to 'begin', and empty to label is
3233 synonymous to the end of the command list.
3236 The following commands are executed by this synthesis command:
3239 hierarchy -check
[-top <top> | -auto-top
]
3243 flatten (if -flatten)
3248 wreduce -keepdc
[-memx
]
3249 memory_dff
[-nordff
]
3250 memory_memx (if -memx)
3260 \section{proc -- translate processes to netlists
}
3262 \begin{lstlisting
}[numbers=left,frame=single
]
3263 proc
[options
] [selection
]
3265 This pass calls all the other proc_* passes in the most common order.
3277 This replaces the processes in the design with multiplexers,
3278 flip-flops and latches.
3280 The following options are supported:
3282 -global_arst
[!
]<netname>
3283 This option is passed through to proc_arst.
3286 This option is passed through to proc_mux. proc_rmdead is not
3287 executed in -ifx mode.
3290 \section{proc
\_arst -- detect asynchronous resets
}
3291 \label{cmd:proc_arst
}
3292 \begin{lstlisting
}[numbers=left,frame=single
]
3293 proc_arst
[-global_arst
[!
]<netname>
] [selection
]
3295 This pass identifies asynchronous resets in the processes and converts them
3296 to a different internal representation that is suitable for generating
3297 flip-flop cells with asynchronous resets.
3299 -global_arst
[!
]<netname>
3300 In modules that have a net with the given name, use this net as async
3301 reset for registers that have been assign initial values in their
3302 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
3303 active low reset signals. Note: the frontend stores the default value
3304 in the 'init' attribute on the net.
3307 \section{proc
\_clean -- remove empty parts of processes
}
3308 \label{cmd:proc_clean
}
3309 \begin{lstlisting
}[numbers=left,frame=single
]
3310 proc_clean
[options
] [selection
]
3313 do not print any messages.
3315 This pass removes empty parts of processes and ultimately removes a process
3316 if it contains only empty structures.
3319 \section{proc
\_dff -- extract flip-flops from processes
}
3320 \label{cmd:proc_dff
}
3321 \begin{lstlisting
}[numbers=left,frame=single
]
3322 proc_dff
[selection
]
3324 This pass identifies flip-flops in the processes and converts them to
3325 d-type flip-flop cells.
3328 \section{proc
\_dlatch -- extract latches from processes
}
3329 \label{cmd:proc_dlatch
}
3330 \begin{lstlisting
}[numbers=left,frame=single
]
3331 proc_dlatch
[selection
]
3333 This pass identifies latches in the processes and converts them to
3337 \section{proc
\_init -- convert initial block to init attributes
}
3338 \label{cmd:proc_init
}
3339 \begin{lstlisting
}[numbers=left,frame=single
]
3340 proc_init
[selection
]
3342 This pass extracts the 'init' actions from processes (generated from Verilog
3343 'initial' blocks) and sets the initial value to the 'init' attribute on the
3347 \section{proc
\_mux -- convert decision trees to multiplexers
}
3348 \label{cmd:proc_mux
}
3349 \begin{lstlisting
}[numbers=left,frame=single
]
3350 proc_mux
[options
] [selection
]
3352 This pass converts the decision trees in processes (originating from if-else
3353 and case statements) to trees of multiplexer cells.
3356 Use Verilog simulation behavior with respect to undef values in
3357 'case' expressions and 'if' conditions.
3360 \section{proc
\_prune -- remove redundant assignments
}
3361 \label{cmd:proc_prune
}
3362 \begin{lstlisting
}[numbers=left,frame=single
]
3363 proc_prune
[selection
]
3365 This pass identifies assignments in processes that are always overwritten by
3366 a later assignment to the same signal and removes them.
3369 \section{proc
\_rmdead -- eliminate dead trees in decision trees
}
3370 \label{cmd:proc_rmdead
}
3371 \begin{lstlisting
}[numbers=left,frame=single
]
3372 proc_rmdead
[selection
]
3374 This pass identifies unreachable branches in decision trees and removes them.
3377 \section{qwp -- quadratic wirelength placer
}
3379 \begin{lstlisting
}[numbers=left,frame=single
]
3380 qwp
[options
] [selection
]
3382 This command runs quadratic wirelength placement on the selected modules and
3383 annotates the cells in the design with 'qwp_position' attributes.
3386 Add left-to-right constraints: constrain all inputs on the left border
3387 outputs to the right border.
3390 Add constraints for inputs/outputs to be placed in alphanumerical
3391 order along the y-axis (top-to-bottom).
3394 Number of grid divisions in x- and y-direction. (default=
16)
3396 -dump <html_file_name>
3397 Dump a protocol of the placement algorithm to the html file.
3400 Verbose solver output for profiling or debugging
3402 Note: This implementation of a quadratic wirelength placer uses exact
3403 dense matrix operations. It is only a toy-placer for small circuits.
3406 \section{read -- load HDL designs
}
3408 \begin{lstlisting
}[numbers=left,frame=single
]
3409 read
{-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal
} <verilog-file>..
3411 Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support
3412 is only available via Verific.)
3414 Additional -D<macro>
[=<value>
] options may be added after the option indicating
3415 the language version (and before file names) to set additional verilog defines.
3418 read
{-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl
} <vhdl-file>..
3420 Load the specified VHDL files. (Requires Verific.)
3423 read -define <macro>
[=<value>
]..
3425 Set global Verilog/SystemVerilog defines.
3428 read -undef <macro>..
3430 Unset global Verilog/SystemVerilog defines.
3433 read -incdir <directory>
3435 Add directory to global Verilog/SystemVerilog include directories.
3441 Subsequent calls to 'read' will either use or not use Verific. Calling 'read'
3442 with -verific will result in an error on Yosys binaries that are built without
3443 Verific support. The default is to use Verific if it is available.
3446 \section{read
\_aiger -- read AIGER file
}
3447 \label{cmd:read_aiger
}
3448 \begin{lstlisting
}[numbers=left,frame=single
]
3449 read_aiger
[options
] [filename
]
3451 Load module from an AIGER file into the current design.
3453 -module_name <module_name>
3454 name of module to be created (default: <filename>)
3456 -clk_name <wire_name>
3457 if specified, AIGER latches to be transformed into $_DFF_P_ cells
3458 clocked by wire of this name. otherwise, $_FF_ cells will be used
3461 read file with port and latch symbols
3464 merge ports that match the pattern 'name
[int
]' into a single
3465 multi-bit port 'name'
3468 read XAIGER extensions
3471 \section{read
\_blif -- read BLIF file
}
3472 \label{cmd:read_blif
}
3473 \begin{lstlisting
}[numbers=left,frame=single
]
3474 read_blif
[options
] [filename
]
3476 Load modules from a BLIF file into the current design.
3479 Create $sop cells instead of $lut cells
3482 Merge ports that match the pattern 'name
[int
]' into a single
3483 multi-bit port 'name'.
3486 \section{read
\_ilang -- read modules from ilang file
}
3487 \label{cmd:read_ilang
}
3488 \begin{lstlisting
}[numbers=left,frame=single
]
3489 read_ilang
[filename
]
3491 Load modules from an ilang file to the current design. (ilang is a text
3492 representation of a design in yosys's internal format.)
3495 ignore re-definitions of modules. (the default behavior is to
3496 create an error message if the existing module is not a blackbox
3497 module, and overwrite the existing module if it is a blackbox module.)
3500 overwrite existing modules with the same name
3503 only create empty blackbox modules
3506 \section{read
\_json -- read JSON file
}
3507 \label{cmd:read_json
}
3508 \begin{lstlisting
}[numbers=left,frame=single
]
3509 read_json
[filename
]
3511 Load modules from a JSON file into the current design See "help write_json"
3512 for a description of the file format.
3515 \section{read
\_liberty -- read cells from liberty file
}
3516 \label{cmd:read_liberty
}
3517 \begin{lstlisting
}[numbers=left,frame=single
]
3518 read_liberty
[filename
]
3520 Read cells from liberty file as modules into current design.
3523 only create empty blackbox modules
3526 ignore re-definitions of modules. (the default behavior is to
3527 create an error message if the existing module is not a blackbox
3528 module, and overwrite the existing module if it is a blackbox module.)
3531 overwrite existing modules with the same name
3534 ignore cells with missing function specification of outputs
3537 ignore cells with a missing or invalid direction
3538 specification on a pin
3540 -ignore_miss_data_latch
3541 ignore latches with missing data and/or enable pins
3543 -setattr <attribute_name>
3544 set the specified attribute (to the value
1) on all loaded modules
3547 \section{read
\_verilog -- read modules from Verilog file
}
3548 \label{cmd:read_verilog
}
3549 \begin{lstlisting
}[numbers=left,frame=single
]
3550 read_verilog
[options
] [filename
]
3552 Load modules from a Verilog file to the current design. A large subset of
3553 Verilog-
2005 is supported.
3556 enable support for SystemVerilog features. (only a small subset
3557 of SystemVerilog is supported)
3560 enable support for SystemVerilog assertions and some Yosys extensions
3561 replace the implicit -D SYNTHESIS with -D FORMAL
3564 ignore assert() statements
3567 ignore assume() statements
3570 ignore restrict() statements
3573 treat all assert() statements like assume() statements
3576 treat all assume() statements like assert() statements
3579 alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug
3582 dump abstract syntax tree (before simplification)
3585 dump abstract syntax tree (after simplification)
3588 do not include hex memory addresses in dump (easier to diff dumps)
3591 dump ast as Verilog code (before simplification)
3594 dump ast as Verilog code (after simplification)
3597 dump generated RTLIL netlist
3600 enable parser debug output
3603 usually latches are synthesized into logic loops
3604 this option prohibits this and sets the output to 'x'
3605 in what would be the latches hold condition
3607 this behavior can also be achieved by setting the
3608 'nolatches' attribute on the respective module or
3612 under certain conditions memories are converted to registers
3613 early during simplification to ensure correct handling of
3614 complex corner cases. this option disables this behavior.
3616 this can also be achieved by setting the 'nomem2reg'
3617 attribute on the respective module or register.
3619 This is potentially dangerous. Usually the front-end has good
3620 reasons for converting an array to a list of registers.
3621 Prohibiting this step will likely result in incorrect synthesis
3625 always convert memories to registers. this can also be
3626 achieved by setting the 'mem2reg' attribute on the respective
3630 do not infer $meminit cells and instead convert initialized
3631 memories to registers directly in the front-end.
3634 dump Verilog code after pre-processor
3637 do not run the pre-processor
3640 disable DPI-C support
3643 do not automatically add a
(* blackbox *) attribute to an
3647 only create empty blackbox modules. This implies -DBLACKBOX.
3648 modules with the
(* whitebox *) attribute will be preserved.
3649 (* lib_whitebox *) will be treated like
(* whitebox *).
3652 delete
(* whitebox *) and
(* lib_whitebox *) attributes from
3656 parse and import specify blocks
3659 don't perform basic optimizations (such as const folding) in the
3660 high-level front-end.
3663 interpret cell types starting with '$' as internal cell types
3666 add a wire for each module parameter
3669 ignore re-definitions of modules. (the default behavior is to
3670 create an error message if the existing module is not a black box
3671 module, and overwrite the existing module otherwise.)
3674 overwrite existing modules with the same name
3677 only read the abstract syntax tree and defer actual compilation
3678 to a later 'hierarchy' command. Useful in cases where the default
3679 parameters of modules yield invalid or not synthesizable code.
3682 make the default of `default_nettype be "none" instead of "wire".
3684 -setattr <attribute_name>
3685 set the specified attribute (to the value
1) on all loaded modules
3688 define the preprocessor symbol 'name' and set its optional value
3692 add 'dir' to the directories which are used when searching include
3695 The command 'verilog_defaults' can be used to register default options for
3696 subsequent calls to 'read_verilog'.
3698 Note that the Verilog frontend does a pretty good job of processing valid
3699 verilog input, but has not very good error reporting. It generally is
3700 recommended to use a simulator (for example Icarus Verilog) for checking
3701 the syntax of the code, rather than to rely on read_verilog for that.
3703 Depending on if read_verilog is run in -formal mode, either the macro
3704 SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog
3705 always defines the macro YOSYS.
3707 See the Yosys README file for a list of non-standard Verilog features
3708 supported by the Yosys Verilog front-end.
3711 \section{rename -- rename object in the design
}
3713 \begin{lstlisting
}[numbers=left,frame=single
]
3714 rename old_name new_name
3716 Rename the specified object. Note that selection patterns are not supported
3721 rename -output old_name new_name
3723 Like above, but also make the wire an output. This will fail if the object is
3727 rename -src
[selection
]
3729 Assign names auto-generated from the src attribute to all selected wires and
3730 cells with private names.
3733 rename -wire
[selection
]
3735 Assign auto-generated names based on the wires they drive to all selected
3736 cells with private names. Ignores cells driving privatly named wires.
3739 rename -enumerate
[-pattern <pattern>
] [selection
]
3741 Assign short auto-generated names to all selected wires and cells with private
3742 names. The -pattern option can be used to set the pattern for the new names.
3743 The character
% in the pattern is replaced with a integer number. The default
3747 rename -hide
[selection
]
3749 Assign private names (the ones with $-prefix) to all selected wires and cells
3750 with public names. This ignores all selected ports.
3753 rename -top new_name
3758 \section{rmports -- remove module ports with no connections
}
3760 \begin{lstlisting
}[numbers=left,frame=single
]
3763 This pass identifies ports in the selected modules which are not used or
3764 driven and removes them.
3767 \section{sat -- solve a SAT problem in the circuit
}
3769 \begin{lstlisting
}[numbers=left,frame=single
]
3770 sat
[options
] [selection
]
3772 This command solves a SAT problem defined over the currently selected circuit
3773 and additional constraints passed as parameters.
3776 show all solutions to the problem (this can grow exponentially, use
3777 -max <N> instead to get <N> solutions)
3780 like -all, but limit number of solutions to <N>
3783 enable modeling of undef value (aka 'x-bits')
3784 this option is implied by -set-def, -set-undef et. cetera
3787 maximize the number of undef bits in solutions, giving a better
3788 picture of which input bits are actually vital to the solution.
3790 -set <signal> <value>
3791 set the specified signal to the specified value.
3794 add a constraint that all bits of the given signal must be defined
3796 -set-any-undef <signal>
3797 add a constraint that at least one bit of the given signal is undefined
3799 -set-all-undef <signal>
3800 add a constraint that all bits of the given signal are undefined
3803 add -set-def constraints for all module inputs
3806 show the model for the specified signal. if no -show option is
3807 passed then a set of signals to be shown is automatically selected.
3809 -show-inputs, -show-outputs, -show-ports
3810 add all module (input/output) ports to the list of shown signals
3812 -show-regs, -show-public, -show-all
3813 show all registers, show signals with 'public' names, show all signals
3816 ignore all solutions that involve a division by zero
3818 -ignore_unknown_cells
3819 ignore all cells that can not be matched to a SAT model
3821 The following options can be used to set up a sequential problem:
3824 set up a sequential problem with <N> time steps. The steps will
3825 be numbered from
1 to N.
3827 note: for large <N> it can be significantly faster to use
3828 -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.
3830 -set-at <N> <signal> <value>
3831 -unset-at <N> <signal>
3832 set or unset the specified signal to the specified value in the
3833 given timestep. this has priority over a -set for the same signal.
3836 set all assumptions provided via $assume cells
3838 -set-def-at <N> <signal>
3839 -set-any-undef-at <N> <signal>
3840 -set-all-undef-at <N> <signal>
3841 add undef constraints in the given timestep.
3843 -set-init <signal> <value>
3844 set the initial value for the register driving the signal to the value
3847 set all initial states (not set using -set-init) to undef
3850 do not force a value for the initial state but do not allow undef
3853 set all initial states (not set using -set-init) to zero
3855 -dump_vcd <vcd-file-name>
3856 dump SAT model (counter example in proof) to VCD file
3858 -dump_json <json-file-name>
3859 dump SAT model (counter example in proof) to a WaveJSON file.
3861 -dump_cnf <cnf-file-name>
3862 dump CNF of SAT problem (in DIMACS format). in temporal induction
3863 proofs this is the CNF of the first induction step.
3865 The following additional options can be used to set up a proof. If also -seq
3866 is passed, a temporal induction proof is performed.
3869 Perform a temporal induction proof. In a temporal induction proof it is
3870 proven that the condition holds forever after the number of time steps
3871 specified using -seq.
3874 Perform a temporal induction proof. Assume an initial state with all
3875 registers set to defined values for the induction step.
3877 -tempinduct-baseonly
3878 Run only the basecase half of temporal induction (requires -maxsteps)
3880 -tempinduct-inductonly
3881 Run only the induction half of temporal induction
3883 -tempinduct-skip <N>
3884 Skip the first <N> steps of the induction proof.
3886 note: this will assume that the base case holds for <N> steps.
3887 this must be proven independently with "-tempinduct-baseonly
3888 -maxsteps <N>". Use -initsteps if you just want to set a
3889 minimal induction length.
3891 -prove <signal> <value>
3892 Attempt to proof that <signal> is always <value>.
3894 -prove-x <signal> <value>
3895 Like -prove, but an undef (x) bit in the lhs matches any value on
3896 the right hand side. Useful for equivalence checking.
3899 Prove that all asserts in the design hold.
3902 Do not enforce the prove-condition for the first <N> time steps.
3905 Set a maximum length for the induction.
3908 Set initial length for the induction.
3909 This will speed up the search of the right induction length
3910 for deep induction proofs.
3913 Increase the size of the induction proof in steps of <N>.
3914 This will speed up the search of the right induction length
3915 for deep induction proofs.
3918 Maximum number of seconds a single SAT instance may take.
3921 Return an error and stop the synthesis script if the proof fails.
3924 Like -verify but do not return an error for timeouts.
3927 Return an error and stop the synthesis script if the proof succeeds.
3930 Like -falsify but do not return an error for timeouts.
3933 \section{scatter -- add additional intermediate nets
}
3935 \begin{lstlisting
}[numbers=left,frame=single
]
3938 This command adds additional intermediate nets on all cell ports. This is used
3939 for testing the correct use of the SigMap helper in passes. If you don't know
3940 what this means: don't worry -- you only need this pass when testing your own
3941 extensions to Yosys.
3943 Use the opt_clean command to get rid of the additional nets.
3946 \section{scc -- detect strongly connected components (logic loops)
}
3948 \begin{lstlisting
}[numbers=left,frame=single
]
3949 scc
[options
] [selection
]
3951 This command identifies strongly connected components (aka logic loops) in the
3955 expect to find exactly <num> SSCs. A different number of SSCs will
3959 limit to loops not longer than the specified number of cells. This
3960 can e.g. be useful in identifying small local loops in a module that
3961 implements one large SCC.
3964 do not count cells that have their output fed back into one of their
3965 inputs as single-cell scc.
3968 Usually this command only considers internal non-memory cells. With
3969 this option set, all cells are considered. For unknown cells all ports
3970 are assumed to be bidirectional 'inout' ports.
3972 -set_attr <name> <value>
3973 set the specified attribute on all cells that are part of a logic
3974 loop. the special token
{} in the value is replaced with a unique
3975 identifier for the logic loop.
3978 replace the current selection with a selection of all cells and wires
3979 that are part of a found logic loop
3982 \section{scratchpad -- get/set values in the scratchpad
}
3983 \label{cmd:scratchpad
}
3984 \begin{lstlisting
}[numbers=left,frame=single
]
3985 scratchpad
[options
]
3987 This pass allows to read and modify values from the scratchpad of the current
3991 print the value saved in the scratchpad under the given identifier.
3993 -set <identifier> <value>
3994 save the given value in the scratchpad under the given identifier.
3997 remove the entry for the given identifier from the scratchpad.
3999 -copy <identifier_from> <identifier_to>
4000 copy the value of the first identifier to the second identifier.
4002 -assert <identifier> <value>
4003 assert that the entry for the given identifier is set to the given value.
4005 -assert-set <identifier>
4006 assert that the entry for the given identifier exists.
4008 -assert-unset <identifier>
4009 assert that the entry for the given identifier does not exist.
4011 The identifier may not contain whitespace. By convention, it is usually prefixed
4012 by the name of the pass that uses it, e.g. 'opt.did_something'. If the value
4013 contains whitespace, it must be enclosed in double quotes.
4016 \section{script -- execute commands from file or wire
}
4018 \begin{lstlisting
}[numbers=left,frame=single
]
4019 script <filename>
[<from_label>:<to_label>
]
4020 script -scriptwire
[selection
]
4022 This command executes the yosys commands in the specified file (default
4023 behaviour), or commands embedded in the constant text value connected to the
4026 In the default (file) case, the
2nd argument can be used to only execute the
4027 section of the file between the specified labels. An empty from label is
4028 synonymous with the beginning of the file and an empty to label is synonymous
4029 with the end of the file.
4031 If only one label is specified (without ':') then only the block
4032 marked with that label (until the next label) is executed.
4034 In "-scriptwire" mode, the commands on the selected wire(s) will be executed
4035 in the scope of (and thus, relative to) the wires' owning module(s). This
4036 '-module' mode can be exited by using the 'cd' command.
4039 \section{select -- modify and view the list of selected objects
}
4041 \begin{lstlisting
}[numbers=left,frame=single
]
4042 select
[ -add | -del | -set <name>
] {-read <filename> | <selection>
}
4043 select
[ <assert_option>
] {-read <filename> | <selection>
}
4044 select
[ -list | -write <filename> | -count | -clear
]
4045 select -module <modname>
4047 Most commands use the list of currently selected objects to determine which part
4048 of the design to operate on. This command can be used to modify and view this
4049 list of selected objects.
4051 Note that many commands support an optional
[selection
] argument that can be
4052 used to override the global selection for the command. The syntax of this
4053 optional argument is identical to the syntax of the <selection> argument
4057 add or remove the given objects to the current selection.
4058 without this options the current selection is replaced.
4061 do not modify the current selection. instead save the new selection
4062 under the given name (see @<name> below). to save the current selection,
4063 use "select -set <name>
%"
4066 do not modify the current selection. instead assert that the given
4067 selection is empty. i.e. produce an error if any object matching the
4071 do not modify the current selection. instead assert that the given
4072 selection is non-empty. i.e. produce an error if no object matching
4073 the selection is found.
4076 do not modify the current selection. instead assert that the given
4077 selection contains exactly N objects.
4080 do not modify the current selection. instead assert that the given
4081 selection contains less than or exactly N objects.
4084 do not modify the current selection. instead assert that the given
4085 selection contains at least N objects.
4088 list all objects in the current selection
4091 like -list but write the output to the specified file
4094 read the specified file (written by -write)
4097 count all objects in the current selection
4100 clear the current selection. this effectively selects the whole
4101 design. it also resets the selected module (see -module). use the
4102 command 'select *' to select everything but stay in the current module.
4105 create an empty selection. the current module is unchanged.
4108 limit the current scope to the specified module.
4109 the difference between this and simply selecting the module
4110 is that all object names are interpreted relative to this
4111 module after this command until the selection is cleared again.
4113 When this command is called without an argument, the current selection
4114 is displayed in a compact form (i.e. only the module name when a whole module
4117 The <selection> argument itself is a series of commands for a simple stack
4118 machine. Each element on the stack represents a set of selected objects.
4119 After this commands have been executed, the union of all remaining sets
4120 on the stack is computed and used as selection for the command.
4122 Pushing (selecting) object when not in -module mode:
4125 select the specified module(s)
4127 <mod_pattern>/<obj_pattern>
4128 select the specified object(s) from the module(s)
4130 Pushing (selecting) object when in -module mode:
4133 select the specified object(s) from the current module
4135 A <mod_pattern> can be a module name, wildcard expression
(*, ?, [..])
4136 matching module names, or one of the following:
4138 A:<pattern>, A:<pattern>=<pattern>
4139 all modules with an attribute matching the given pattern
4140 in addition to = also <, <=, >=, and > are supported
4143 all modules with a name matching the given pattern
4144 (i.e. 'N:' is optional as it is the default matching rule)
4146 An <obj_pattern> can be an object name, wildcard expression, or one of
4150 all wires with a name matching the given wildcard pattern
4152 i:<pattern>, o:<pattern>, x:<pattern>
4153 all inputs (i:), outputs (o:) or any ports (x:) with matching names
4155 s:<size>, s:<min>:<max>
4156 all wires with a matching width
4159 all memories with a name matching the given pattern
4162 all cells with a name matching the given pattern
4165 all cells with a type matching the given pattern
4168 all processes with a name matching the given pattern
4171 all objects with an attribute name matching the given pattern
4173 a:<pattern>=<pattern>
4174 all objects with a matching attribute name-value-pair.
4175 in addition to = also <, <=, >=, and > are supported
4177 r:<pattern>, r:<pattern>=<pattern>
4178 cells with matching parameters. also with <, <=, >= and >.
4181 all objects with a name matching the given pattern
4182 (i.e. 'n:' is optional as it is the default matching rule)
4185 push the selection saved prior with 'select -set <name> ...'
4187 The following actions can be performed on the top sets on the stack:
4190 push a copy of the current selection to the stack
4193 replace the stack with a union of all elements on it
4196 replace top set with its invert
4199 replace the two top sets on the stack with their union
4202 replace the two top sets on the stack with their intersection
4205 pop the top set from the stack and subtract it from the new top
4208 like %d but swap the roles of two top sets on the stack
4211 create a copy of the top set from the stack and push it
4213 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
4214 expand top set <num1> num times according to the specified rules.
4215 (i.e. select all cells connected to selected wires and select all
4216 wires connected to selected cells) The rules specify which cell
4217 ports to use for this. the syntax for a rule is a '-' for exclusion
4218 and a '+' for inclusion, followed by an optional comma separated
4219 list of cell types followed by an optional comma separated list of
4220 cell ports in square brackets. a rule can also be just a cell or wire
4221 name that limits the expansion (is included but does not go beyond).
4222 select at most <num2> objects. a warning message is printed when this
4223 limit is reached. When '*' is used instead of <num1> then the process
4224 is repeated until no further object are selected.
4226 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
4227 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
4228 similar to %x, but only select input (%ci) or output cones (%co)
4230 %xe[...] %cie[...] %coe
4231 like %x, %ci, and %co but only consider combinatorial cells
4234 expand top set by selecting all wires that are (at least in part)
4235 aliases for selected wires.
4238 expand top set by adding all modules that implement cells in selected
4242 expand top set by selecting all modules that contain selected objects
4245 select modules that implement selected cells
4248 select cells that implement selected modules
4251 select <num> random objects from top selection (default 1)
4253 Example: the following command selects all wires that are connected to a
4254 'GATE' input of a 'SWITCH' cell:
4256 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
4259 \section{setattr -- set/unset attributes on objects}
4261 \begin{lstlisting}[numbers=left,frame=single]
4262 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
4264 Set/unset the given attributes on the selected objects. String values must be
4265 passed in double quotes (").
4267 When called with -mod, this command will set and unset attributes on modules
4268 instead of objects within modules.
4271 \section{setparam -- set/unset parameters on objects}
4272 \label{cmd:setparam}
4273 \begin{lstlisting}[numbers=left,frame=single]
4274 setparam [ -type cell_type ] [ -set name value | -unset name ]... [selection]
4276 Set/unset the given parameters on the selected cells. String values must be
4277 passed in double quotes (").
4279 The -type option can be used to change the cell type of the selected cells.
4282 \section{setundef -- replace undef values with defined constants}
4283 \label{cmd:setundef}
4284 \begin{lstlisting}[numbers=left,frame=single]
4285 setundef [options] [selection]
4287 This command replaces undef (x) constants with defined (0/1) constants.
4290 also set undriven nets to constant values
4293 also expose undriven nets as inputs (use with -undriven)
4296 replace with bits cleared (0)
4299 replace with bits set (1)
4302 replace with undef (x) bits, may be used with -undriven
4305 replace with $anyseq drivers (for formal)
4308 replace with $anyconst drivers (for formal)
4311 replace with random bits using the specified integer as seed
4312 value for the random number generator.
4315 also create/update init values for flip-flops
4318 replace undef in cell parameters
4321 \section{sf2\_iobs -- SF2: insert IO buffers}
4322 \label{cmd:sf2_iobs}
4323 \begin{lstlisting}[numbers=left,frame=single]
4324 sf2_iobs [options] [selection]
4326 Add SF2 I/O buffers and global buffers to top module as needed.
4329 Insert PAD->global_net clock buffers
4332 \section{share -- perform sat-based resource sharing}
4334 \begin{lstlisting}[numbers=left,frame=single]
4335 share [options] [selection]
4337 This pass merges shareable resources into a single resource. A SAT solver
4338 is used to determine if two resources are share-able.
4341 Per default the selection of cells that is considered for sharing is
4342 narrowed using a list of cell types. With this option all selected
4343 cells are considered for resource sharing.
4345 IMPORTANT NOTE: If the -all option is used then no cells with internal
4346 state must be selected!
4349 Per default some heuristics are used to reduce the number of cells
4350 considered for resource sharing to only large resources. This options
4351 turns this heuristics off, resulting in much more cells being considered
4352 for resource sharing.
4355 Only consider the simple part of the control logic in SAT solving, resulting
4356 in much easier SAT problems at the cost of maybe missing some opportunities
4357 for resource sharing.
4360 Only perform the first N merges, then stop. This is useful for debugging.
4363 \section{shell -- enter interactive command mode}
4365 \begin{lstlisting}[numbers=left,frame=single]
4368 This command enters the interactive command mode. This can be useful
4369 in a script to interrupt the script at a certain point and allow for
4370 interactive inspection or manual synthesis of the design at this point.
4372 The command prompt of the interactive shell indicates the current
4373 selection (see 'help select'):
4376 the entire design is selected
4379 only part of the design is selected
4382 the entire module 'modname' is selected using 'select -module modname'
4385 only part of current module 'modname' is selected
4387 When in interactive shell, some errors (e.g. invalid command arguments)
4388 do not terminate yosys but return to the command prompt.
4390 This command is the default action if nothing else has been specified
4391 on the command line.
4393 Press Ctrl-D or type 'exit' to leave the interactive shell.
4396 \section{show -- generate schematics using graphviz}
4398 \begin{lstlisting}[numbers=left,frame=single]
4399 show [options] [selection]
4401 Create a graphviz DOT file for the selected part of the design and compile it
4402 to a graphics file (usually SVG or PostScript).
4405 Run the specified command with the graphics file as parameter.
4406 On Windows, this pauses yosys until the viewer exits.
4409 Generate a graphics file in the specified format. Use 'dot' to just
4410 generate a .dot file, or other <format> strings such as 'svg' or 'ps'
4411 to generate files in other formats (this calls the 'dot' command).
4413 -lib <verilog_or_ilang_file>
4414 Use the specified library file for determining whether cell ports are
4415 inputs or outputs. This option can be used multiple times to specify
4416 more than one library.
4418 note: in most cases it is better to load the library before calling
4419 show with 'read_verilog -lib <filename>'. it is also possible to
4420 load liberty files with 'read_liberty -lib <filename>'.
4423 generate <prefix>.* instead of ~/.yosys_show.*
4425 -color <color> <object>
4426 assign the specified color to the specified object. The object can be
4427 a single selection wildcard expressions or a saved set of objects in
4428 the @<name> syntax (see "help select" for details).
4430 -label <text> <object>
4431 assign the specified label text to the specified object. The object can
4432 be a single selection wildcard expressions or a saved set of objects in
4433 the @<name> syntax (see "help select" for details).
4436 Randomly assign colors to the wires. The integer argument is the seed
4437 for the random number generator. Change the seed value if the colored
4438 graph still is ambiguous. A seed of zero deactivates the coloring.
4440 -colorattr <attribute_name>
4441 Use the specified attribute to assign colors. A unique color is
4442 assigned to each unique value of this attribute.
4445 annotate buses with a label indicating the width of the bus.
4448 mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
4449 cell parameter) with an asterisk next to the port name.
4452 stretch the graph so all inputs are on the left side and all outputs
4453 (including inout ports) are on the right side.
4456 wait for the use to press enter to before returning
4459 enumerate objects with internal ($-prefixed) names
4462 do not abbreviate objects with internal ($-prefixed) names
4465 do not add the module name as graph title to the dot file
4468 don't run viewer in the background, IE wait for the viewer tool to
4469 exit before returning
4471 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
4472 specified, 'xdot' is used to display the schematic (POSIX systems only).
4474 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
4475 unless another prefix is specified using -prefix <prefix>.
4477 Yosys on Windows and YosysJS use different defaults: The output is written
4478 to 'show.dot' in the current directory and new viewer is launched each time
4479 the 'show' command is executed.
4482 \section{shregmap -- map shift registers}
4483 \label{cmd:shregmap}
4484 \begin{lstlisting}[numbers=left,frame=single]
4485 shregmap [options] [selection]
4487 This pass converts chains of $_DFF_[NP]_ gates to target specific shift register
4488 primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and
4489 will use the same interface as the original $_DFF_*_ cells. The cell parameter
4490 'DEPTH' will contain the depth of the shift register. Use a target-specific
4491 'techmap' map file to convert those cells to the actual target cells.
4494 minimum length of shift register (default = 2)
4495 (this is the length after -keep_before and -keep_after)
4498 maximum length of shift register (default = no limit)
4499 larger chains will be mapped to multiple shift register instances
4502 number of DFFs to keep before the shift register (default = 0)
4505 number of DFFs to keep after the shift register (default = 0)
4508 limit match to only positive or negative edge clocks. (default = any)
4510 -enpol pos|neg|none|any_or_none|any
4511 limit match to FFs with the specified enable polarity. (default = none)
4513 -match <cell_type>[:<d_port_name>:<q_port_name>]
4514 match the specified cells instead of $_DFF_N_ and $_DFF_P_. If
4515 ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used
4516 by default. E.g. the option '-clkpol pos' is just an alias for
4517 '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.
4520 instead of encoding the clock and enable polarity in the cell name by
4521 deriving from the original cell name, simply name all generated cells
4522 $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is
4523 used to denote cells without enable input. The ENPOL parameter is
4524 omitted when '-enpol none' (or no -enpol option) is passed.
4527 assume the shift register is automatically zero-initialized, so it
4528 becomes legal to merge zero initialized FFs into the shift register.
4531 map initialized registers to the shift reg, add an INIT parameter to
4532 generated cells with the initialization value. (first bit to shift out
4536 map to greenpak4 shift registers.
4539 \section{sim -- simulate the circuit}
4541 \begin{lstlisting}[numbers=left,frame=single]
4542 sim [options] [top-level]
4544 This command simulates the circuit using the given top-level module.
4547 write the simulation results to the given VCD file
4550 name of top-level clock input
4553 name of top-level clock input (inverse polarity)
4556 name of top-level reset input (active high)
4559 name of top-level inverted reset input (active low)
4562 number of cycles reset should stay active (default: 1)
4565 zero-initialize all uninitialized regs and memories
4568 number of cycles to simulate (default: 20)
4571 include all nets in VCD output, not just those with public names
4574 writeback mode: use final simulation state as new init state
4580 \section{simplemap -- mapping simple coarse-grain cells}
4581 \label{cmd:simplemap}
4582 \begin{lstlisting}[numbers=left,frame=single]
4583 simplemap [selection]
4585 This pass maps a small selection of simple coarse-grain cells to yosys gate
4586 primitives. The following internal cell types are mapped by this pass:
4588 $not, $pos, $and, $or, $xor, $xnor
4589 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
4590 $logic_not, $logic_and, $logic_or, $mux, $tribuf
4591 $sr, $ff, $dff, $dffsr, $adff, $dlatch
4594 \section{splice -- create explicit splicing cells}
4596 \begin{lstlisting}[numbers=left,frame=single]
4597 splice [options] [selection]
4599 This command adds $slice and $concat cells to the design to make the splicing
4600 of multi-bit signals explicit. This for example is useful for coarse grain
4601 synthesis, where dedicated hardware is needed to splice signals.
4604 only select the cell ports to rewire by the cell. if the selection
4605 contains a cell, than all cell inputs are rewired, if necessary.
4608 only select the cell ports to rewire by the wire. if the selection
4609 contains a wire, than all cell ports driven by this wire are wired,
4613 it is sufficient if the driver of any bit of a cell port is selected.
4614 by default all bits must be selected.
4617 also add $slice and $concat cells to drive otherwise unused wires.
4620 do not rewire selected module outputs.
4623 only rewire cell ports with the specified name. can be used multiple
4624 times. implies -no_output.
4627 do not rewire cell ports with the specified name. can be used multiple
4628 times. can not be combined with -port <name>.
4630 By default selected output wires and all cell ports of selected cells driven
4631 by selected wires are rewired.
4634 \section{splitnets -- split up multi-bit nets}
4635 \label{cmd:splitnets}
4636 \begin{lstlisting}[numbers=left,frame=single]
4637 splitnets [options] [selection]
4639 This command splits multi-bit nets into single-bit nets.
4641 -format char1[char2[char3]]
4642 the first char is inserted between the net name and the bit index, the
4643 second char is appended to the netname. e.g. -format () creates net
4644 names like 'mysignal(42)'. the 3rd character is the range separation
4645 character when creating multi-bit wires. the default is '[]:'.
4648 also split module ports. per default only internal signals are split.
4651 don't blindly split nets in individual bits. instead look at the driver
4652 and split nets so that no driver drives only part of a net.
4655 \section{stat -- print some statistics}
4657 \begin{lstlisting}[numbers=left,frame=single]
4658 stat [options] [selection]
4660 Print some statistics (number of objects) on the selected portion of the
4664 print design hierarchy with this module as top. if the design is fully
4665 selected and a module has the 'top' attribute set, this module is used
4666 default value for this option.
4668 -liberty <liberty_file>
4669 use cell area information from the provided liberty file
4672 print area estemate for the specified technology. Currently supported
4673 values for <technology>: xilinx, cmos
4676 annotate internal cell types with their word width.
4677 e.g. $add_8 for an 8 bit wide $add cell.
4680 \section{submod -- moving part of a module to a new submodule}
4682 \begin{lstlisting}[numbers=left,frame=single]
4683 submod [options] [selection]
4685 This pass identifies all cells with the 'submod' attribute and moves them to
4686 a newly created module. The value of the attribute is used as name for the
4687 cell that replaces the group of cells with the same attribute value.
4689 This pass can be used to create a design hierarchy in flat design. This can
4690 be useful for analyzing or reverse-engineering a design.
4692 This pass only operates on completely selected modules with no processes
4696 by default the cells are 'moved' from the source module and the source
4697 module will use an instance of the new module after this command is
4698 finished. call with -copy to not modify the source module.
4701 don't use the 'submod' attribute but instead use the selection. only
4702 objects from one module might be selected. the value of the -name option
4703 is used as the value of the 'submod' attribute instead.
4706 instead of creating submodule ports with public names, create ports with
4707 private names so that a subsequent 'flatten; clean' call will restore the
4708 original module with original public names.
4711 \section{supercover -- add hi/lo cover cells for each wire bit}
4712 \label{cmd:supercover}
4713 \begin{lstlisting}[numbers=left,frame=single]
4714 supercover [options] [selection]
4716 This command adds two cover cells for each bit of each selected wire, one
4717 checking for a hi signal level and one checking for lo level.
4720 \section{synth -- generic synthesis script}
4722 \begin{lstlisting}[numbers=left,frame=single]
4725 This command runs the default synthesis script. This command does not operate
4726 on partly selected designs.
4729 use the specified module as top module (default='top')
4732 automatically determine the top of the design hierarchy
4735 flatten the design before synthesis. this will pass '-auto-top' to
4736 'hierarchy' if no top module is specified.
4739 passed to 'fsm_recode' via 'fsm'
4742 perform synthesis for a k-LUT architecture.
4745 do not run FSM optimization
4748 do not run abc (as if yosys was compiled without ABC support)
4751 do not run 'alumacc' pass. i.e. keep arithmetic operators in
4752 their direct form ($add, $sub, etc.).
4755 passed to 'memory'. prohibits merging of FFs into memory read ports
4758 do not run SAT-based resource sharing
4760 -run <from_label>[:<to_label>]
4761 only run the commands between the labels (see below). an empty
4762 from label is synonymous to 'begin', and empty to label is
4763 synonymous to the end of the command list.
4766 use new ABC9 flow (EXPERIMENTAL)
4769 use FlowMap LUT techmapping instead of ABC
4772 The following commands are executed by this synthesis command:
4775 hierarchy -check [-top <top> | -auto-top]
4779 flatten (if -flatten)
4787 techmap -map +/cmp2lut.v -map +/cmp2lcu.v (if -lut)
4788 alumacc (unless -noalumacc)
4789 share (unless -noshare)
4801 techmap -map +/gate2lut.v (if -noabc and -lut)
4802 clean; opt_lut (if -noabc and -lut)
4803 flowmap -maxlut K (if -flowmap and -lut)
4805 abc -fast (unless -noabc, unless -lut)
4806 abc -fast -lut k (unless -noabc, if -lut)
4807 opt -fast (unless -noabc)
4815 \section{synth\_achronix -- synthesis for Acrhonix Speedster22i FPGAs.}
4816 \label{cmd:synth_achronix}
4817 \begin{lstlisting}[numbers=left,frame=single]
4818 synth_achronix [options]
4820 This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.
4823 use the specified module as top module (default='top')
4826 write the design to the specified Verilog netlist file. writing of an
4827 output file is omitted if this parameter is not specified.
4829 -run <from_label>:<to_label>
4830 only run the commands between the labels (see below). an empty
4831 from label is synonymous to 'begin', and empty to label is
4832 synonymous to the end of the command list.
4835 do not flatten design before synthesis
4838 run 'abc' with '-dff -D 1' options
4841 The following commands are executed by this synthesis command:
4844 read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v
4845 hierarchy -check -top <top>
4847 flatten: (unless -noflatten)
4857 opt -fast -mux_undef -undriven -fine -full
4860 dff2dffe -direct-match $_DFF_*
4862 techmap -map +/techmap.v
4865 setundef -undriven -zero
4866 abc -markgroups -dff -D 1 (only if -retime)
4873 iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I
4874 techmap -map +/achronix/speedster22i/cells_map.v
4883 write_verilog -nodec -attr2comment -defparam -renameprefix syn_ <file-name>
4886 \section{synth\_anlogic -- synthesis for Anlogic FPGAs}
4887 \label{cmd:synth_anlogic}
4888 \begin{lstlisting}[numbers=left,frame=single]
4889 synth_anlogic [options]
4891 This command runs synthesis for Anlogic FPGAs.
4894 use the specified module as top module
4897 write the design to the specified EDIF file. writing of an output file
4898 is omitted if this parameter is not specified.
4901 write the design to the specified JSON file. writing of an output file
4902 is omitted if this parameter is not specified.
4904 -run <from_label>:<to_label>
4905 only run the commands between the labels (see below). an empty
4906 from label is synonymous to 'begin', and empty to label is
4907 synonymous to the end of the command list.
4910 do not flatten design before synthesis
4913 run 'abc' with '-dff -D 1' options
4916 do not use EG_LOGIC_DRAM16X4 cells in output netlist
4919 The following commands are executed by this synthesis command:
4922 read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
4923 hierarchy -check -top <top>
4925 flatten: (unless -noflatten)
4934 map_lutram: (skip if -nolutram)
4935 memory_bram -rules +/anlogic/lutrams.txt
4936 techmap -map +/anlogic/lutrams_map.v
4937 setundef -zero -params t:EG_LOGIC_DRAM16X4
4940 opt -fast -mux_undef -undriven -fine
4945 techmap -map +/techmap.v -map +/anlogic/arith_map.v
4947 abc -dff -D 1 (only if -retime)
4950 techmap -D NO_LUT -map +/anlogic/cells_map.v
4951 dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
4960 techmap -map +/anlogic/cells_map.v
4973 write_edif <file-name>
4976 write_json <file-name>
4979 \section{synth\_coolrunner2 -- synthesis for Xilinx Coolrunner-II CPLDs}
4980 \label{cmd:synth_coolrunner2}
4981 \begin{lstlisting}[numbers=left,frame=single]
4982 synth_coolrunner2 [options]
4984 This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.
4985 It is intended to be used with https://github.com/azonenberg/openfpga as the
4989 use the specified module as top module (default='top')
4992 write the design to the specified JSON file. writing of an output file
4993 is omitted if this parameter is not specified.
4995 -run <from_label>:<to_label>
4996 only run the commands between the labels (see below). an empty
4997 from label is synonymous to 'begin', and empty to label is
4998 synonymous to the end of the command list.
5001 do not flatten design before synthesis
5004 run 'abc' with '-dff -D 1' options
5007 The following commands are executed by this synthesis command:
5010 read_verilog -lib +/coolrunner2/cells_sim.v
5011 hierarchy -check -top <top>
5013 flatten: (unless -noflatten)
5022 extract_counter -dir up -allow_arst no
5023 techmap -map +/coolrunner2/cells_counter_map.v
5026 techmap -map +/techmap.v -map +/coolrunner2/cells_latch.v
5028 dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib
5033 extract -map +/coolrunner2/tff_extract.v
5036 abc -sop -I 40 -P 56
5040 dfflibmap -liberty +/coolrunner2/xc2_dff.lib
5041 dffinit -ff FDCP Q INIT
5042 dffinit -ff FDCP_N Q INIT
5043 dffinit -ff FTCP Q INIT
5044 dffinit -ff FTCP_N Q INIT
5045 dffinit -ff LDCP Q INIT
5046 dffinit -ff LDCP_N Q INIT
5049 iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO
5050 attrmvcp -attr src -attr LOC t:IOBUFE n:*
5051 attrmvcp -attr src -attr LOC -driven t:IBUF n:*
5062 write_json <file-name>
5065 \section{synth\_easic -- synthesis for eASIC platform}
5066 \label{cmd:synth_easic}
5067 \begin{lstlisting}[numbers=left,frame=single]
5068 synth_easic [options]
5070 This command runs synthesis for eASIC platform.
5073 use the specified module as top module
5076 write the design to the specified structural Verilog file. writing of
5077 an output file is omitted if this parameter is not specified.
5080 set path to the eTools installation. (default=/opt/eTools)
5082 -run <from_label>:<to_label>
5083 only run the commands between the labels (see below). an empty
5084 from label is synonymous to 'begin', and empty to label is
5085 synonymous to the end of the command list.
5088 do not flatten design before synthesis
5091 run 'abc' with '-dff -D 1' options
5094 The following commands are executed by this synthesis command:
5097 read_liberty -lib <etools_phys_clk_lib>
5098 read_liberty -lib <etools_logic_lut_lib>
5099 hierarchy -check -top <top>
5101 flatten: (unless -noflatten)
5109 opt -fast -mux_undef -undriven -fine
5114 abc -dff -D 1 (only if -retime)
5115 opt_clean (only if -retime)
5118 dfflibmap -liberty <etools_phys_clk_lib>
5119 abc -liberty <etools_logic_lut_lib>
5128 write_verilog -noexpr -attr2comment <file-name>
5131 \section{synth\_ecp5 -- synthesis for ECP5 FPGAs}
5132 \label{cmd:synth_ecp5}
5133 \begin{lstlisting}[numbers=left,frame=single]
5134 synth_ecp5 [options]
5136 This command runs synthesis for ECP5 FPGAs.
5139 use the specified module as top module
5142 write the design to the specified BLIF file. writing of an output file
5143 is omitted if this parameter is not specified.
5146 write the design to the specified EDIF file. writing of an output file
5147 is omitted if this parameter is not specified.
5150 write the design to the specified JSON file. writing of an output file
5151 is omitted if this parameter is not specified.
5153 -run <from_label>:<to_label>
5154 only run the commands between the labels (see below). an empty
5155 from label is synonymous to 'begin', and empty to label is
5156 synonymous to the end of the command list.
5159 do not flatten design before synthesis
5162 run 'abc' with '-dff -D 1' options
5165 do not use CCU2 cells in output netlist
5168 do not use flipflops with CE in output netlist
5171 do not use block RAM cells in output netlist
5174 do not use LUT RAM cells in output netlist
5177 do not use PFU muxes to implement LUTs larger than LUT4s
5180 use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)
5183 run two passes of 'abc' for slightly improved logic density
5186 use new ABC9 flow (EXPERIMENTAL)
5189 generate an output netlist (and BLIF file) suitable for VPR
5190 (this feature is experimental and incomplete)
5193 do not map multipliers to MULT18X18D
5196 The following commands are executed by this synthesis command:
5199 read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v
5200 hierarchy -check -top <top>
5215 techmap -map +/cmp2lut.v -D LUT_WIDTH=4
5218 techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18 (unless -nodsp)
5219 chtype -set $mul t:$__soft_mul (unless -nodsp)
5227 map_bram: (skip if -nobram)
5228 memory_bram -rules +/ecp5/brams.txt
5229 techmap -map +/ecp5/brams_map.v
5231 map_lutram: (skip if -nolutram)
5232 memory_bram -rules +/ecp5/lutrams.txt
5233 techmap -map +/ecp5/lutrams_map.v
5236 opt -fast -mux_undef -undriven -fine
5237 memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic
5241 techmap -map +/techmap.v -map +/ecp5/arith_map.v
5243 abc -dff -D 1 (only if -retime)
5248 dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
5249 techmap -D NO_LUT [-D ASYNC_PRLD] -map +/ecp5/cells_map.v
5250 opt_expr -undriven -mux_undef
5254 attrmvcp -copy -attr syn_useioff
5259 techmap -map +/ecp5/latches_map.v
5264 techmap -map +/ecp5/cells_map.v (with -D NO_LUT in vpr mode)
5265 opt_lut_ins -tech ecp5
5275 opt_clean -purge (vpr mode)
5276 write_blif -attr -cname -conn -param <file-name> (vpr mode)
5277 write_blif -gates -attr -param <file-name> (non-vpr mode)
5280 write_edif <file-name>
5283 write_json <file-name>
5286 \section{synth\_efinix -- synthesis for Efinix FPGAs}
5287 \label{cmd:synth_efinix}
5288 \begin{lstlisting}[numbers=left,frame=single]
5289 synth_efinix [options]
5291 This command runs synthesis for Efinix FPGAs.
5294 use the specified module as top module
5297 write the design to the specified EDIF file. writing of an output file
5298 is omitted if this parameter is not specified.
5301 write the design to the specified JSON file. writing of an output file
5302 is omitted if this parameter is not specified.
5304 -run <from_label>:<to_label>
5305 only run the commands between the labels (see below). an empty
5306 from label is synonymous to 'begin', and empty to label is
5307 synonymous to the end of the command list.
5310 do not flatten design before synthesis
5313 run 'abc' with '-dff -D 1' options
5316 do not use EFX_RAM_5K cells in output netlist
5319 The following commands are executed by this synthesis command:
5322 read_verilog -lib +/efinix/cells_sim.v
5323 hierarchy -check -top <top>
5325 flatten: (unless -noflatten)
5333 memory_bram -rules +/efinix/brams.txt
5334 techmap -map +/efinix/brams_map.v
5335 setundef -zero -params t:EFX_RAM_5K
5338 opt -fast -mux_undef -undriven -fine
5343 techmap -map +/techmap.v -map +/efinix/arith_map.v
5345 abc -dff -D 1 (only if -retime)
5348 techmap -D NO_LUT -map +/efinix/cells_map.v
5349 dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
5358 techmap -map +/efinix/cells_map.v
5372 write_edif <file-name>
5375 write_json <file-name>
5378 \section{synth\_gowin -- synthesis for Gowin FPGAs}
5379 \label{cmd:synth_gowin}
5380 \begin{lstlisting}[numbers=left,frame=single]
5381 synth_gowin [options]
5383 This command runs synthesis for Gowin FPGAs. This work is experimental.
5386 use the specified module as top module (default='top')
5389 write the design to the specified Verilog netlist file. writing of an
5390 output file is omitted if this parameter is not specified.
5392 -run <from_label>:<to_label>
5393 only run the commands between the labels (see below). an empty
5394 from label is synonymous to 'begin', and empty to label is
5395 synonymous to the end of the command list.
5398 do not use flipflops with CE in output netlist
5401 do not use BRAM cells in output netlist
5404 do not use distributed RAM cells in output netlist
5407 do not flatten design before synthesis
5410 run 'abc' with '-dff -D 1' options
5413 do not use muxes to implement LUTs larger than LUT4s
5416 do not emit IOB at top level ports
5419 The following commands are executed by this synthesis command:
5422 read_verilog -lib +/gowin/cells_sim.v
5423 hierarchy -check -top <top>
5425 flatten: (unless -noflatten)
5434 map_bram: (skip if -nobram)
5435 memory_bram -rules +/gowin/brams.txt
5436 techmap -map +/gowin/brams_map.v
5438 map_lutram: (skip if -nolutram)
5439 memory_bram -rules +/gowin/lutrams.txt
5440 techmap -map +/gowin/lutrams_map.v
5444 opt -fast -mux_undef -undriven -fine
5449 techmap -map +/techmap.v -map +/gowin/arith_map.v
5451 abc -dff -D 1 (only if -retime)
5455 dff2dffs -match-init
5457 dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
5458 techmap -map +/gowin/cells_map.v
5467 techmap -map +/gowin/cells_map.v
5468 opt_lut_ins -tech gowin
5469 setundef -undriven -params -zero
5470 hilomap -singleton -hicell VCC V -locell GND G
5471 iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO (unless -noiopads)
5480 write_verilog -decimal -attr2comment -defparam -renameprefix gen <file-name>
5483 \section{synth\_greenpak4 -- synthesis for GreenPAK4 FPGAs}
5484 \label{cmd:synth_greenpak4}
5485 \begin{lstlisting}[numbers=left,frame=single]
5486 synth_greenpak4 [options]
5488 This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
5489 It is intended to be used with https://github.com/azonenberg/openfpga as the
5493 use the specified module as top module (default='top')
5496 synthesize for the specified part. Valid values are SLG46140V,
5497 SLG46620V, and SLG46621V (default).
5500 write the design to the specified JSON file. writing of an output file
5501 is omitted if this parameter is not specified.
5503 -run <from_label>:<to_label>
5504 only run the commands between the labels (see below). an empty
5505 from label is synonymous to 'begin', and empty to label is
5506 synonymous to the end of the command list.
5509 do not flatten design before synthesis
5512 run 'abc' with '-dff -D 1' options
5515 The following commands are executed by this synthesis command:
5518 read_verilog -lib +/greenpak4/cells_sim.v
5519 hierarchy -check -top <top>
5521 flatten: (unless -noflatten)
5530 extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14
5532 opt -fast -mux_undef -undriven -fine
5535 techmap -map +/techmap.v -map +/greenpak4/cells_latch.v
5536 dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
5538 abc -dff -D 1 (only if -retime)
5541 nlutmap -assert -luts 0,6,8,2 (for -part SLG46140V)
5542 nlutmap -assert -luts 2,8,16,2 (for -part SLG46620V)
5543 nlutmap -assert -luts 2,8,16,2 (for -part SLG46621V)
5547 shregmap -tech greenpak4
5548 dfflibmap -liberty +/greenpak4/gp_dff.lib
5549 dffinit -ff GP_DFF Q INIT
5550 dffinit -ff GP_DFFR Q INIT
5551 dffinit -ff GP_DFFS Q INIT
5552 dffinit -ff GP_DFFSR Q INIT
5553 iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO
5554 attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*
5555 attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*
5556 techmap -map +/greenpak4/cells_map.v
5566 write_json <file-name>
5569 \section{synth\_ice40 -- synthesis for iCE40 FPGAs}
5570 \label{cmd:synth_ice40}
5571 \begin{lstlisting}[numbers=left,frame=single]
5572 synth_ice40 [options]
5574 This command runs synthesis for iCE40 FPGAs.
5576 -device < hx | lp | u >
5577 relevant only for '-abc9' flow, optimise timing for the specified device.
5581 use the specified module as top module
5584 write the design to the specified BLIF file. writing of an output file
5585 is omitted if this parameter is not specified.
5588 write the design to the specified EDIF file. writing of an output file
5589 is omitted if this parameter is not specified.
5592 write the design to the specified JSON file. writing of an output file
5593 is omitted if this parameter is not specified.
5595 -run <from_label>:<to_label>
5596 only run the commands between the labels (see below). an empty
5597 from label is synonymous to 'begin', and empty to label is
5598 synonymous to the end of the command list.
5601 do not flatten design before synthesis
5604 run 'abc' with '-dff -D 1' options
5607 do not use SB_CARRY cells in output netlist
5610 do not use SB_DFFE* cells in output netlist
5612 -dffe_min_ce_use <min_ce_use>
5613 do not use SB_DFFE* cells if the resulting CE line would go to less
5614 than min_ce_use SB_DFFE* in output netlist
5617 do not use SB_RAM40_4K* cells in output netlist
5620 use iCE40 UltraPlus DSP cells for large arithmetic
5623 use built-in Yosys LUT techmapping instead of abc
5626 run two passes of 'abc' for slightly improved logic density
5629 generate an output netlist (and BLIF file) suitable for VPR
5630 (this feature is experimental and incomplete)
5633 use new ABC9 flow (EXPERIMENTAL)
5636 use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)
5639 The following commands are executed by this synthesis command:
5642 read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v
5643 hierarchy -check -top <top>
5646 flatten: (unless -noflatten)
5660 techmap -map +/cmp2lut.v -D LUT_WIDTH=4
5665 techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16 (if -dsp)
5666 select a:mul2dsp (if -dsp)
5667 setattr -unset mul2dsp (if -dsp)
5668 opt_expr -fine (if -dsp)
5670 select -clear (if -dsp)
5672 chtype -set $mul t:$__soft_mul (if -dsp)
5680 map_bram: (skip if -nobram)
5681 memory_bram -rules +/ice40/brams.txt
5682 techmap -map +/ice40/brams_map.v
5686 opt -fast -mux_undef -undriven -fine
5687 memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic
5692 techmap -map +/techmap.v -map +/ice40/arith_map.v
5694 abc -dff -D 1 (only if -retime)
5698 dff2dffe -direct-match $_DFF_*
5699 techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v
5708 ice40_opt (only if -abc2)
5709 techmap -map +/ice40/latches_map.v
5710 simplemap (if -noabc or -flowmap)
5711 techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc)
5712 flowmap -maxlut 4 (only if -flowmap)
5713 abc -dress -lut 4 (skip if -noabc)
5714 ice40_wrapcarry -unwrap
5715 techmap -D NO_LUT -map +/ice40/cells_map.v
5717 opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0
5720 techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode)
5730 opt_clean -purge (vpr mode)
5731 write_blif -attr -cname -conn -param <file-name> (vpr mode)
5732 write_blif -gates -attr -param <file-name> (non-vpr mode)
5735 write_edif <file-name>
5738 write_json <file-name>
5741 \section{synth\_intel -- synthesis for Intel (Altera) FPGAs.}
5742 \label{cmd:synth_intel}
5743 \begin{lstlisting}[numbers=left,frame=single]
5744 synth_intel [options]
5746 This command runs synthesis for Intel FPGAs.
5748 -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>
5749 generate the synthesis netlist for the specified family.
5750 MAX10 is the default target if no family argument specified.
5751 For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.
5752 Cyclone V and Arria 10 GX devices are experimental.
5755 use the specified module as top module (default='top')
5758 write the design to the specified Verilog Quartus Mapping File. Writing of an
5759 output file is omitted if this parameter is not specified.
5760 Note that this backend has not been tested and is likely incompatible
5761 with recent versions of Quartus.
5764 write BLIF files for VPR flow experiments. The synthesized BLIF output file is not
5765 compatible with the Quartus flow. Writing of an
5766 output file is omitted if this parameter is not specified.
5768 -run <from_label>:<to_label>
5769 only run the commands between the labels (see below). an empty
5770 from label is synonymous to 'begin', and empty to label is
5771 synonymous to the end of the command list.
5774 use IO pad cells in output netlist
5777 do not use block RAM cells in output netlist
5780 do not flatten design before synthesis
5783 run 'abc' with '-dff -D 1' options
5785 The following commands are executed by this synthesis command:
5790 read_verilog -sv -lib +/intel/max10/cells_sim.v
5791 read_verilog -sv -lib +/intel/common/m9k_bb.v
5792 read_verilog -sv -lib +/intel/common/altpll_bb.v
5793 hierarchy -check -top <top>
5795 flatten: (unless -noflatten)
5804 map_bram: (skip if -nobram)
5805 memory_bram -rules +/intel/common/brams_m9k.txt (if applicable for family)
5806 techmap -map +/intel/common/brams_map_m9k.v (if applicable for family)
5809 opt -fast -mux_undef -undriven -fine -full
5812 dff2dffe -direct-match $_DFF_*
5814 techmap -map +/techmap.v
5817 setundef -undriven -zero
5818 abc -markgroups -dff -D 1 (only if -retime)
5825 iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I (if -iopads)
5826 techmap -map +/intel/max10/cells_map.v
5827 dffinit -highlow -ff dffeas q power_up
5836 write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ <file-name>
5840 write_blif <file-name>
5843 WARNING: THE 'synth_intel' COMMAND IS EXPERIMENTAL.
5846 \section{synth\_sf2 -- synthesis for SmartFusion2 and IGLOO2 FPGAs}
5847 \label{cmd:synth_sf2}
5848 \begin{lstlisting}[numbers=left,frame=single]
5851 This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.
5854 use the specified module as top module
5857 write the design to the specified EDIF file. writing of an output file
5858 is omitted if this parameter is not specified.
5861 write the design to the specified Verilog file. writing of an output file
5862 is omitted if this parameter is not specified.
5865 write the design to the specified JSON file. writing of an output file
5866 is omitted if this parameter is not specified.
5868 -run <from_label>:<to_label>
5869 only run the commands between the labels (see below). an empty
5870 from label is synonymous to 'begin', and empty to label is
5871 synonymous to the end of the command list.
5874 do not flatten design before synthesis
5877 run synthesis in "block mode", i.e. do not insert IO buffers
5880 insert direct PAD->global_net buffers
5883 run 'abc' with '-dff -D 1' options
5886 The following commands are executed by this synthesis command:
5889 read_verilog -lib +/sf2/cells_sim.v
5890 hierarchy -check -top <top>
5892 flatten: (unless -noflatten)
5902 opt -fast -mux_undef -undriven -fine
5905 techmap -map +/techmap.v -map +/sf2/arith_map.v
5907 abc -dff -D 1 (only if -retime)
5910 techmap -D NO_LUT -map +/sf2/cells_map.v
5919 techmap -map +/sf2/cells_map.v
5923 sf2_iobs [-clkbuf] (unless -noiobs)
5932 write_edif -gndvccy <file-name>
5935 write_verilog <file-name>
5938 write_json <file-name>
5941 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
5942 \label{cmd:synth_xilinx}
5943 \begin{lstlisting}[numbers=left,frame=single]
5944 synth_xilinx [options]
5946 This command runs synthesis for Xilinx FPGAs. This command does not operate on
5947 partly selected designs. At the moment this command creates netlists that are
5948 compatible with 7-Series Xilinx devices.
5951 use the specified module as top module
5954 run synthesis for the specified Xilinx architecture
5955 generate the synthesis netlist for the specified family.
5957 - xcup: Ultrascale Plus
5959 - xc7: Series 7 (default)
5962 - xc5v: Virtex 5 (EXPERIMENTAL)
5963 - xc4v: Virtex 4 (EXPERIMENTAL)
5964 - xc3sda: Spartan 3A DSP (EXPERIMENTAL)
5965 - xc3sa: Spartan 3A (EXPERIMENTAL)
5966 - xc3se: Spartan 3E (EXPERIMENTAL)
5967 - xc3s: Spartan 3 (EXPERIMENTAL)
5968 - xc2vp: Virtex 2 Pro (EXPERIMENTAL)
5969 - xc2v: Virtex 2 (EXPERIMENTAL)
5970 - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)
5971 - xcv: Virtex, Spartan 2 (EXPERIMENTAL)
5974 write the design to the specified edif file. writing of an output file
5975 is omitted if this parameter is not specified.
5978 write the design to the specified BLIF file. writing of an output file
5979 is omitted if this parameter is not specified.
5982 generate an output netlist (and BLIF file) suitable for VPR
5983 (this feature is experimental and incomplete)
5986 generate an output netlist suitable for ISE
5989 do not use block RAM cells in output netlist
5992 do not use distributed RAM cells in output netlist
5995 do not use distributed SRL cells in output netlist
5998 do not use XORCY/MUXCY/CARRY4 cells in output netlist
6001 do not use MUXF[5-9] resources to implement LUTs larger than native for the target
6004 do not use DSP48*s to implement multipliers and associated logic
6007 disable I/O buffer insertion (useful for hierarchical or
6008 out-of-context flows)
6011 disable automatic clock buffer insertion
6014 infer URAM288s for large memories (xcup only)
6017 enable inference of hard multiplexer resources (MUXF[78]) for muxes at or
6018 above this number of inputs (minimum value 2, recommended value >= 5).
6019 default: 0 (no inference)
6021 -run <from_label>:<to_label>
6022 only run the commands between the labels (see below). an empty
6023 from label is synonymous to 'begin', and empty to label is
6024 synonymous to the end of the command list.
6027 flatten design before synthesis
6030 run 'abc'/'abc9' with -dff option
6033 run 'abc' with '-D 1' option to enable flip-flop retiming.
6037 use new ABC9 flow (EXPERIMENTAL)
6040 The following commands are executed by this synthesis command:
6043 read_verilog -lib -specify +/xilinx/cells_sim.v
6044 read_verilog -lib +/xilinx/cells_xtra.v
6045 hierarchy -check -auto-top
6049 flatten (with '-flatten')
6056 wreduce [-keepdc] (option for '-widemux')
6059 muxpack ('-widemux' only)
6060 pmux2shiftx (skip if '-nosrl' and '-widemux=0')
6061 clean (skip if '-nosrl' and '-widemux=0')
6063 map_dsp: (skip if '-nodsp')
6065 techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}
6067 setattr -unset mul2dsp
6071 xilinx_dsp -family <family>
6072 chtype -set $mul t:$__soft_mul
6075 techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=[46]
6084 map_uram: (only if '-uram')
6085 memory_bram -rules +/xilinx/{family}_urams.txt
6086 techmap -map +/xilinx/{family}_urams_map.v
6088 map_bram: (skip if '-nobram')
6089 memory_bram -rules +/xilinx/{family}_brams.txt
6090 techmap -map +/xilinx/{family}_brams_map.v
6092 map_lutram: (skip if '-nolutram')
6093 memory_bram -rules +/xilinx/lut[46]_lutrams.txt
6094 techmap -map +/xilinx/lutrams_map.v
6097 simplemap t:$dff t:$adff t:$mux
6098 dff2dffs [-match-init] (-match-init for xc6s only)
6103 dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
6104 muxcover <internal options> ('-widemux' only)
6106 xilinx_srl -variable -minlen 3 (skip if '-nosrl')
6107 techmap -map +/techmap.v -D LUT_SIZE=[46] [-map +/xilinx/mux_map.v] -map +/xilinx/arith_map.v
6111 iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top (skip if '-noiopad')
6112 techmap -map +/techmap.v -map +/xilinx/cells_map.v
6116 techmap -map +/xilinx/{family}_ff_map.v ('-abc9' only)
6120 abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1] (option for 'nowidelut', '-dff', '-retime')
6122 xilinx_srl -fixed -minlen 3 (skip if '-nosrl')
6123 techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/{family}_ff_map.v -D LUT_WIDTH=[46]
6124 xilinx_dffopt [-lut4]
6125 opt_lut_ins -tech xilinx
6128 clkbufmap -buf BUFG O:I (skip if '-noclkbuf')
6129 extractinv -inv INV O:I (only if '-ise')
6138 write_edif -pvector bra
6144 \section{tcl -- execute a TCL script file}
6146 \begin{lstlisting}[numbers=left,frame=single]
6147 tcl <filename> [args]
6149 This command executes the tcl commands in the specified file.
6150 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
6152 The tcl command 'yosys -import' can be used to import all yosys
6153 commands directly as tcl commands to the tcl shell. Yosys commands
6154 'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'
6155 in order to avoid a name collision with the built in commands.
6157 If any arguments are specified, these arguments are provided to the script via
6158 the standard $argc and $argv variables.
6161 \section{techmap -- generic technology mapper}
6163 \begin{lstlisting}[numbers=left,frame=single]
6164 techmap [-map filename] [selection]
6166 This pass implements a very simple technology mapper that replaces cells in
6167 the design with implementations given in form of a Verilog or ilang source
6171 the library of cell implementations to be used.
6172 without this parameter a builtin library is used that
6173 transforms the internal RTL cells to the internal gate
6177 like -map above, but with an in-memory design instead of a file.
6180 load the cell implementations as separate modules into the design
6181 instead of inlining them.
6184 only run the specified number of iterations on each module.
6188 instead of the iterative breadth-first algorithm use a recursive
6189 depth-first algorithm. both methods should yield equivalent results,
6190 but may differ in performance.
6193 Automatically call "proc" on implementations that contain processes.
6196 Ignore the 'whitebox' attribute on cell implementations.
6199 this option will cause techmap to exit with an error if it can't map
6200 a selected cell. only cell types that end on an underscore are accepted
6201 as final cell types by this mode.
6203 -D <define>, -I <incdir>
6204 this options are passed as-is to the Verilog frontend for loading the
6205 map file. Note that the Verilog frontend is also called with the
6206 '-nooverwrite' option set.
6208 When a module in the map file has the 'techmap_celltype' attribute set, it will
6209 match cells with a type that match the text value of this attribute. Otherwise
6210 the module name will be used to match the cell.
6212 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
6213 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
6215 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
6216 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
6218 When a module in the map file has the 'techmap_wrap' attribute set, techmap
6219 will create a wrapper for the cell and then run the command string that the
6220 attribute is set to on the wrapper module.
6222 When a port on a module in the map file has the 'techmap_autopurge' attribute
6223 set, and that port is not connected in the instantiation that is mapped, then
6224 then a cell port connected only to such wires will be omitted in the mapped
6225 version of the circuit.
6227 All wires in the modules from the map file matching the pattern _TECHMAP_*
6228 or *._TECHMAP_* are special wires that are used to pass instructions from
6229 the mapping module to the techmap command. At the moment the following special
6230 wires are supported:
6233 When this wire is set to a non-zero constant value, techmap will not
6234 use this module and instead try the next module with a matching
6235 'techmap_celltype' attribute.
6237 When such a wire exists but does not have a constant value after all
6238 _TECHMAP_DO_* commands have been executed, an error is generated.
6241 This wires are evaluated in alphabetical order. The constant text value
6242 of this wire is a yosys command (or sequence of commands) that is run
6243 by techmap on the module. A common use case is to run 'proc' on modules
6244 that are written using always-statements.
6246 When such a wire has a non-constant value at the time it is to be
6247 evaluated, an error is produced. That means it is possible for such a
6248 wire to start out as non-constant and evaluate to a constant value
6249 during processing of other _TECHMAP_DO_* commands.
6251 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
6252 in this case techmap will create a copy for each distinct configuration
6253 of constant inputs and shorted inputs at this point and import the
6254 constant and connected bits into the map module. All further commands
6255 are executed in this copy. This is a very convenient way of creating
6256 optimized specializations of techmap modules without using the special
6257 parameters described below.
6259 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
6260 then techmap will recursively replace the cells in the module with their
6261 implementation. This is not affected by the -max_iter option.
6263 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
6265 _TECHMAP_REMOVEINIT_<port-name>_
6266 When this wire is set to a constant value, the init attribute of the wire(s)
6267 connected to this port will be consumed. This wire must have the same
6268 width as the given port, and for every bit that is set to 1 in the value,
6269 the corresponding init attribute bit will be changed to 1'bx. If all
6270 bits of an init attribute are left as x, it will be removed.
6272 In addition to this special wires, techmap also supports special parameters in
6273 modules in the map file:
6276 When a parameter with this name exists, it will be set to the type name
6277 of the cell that matches the module.
6279 _TECHMAP_CONSTMSK_<port-name>_
6280 _TECHMAP_CONSTVAL_<port-name>_
6281 When this pair of parameters is available in a module for a port, then
6282 former has a 1-bit for each constant input bit and the latter has the
6283 value for this bit. The unused bits of the latter are set to undef (x).
6285 _TECHMAP_WIREINIT_<port-name>_
6286 When a parameter with this name exists, it will be set to the initial
6287 value of the wire(s) connected to the given port, as specified by the init
6288 attribute. If the attribute doesn't exist, x will be filled for the
6289 missing bits. To remove the init attribute bits used, use the
6290 _TECHMAP_REMOVEINIT_*_ wires.
6292 _TECHMAP_BITS_CONNMAP_
6293 _TECHMAP_CONNMAP_<port-name>_
6294 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
6295 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
6296 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
6297 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
6298 This can be used to detect shorted inputs.
6300 When a module in the map file has a parameter where the according cell in the
6301 design has a port, the module from the map file is only used if the port in
6302 the design is connected to a constant value. The parameter is then set to the
6305 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
6306 and attributes of the cell that is being replaced.
6307 A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will
6308 be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name
6309 of the cell being replaced.
6310 Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a
6311 new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'
6312 prefix also substituted.
6314 See 'help extract' for a pass that does the opposite thing.
6316 See 'help flatten' for a pass that does flatten the design (which is
6317 essentially techmap but using the design itself as map library).
6320 \section{tee -- redirect command output to file}
6322 \begin{lstlisting}[numbers=left,frame=single]
6323 tee [-q] [-o logfile|-a logfile] cmd
6325 Execute the specified command, optionally writing the commands output to the
6326 specified logfile(s).
6329 Do not print output to the normal destination (console and/or log file).
6332 Write output to this file, truncate if exists.
6335 Write output to this file, append if exists.
6338 Add/subtract INT from the -v setting for this command.
6341 \section{test\_abcloop -- automatically test handling of loops in abc command}
6342 \label{cmd:test_abcloop}
6343 \begin{lstlisting}[numbers=left,frame=single]
6344 test_abcloop [options]
6346 Test handling of logic loops in ABC.
6349 create this number of circuits and test them (default = 100).
6351 -s {positive_integer}
6352 use this value as rng seed value (default = unix time).
6355 \section{test\_autotb -- generate simple test benches}
6356 \label{cmd:test_autotb}
6357 \begin{lstlisting}[numbers=left,frame=single]
6358 test_autotb [options] [filename]
6360 Automatically create primitive Verilog test benches for all modules in the
6361 design. The generated testbenches toggle the input pins of the module in
6362 a semi-random manner and dumps the resulting output signals.
6364 This can be used to check the synthesis results for simple circuits by
6365 comparing the testbench output for the input files and the synthesis results.
6367 The backend automatically detects clock signals. Additionally a signal can
6368 be forced to be interpreted as clock signal by setting the attribute
6369 'gentb_clock' on the signal.
6371 The attribute 'gentb_constant' can be used to force a signal to a constant
6372 value after initialization. This can e.g. be used to force a reset signal
6373 low in order to explore more inner states in a state machine.
6375 The attribute 'gentb_skip' can be attached to modules to suppress testbench
6379 number of iterations the test bench should run (default = 1000)
6382 seed used for pseudo-random number generation (default = 0).
6383 a value of 0 will cause an arbitrary seed to be chosen, based on
6384 the current system time.
6387 \section{test\_cell -- automatically test the implementation of a cell type}
6388 \label{cmd:test_cell}
6389 \begin{lstlisting}[numbers=left,frame=single]
6390 test_cell [options] {cell-types}
6392 Tests the internal implementation of the given cell type (for example '$add')
6393 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
6395 Run with 'all' instead of a cell type to run the test on all supported
6396 cell types. Use for example 'all /$add' for all cell types except $add.
6399 create this number of cell instances and test them (default = 100).
6401 -s {positive_integer}
6402 use this value as rng seed value (default = unix time).
6405 don't generate circuits. instead load the specified ilang file.
6407 -w {filename_prefix}
6408 don't test anything. just generate the circuits and write them
6409 to ilang files with the specified prefix
6412 pass this option to techmap.
6415 use "techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc"
6418 instead of calling "techmap", call "aigmap"
6421 when creating test benches with dividers, create an additional mux
6422 to mask out the division-by-zero case
6424 -script {script_file}
6425 instead of calling "techmap", call "script {script_file}".
6428 set some input bits to random constant values
6431 do not check SAT model or run SAT equivalence checking
6434 do not check const-eval models
6437 test cell edges db creator against sat-based implementation
6440 print additional debug information to the console
6443 create a Verilog test bench to test simlib and write_verilog
6446 \section{test\_pmgen -- test pass for pmgen}
6447 \label{cmd:test_pmgen}
6448 \begin{lstlisting}[numbers=left,frame=single]
6449 test_pmgen -reduce_chain [options] [selection]
6451 Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.
6454 test_pmgen -reduce_tree [options] [selection]
6456 Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.
6459 test_pmgen -eqpmux [options] [selection]
6461 Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.
6464 test_pmgen -generate [options] <pattern_name>
6466 Create modules that match the specified pattern.
6469 \section{torder -- print cells in topological order}
6471 \begin{lstlisting}[numbers=left,frame=single]
6472 torder [options] [selection]
6474 This command prints the selected cells in topological order.
6476 -stop <cell_type> <cell_port>
6477 do not use the specified cell port in topological sorting
6480 by default Q outputs of internal FF cells and memory read port outputs
6481 are not used in topological sorting. this option deactivates that.
6484 \section{trace -- redirect command output to file}
6486 \begin{lstlisting}[numbers=left,frame=single]
6489 Execute the specified command, logging all changes the command performs on
6490 the design in real time.
6493 \section{tribuf -- infer tri-state buffers}
6495 \begin{lstlisting}[numbers=left,frame=single]
6496 tribuf [options] [selection]
6498 This pass transforms $mux cells with 'z' inputs to tristate buffers.
6501 merge multiple tri-state buffers driving the same net
6502 into a single buffer.
6505 convert tri-state buffers that do not drive output ports
6506 to non-tristate logic. this option implies -merge.
6509 \section{uniquify -- create unique copies of modules}
6510 \label{cmd:uniquify}
6511 \begin{lstlisting}[numbers=left,frame=single]
6512 uniquify [selection]
6514 By default, a module that is instantiated by several other modules is only
6515 kept once in the design. This preserves the original modularity of the design
6516 and reduces the overall size of the design in memory. But it prevents certain
6517 optimizations and other operations on the design. This pass creates unique
6518 modules for all selected cells. The created modules are marked with the
6521 This commands only operates on modules that by themself have the 'unique'
6522 attribute set (the 'top' module is unique implicitly).
6525 \section{verific -- load Verilog and VHDL designs using Verific}
6527 \begin{lstlisting}[numbers=left,frame=single]
6528 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..
6530 Load the specified Verilog/SystemVerilog files into Verific.
6532 All files specified in one call to this command are one compilation unit.
6533 Files passed to different calls to this command are treated as belonging to
6534 different compilation units.
6536 Additional -D<macro>[=<value>] options may be added after the option indicating
6537 the language version (and before file names) to set additional verilog defines.
6538 The macros SYNTHESIS and VERIFIC are defined implicitly.
6541 verific -formal <verilog-file>..
6543 Like -sv, but define FORMAL instead of SYNTHESIS.
6546 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
6548 Load the specified VHDL files into Verific.
6551 verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>
6553 Load the specified Verilog/SystemVerilog/VHDL file into the specified library.
6554 (default library when -work is not present: "work")
6557 verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>
6559 Look up external definitions in the specified library.
6560 (-L may be used more than once)
6563 verific -vlog-incdir <directory>..
6565 Add Verilog include directories.
6568 verific -vlog-libdir <directory>..
6570 Add Verilog library directories. Verific will search in this directories to
6571 find undefined modules.
6574 verific -vlog-define <macro>[=<value>]..
6576 Add Verilog defines.
6579 verific -vlog-undef <macro>..
6581 Remove Verilog defines previously set with -vlog-define.
6584 verific -set-error <msg_id>..
6585 verific -set-warning <msg_id>..
6586 verific -set-info <msg_id>..
6587 verific -set-ignore <msg_id>..
6589 Set message severity. <msg_id> is the string in square brackets when a message
6590 is printed, such as VERI-1209.
6593 verific -import [options] <top-module>..
6595 Elaborate the design for the specified top modules, import to Yosys and
6596 reset the internal state of Verific.
6601 Elaborate all modules, not just the hierarchy below the given top
6602 modules. With this option the list of modules to import is optional.
6605 Create a gate-level netlist.
6608 Flatten the design in Verific before importing.
6611 Resolve references to external nets by adding module ports as needed.
6614 Generate automatic cover statements for all asserts
6617 Keep all register initializations, even those for non-FF registers.
6620 Elaborate the specified top modules (all modules when -all given) using
6621 this parameter value. Modules on which this parameter does not exist will
6622 cause Verific to produce a VERI-1928 or VHDL-1676 message. This option
6623 can be specified multiple times to override multiple parameters.
6624 String values must be passed in double quotes (").
6627 Verbose log messages. (-vv is even more verbose than -v.)
6629 The following additional import options are useful for debugging the Verific
6630 bindings (for Yosys and/or Verific developers):
6633 Keep going after an unsupported verific primitive is found. The
6634 unsupported primitive is added as blockbox module to the design.
6635 This will also add all SVA related cells to the design parallel to
6636 the checker logic inferred by it.
6639 Import Verific netlist as-is without translating to Yosys cell types.
6642 Ignore SVA properties, do not infer checker logic.
6645 Maximum number of ctrl bits for SVA checker FSMs (default=16).
6648 Keep all Verific names on instances and nets. By default only
6649 user-declared names are preserved.
6652 Dump the Verific netlist as a verilog file.
6655 Use Symbiotic EDA Suite if you need Yosys+Verifc.
6656 https://www.symbioticeda.com/seda-suite
6658 Contact office@symbioticeda.com for free evaluation
6659 binaries of Symbiotic EDA Suite.
6662 \section{verilog\_defaults -- set default options for read\_verilog}
6663 \label{cmd:verilog_defaults}
6664 \begin{lstlisting}[numbers=left,frame=single]
6665 verilog_defaults -add [options]
6667 Add the specified options to the list of default options to read_verilog.
6670 verilog_defaults -clear
6672 Clear the list of Verilog default options.
6675 verilog_defaults -push
6676 verilog_defaults -pop
6678 Push or pop the list of default options to a stack. Note that -push does
6682 \section{verilog\_defines -- define and undefine verilog defines}
6683 \label{cmd:verilog_defines}
6684 \begin{lstlisting}[numbers=left,frame=single]
6685 verilog_defines [options]
6687 Define and undefine verilog preprocessor macros.
6690 define the preprocessor symbol 'name' and set its optional value
6694 undefine the preprocessor symbol 'name'
6697 clear list of defined preprocessor symbols
6700 list currently defined preprocessor symbols
6703 \section{wbflip -- flip the whitebox attribute}
6705 \begin{lstlisting}[numbers=left,frame=single]
6708 Flip the whitebox attribute on selected cells. I.e. if it's set, unset it, and
6709 vice-versa. Blackbox cells are not effected by this command.
6712 \section{wreduce -- reduce the word size of operations if possible}
6714 \begin{lstlisting}[numbers=left,frame=single]
6715 wreduce [options] [selection]
6717 This command reduces the word size of operations. For example it will replace
6718 the 32 bit adders in the following code with adders of more appropriate widths:
6720 module test(input [3:0] a, b, c, output [7:0] y);
6721 assign y = a + b + c + 1;
6727 Do not change the width of memory address ports. Use this options in
6728 flows that use the 'memory_memx' pass.
6731 Do not optimize explicit don't-care values.
6734 \section{write\_aiger -- write design to AIGER file}
6735 \label{cmd:write_aiger}
6736 \begin{lstlisting}[numbers=left,frame=single]
6737 write_aiger [options] [filename]
6739 Write the current design to an AIGER file. The design must be flattened and
6740 must not contain any cell types except $_AND_, $_NOT_, simple FF types,
6741 $assert and $assume cells, and $initstate cells.
6743 $assert and $assume cells are converted to AIGER bad state properties and
6744 invariant constraints.
6747 write ASCII version of AIGER format
6750 convert FFs to zero-initialized FFs, adding additional inputs for
6754 design outputs are AIGER bad state properties
6757 include a symbol table in the generated AIGER file
6760 write an extra file with port and latch symbols
6763 like -map, but more verbose
6766 If the design contains no input/output/assert/flip-flop then create one
6767 dummy input/output/bad_state-pin or latch to make the tools reading the
6771 \section{write\_blif -- write design to BLIF file}
6772 \label{cmd:write_blif}
6773 \begin{lstlisting}[numbers=left,frame=single]
6774 write_blif [options] [filename]
6776 Write the current design to an BLIF file.
6779 set the specified module as design top module
6781 -buf <cell-type> <in-port> <out-port>
6782 use cells of type <cell-type> with the specified port names for buffers
6784 -unbuf <cell-type> <in-port> <out-port>
6785 replace buffer cells with the specified name and port names with
6786 a .names statement that models a buffer
6788 -true <cell-type> <out-port>
6789 -false <cell-type> <out-port>
6790 -undef <cell-type> <out-port>
6791 use the specified cell types to drive nets that are constant 1, 0, or
6792 undefined. when '-' is used as <cell-type>, then <out-port> specifies
6793 the wire name to be used for the constant signal and no cell driving
6794 that wire is generated. when '+' is used as <cell-type>, then <out-port>
6795 specifies the wire name to be used for the constant signal and a .names
6796 statement is generated to drive the wire.
6799 if a net name is aliasing another net name, then by default a net
6800 without fanout is created that is driven by the other net. This option
6801 suppresses the generation of this nets without fanout.
6803 The following options can be useful when the generated file is not going to be
6804 read by a BLIF parser but a custom tool. It is recommended to not name the output
6805 file *.blif when any of this options is used.
6808 do not translate Yosys's internal gates to generic BLIF logic
6809 functions. Instead create .subckt or .gate lines for all cells.
6812 print .gate instead of .subckt lines for all cells that are not
6813 instantiations of other modules from this design.
6816 do not generate buffers for connected wires. instead use the
6817 non-standard .conn statement.
6820 use the non-standard .attr statement to write cell attributes
6823 use the non-standard .param statement to write cell parameters
6826 use the non-standard .cname statement to write cell names
6829 enable -cname and -attr functionality for .names statements
6830 (the .cname and .attr statements will be included in the BLIF
6831 output after the truth table for the .names statement)
6834 write blackbox cells with .blackbox statement.
6837 do not write definitions for the $true, $false and $undef wires.
6840 \section{write\_btor -- write design to BTOR file}
6841 \label{cmd:write_btor}
6842 \begin{lstlisting}[numbers=left,frame=single]
6843 write_btor [options] [filename]
6845 Write a BTOR description of the current design.
6848 Add comments and indentation to BTOR output file
6851 Output only a single bad property for all asserts
6854 Output cover properties using 'bad' statements instead of asserts
6857 Create additional info file with auxiliary information
6860 \section{write\_cxxrtl -- convert design to C++ RTL simulation}
6861 \label{cmd:write_cxxrtl}
6862 \begin{lstlisting}[numbers=left,frame=single]
6863 write_cxxrtl [options] [filename]
6865 Write C++ code for simulating the design. The generated code requires a driver;
6866 the following simple driver is provided as an example:
6871 cxxrtl_design::p_top top;
6873 top.p_clk.next = value<1> {1u};
6875 top.p_clk.next = value<1> {0u};
6880 The following options are supported by this backend:
6883 set the optimization level. the default is -O5. higher optimization
6884 levels dramatically decrease compile and run time, and highest level
6885 possible for a design should be used.
6891 elide internal wires if possible.
6894 like -O1, and localize internal wires if possible.
6897 like -O2, and elide public wires not marked (*keep*) if possible.
6900 like -O3, and localize public wires not marked
(*keep*) if possible.
6903 like -O4, and run `splitnets -driver; opt_clean -purge` first.
6906 \section{write
\_edif -- write design to EDIF netlist file
}
6907 \label{cmd:write_edif
}
6908 \begin{lstlisting
}[numbers=left,frame=single
]
6909 write_edif
[options
] [filename
]
6911 Write the current design to an EDIF netlist file.
6914 set the specified module as design top module
6917 do not create "GND" and "VCC" cells. (this will produce an error
6918 if the design contains constant nets. use "hilomap" to map to custom
6919 constant drivers first)
6922 create "GND" and "VCC" cells with "Y" outputs. (the default is "G"
6923 for "GND" and "P" for "VCC".)
6926 create EDIF properties for cell attributes
6928 -pvector
{par|bra|ang
}
6929 sets the delimiting character for module port rename clauses to
6930 parentheses, square brackets, or angle brackets.
6932 Unfortunately there are different "flavors" of the EDIF file format. This
6933 command generates EDIF files for the Xilinx place&route tools. It might be
6934 necessary to make small modifications to this command when a different tool
6938 \section{write
\_file -- write a text to a file
}
6939 \label{cmd:write_file
}
6940 \begin{lstlisting
}[numbers=left,frame=single
]
6941 write_file
[options
] output_file
[input_file
]
6943 Write the text from the input file to the output file.
6946 Append to output file (instead of overwriting)
6949 Inside a script the input file can also can a here-
document:
6951 write_file hello.txt <<EOT
6956 \section{write
\_firrtl -- write design to a FIRRTL file
}
6957 \label{cmd:write_firrtl
}
6958 \begin{lstlisting
}[numbers=left,frame=single
]
6959 write_firrtl
[options
] [filename
]
6961 Write a FIRRTL netlist of the current design.
6962 The following commands are executed by this command:
6966 \section{write
\_ilang -- write design to ilang file
}
6967 \label{cmd:write_ilang
}
6968 \begin{lstlisting
}[numbers=left,frame=single
]
6969 write_ilang
[filename
]
6971 Write the current design to an 'ilang' file. (ilang is a text representation
6972 of a design in yosys's internal format.)
6975 only write selected parts of the design.
6978 \section{write
\_intersynth -- write design to InterSynth netlist file
}
6979 \label{cmd:write_intersynth
}
6980 \begin{lstlisting
}[numbers=left,frame=single
]
6981 write_intersynth
[options
] [filename
]
6983 Write the current design to an 'intersynth' netlist file. InterSynth is
6984 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
6987 do not generate celltypes and conntypes commands. i.e. just output
6988 the netlists. this is used for postsilicon synthesis.
6990 -lib <verilog_or_ilang_file>
6991 Use the specified library file for determining whether cell ports are
6992 inputs or outputs. This option can be used multiple times to specify
6993 more than one library.
6996 only write selected modules. modules must be selected entirely or
6999 http://www.clifford.at/intersynth/
7002 \section{write
\_json -- write design to a JSON file
}
7003 \label{cmd:write_json
}
7004 \begin{lstlisting
}[numbers=left,frame=single
]
7005 write_json
[options
] [filename
]
7007 Write a JSON netlist of the current design.
7010 include AIG models for the different gate types
7013 emit
32-bit or smaller fully-defined parameter values directly
7014 as JSON numbers (for compatibility with old parsers)
7017 The general syntax of the JSON output created by this command is as follows:
7023 <port_name>: <port_details>,
7027 <cell_name>: <cell_details>,
7031 <net_name>: <net_details>,
7041 Where <port_details> is:
7044 "direction": <"input" | "output" | "inout">,
7045 "bits": <bit_vector>
7048 And <cell_details> is:
7051 "hide_name": <
1 |
0>,
7052 "type": <cell_type>,
7054 <parameter_name>: <parameter_value>,
7058 <attribute_name>: <attribute_value>,
7061 "port_directions":
{
7062 <port_name>: <"input" | "output" | "inout">,
7066 <port_name>: <bit_vector>,
7071 And <net_details> is:
7074 "hide_name": <
1 |
0>,
7075 "bits": <bit_vector>
7078 The "hide_name" fields are set to
1 when the name of this cell or net is
7079 automatically created and is likely not of interest for a regular user.
7081 The "port_directions" section is only included for cells for which the
7084 Module and cell ports and nets can be single bit wide or vectors of multiple
7085 bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
7086 values referenced above are vectors of this integers. Signal bits that are
7087 connected to a constant driver are denoted as string "
0", "
1", "x", or
7088 "z" instead of a number.
7090 Bit vectors (including integers) are written as string holding the binaryrepresentation of the value. Strings are written as strings, with an appendedblank in cases of strings of the form /
[01xz
]* */.
7092 For example the following Verilog code:
7094 module test(input x, y);
7095 (* keep *) foo #(.P(
42), .Q(
1337))
7096 foo_inst (.A(
{x, y
}), .B(
{y, x
}), .C(
{4'd10,
{4{x
}}}));
7099 Translates to the following JSON output:
7106 "direction": "input",
7110 "direction": "input",
7127 "C":
[ 2,
2,
2,
2, "
0", "
1", "
0", "
1"
],
7153 The models are given as And-Inverter-Graphs (AIGs) in the following form:
7157 /*
0 */
[ <node-spec>
],
7158 /*
1 */
[ <node-spec>
],
7159 /*
2 */
[ <node-spec>
],
7165 The following node-types may be used:
7167 [ "port", <portname>, <bitindex>, <out-list>
]
7168 - the value of the specified input port bit
7170 [ "nport", <portname>, <bitindex>, <out-list>
]
7171 - the inverted value of the specified input port bit
7173 [ "and", <node-index>, <node-index>, <out-list>
]
7174 - the ANDed value of the specified nodes
7176 [ "nand", <node-index>, <node-index>, <out-list>
]
7177 - the inverted ANDed value of the specified nodes
7179 [ "true", <out-list>
]
7180 - the constant value
1
7182 [ "false", <out-list>
]
7183 - the constant value
0
7185 All nodes appear in topological order. I.e. only nodes with smaller indices
7186 are referenced by "and" and "nand" nodes.
7188 The optional <out-list> at the end of a node specification is a list of
7189 output portname and bitindex pairs, specifying the outputs driven by this node.
7191 For example, the following is the model for a
3-input
3-output $reduce_and cell
7192 inferred by the following code:
7194 module test(input
[2:
0] in, output
[2:
0] out);
7198 "$reduce_and:
3U:
3":
[
7199 /*
0 */
[ "port", "A",
0 ],
7200 /*
1 */
[ "port", "A",
1 ],
7201 /*
2 */
[ "and",
0,
1 ],
7202 /*
3 */
[ "port", "A",
2 ],
7203 /*
4 */
[ "and",
2,
3, "Y",
0 ],
7204 /*
5 */
[ "false", "Y",
1, "Y",
2 ]
7207 Future version of Yosys might add support for additional fields in the JSON
7208 format. A program processing this format must ignore all unknown fields.
7211 \section{write
\_simplec -- convert design to simple C code
}
7212 \label{cmd:write_simplec
}
7213 \begin{lstlisting
}[numbers=left,frame=single
]
7214 write_simplec
[options
] [filename
]
7216 Write simple C code for simulating the design. The C code written can be used to
7217 simulate the design in a C environment, but the purpose of this command is to
7218 generate code that works well with C-based formal verification.
7221 this will print the recursive walk used to export the modules.
7223 -i8, -i16, -i32, -i64
7224 set the maximum integer bit width to use in the generated code.
7226 THIS COMMAND IS UNDER CONSTRUCTION
7229 \section{write
\_smt2 -- write design to SMT-LIBv2 file
}
7230 \label{cmd:write_smt2
}
7231 \begin{lstlisting
}[numbers=left,frame=single
]
7232 write_smt2
[options
] [filename
]
7234 Write a SMT-LIBv2
[1] description of the current design. For a module with name
7235 '<mod>' this will declare the sort '<mod>_s' (state of the module) and will
7236 define and declare functions operating on that state.
7238 The following SMT2 functions are generated for a module with name '<mod>'.
7239 Some declarations/definitions are printed with a special comment. A prover
7240 using the SMT2 files can use those comments to collect all relevant metadata
7243 ; yosys-smt2-module <mod>
7244 (declare-sort |<mod>_s|
0)
7245 The sort representing a state of module <mod>.
7247 (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))
7248 This function must be asserted for each state to establish the
7251 ; yosys-smt2-input <wirename> <width>
7252 ; yosys-smt2-output <wirename> <width>
7253 ; yosys-smt2-register <wirename> <width>
7254 ; yosys-smt2-wire <wirename> <width>
7255 (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))
7256 (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)
7257 For each port, register, and wire with the 'keep' attribute set an
7258 accessor function is generated. Single-bit wires are returned as Bool,
7259 multi-bit wires as BitVec.
7261 ; yosys-smt2-cell <submod> <instancename>
7262 (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)
7263 There is a function like that for each hierarchical instance. It
7264 returns the sort that represents the state of the sub-module that
7265 implements the instance.
7267 (declare-fun |<mod>_is| (|<mod>_s|) Bool)
7268 This function must be asserted 'true' for initial states, and 'false'
7271 (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))
7272 This function must be asserted 'true' for initial states. For
7273 non-initial states it must be left unconstrained.
7275 (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))
7276 This function evaluates to 'true' if the states 'state' and
7277 'next_state' form a valid state transition.
7279 (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))
7280 This function evaluates to 'true' if all assertions hold in the state.
7282 (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))
7283 This function evaluates to 'true' if all assumptions hold in the state.
7285 ; yosys-smt2-assert <id> <filename:linenum>
7286 (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))
7287 Each $assert cell is converted into one of this functions. The function
7288 evaluates to 'true' if the assert statement holds in the state.
7290 ; yosys-smt2-assume <id> <filename:linenum>
7291 (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))
7292 Each $assume cell is converted into one of this functions. The function
7293 evaluates to 'true' if the assume statement holds in the state.
7295 ; yosys-smt2-cover <id> <filename:linenum>
7296 (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))
7297 Each $cover cell is converted into one of this functions. The function
7298 evaluates to 'true' if the cover statement is activated in the state.
7303 this will print the recursive walk used to export the modules.
7306 Use a BitVec sort to represent a state instead of an uninterpreted
7307 sort. As a side-effect this will prevent use of arrays to model
7311 Use SMT-LIB
2.6 style datatypes to represent a state instead of an
7315 disable support for BitVec (FixedSizeBitVectors theory). without this
7316 option multi-bit wires are represented using the BitVec sort and
7317 support for coarse grain cells (incl. arithmetic) is enabled.
7320 disable support for memories (via ArraysEx theory). this option is
7321 implied by -nobv. only $mem cells without merged registers in
7322 read ports are supported. call "memory" with -nordff to make sure
7323 that no registers are merged into $mem read ports. '<mod>_m' functions
7324 will be generated for accessing the arrays that are used to represent
7328 create '<mod>_n' functions for all public wires. by default only ports,
7329 registers, and wires with the 'keep' attribute are exported.
7331 -tpl <template_file>
7332 use the given template file. the line containing only the token '
%%'
7333 is replaced with the regular output of this command.
7335 [1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
7336 R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
7338 ---------------------------------------------------------------------------
7342 Consider the following module (test.v). We want to prove that the output can
7343 never transition from a non-zero value to a zero value.
7345 module test(input clk, output reg
[3:
0] y);
7346 always @(posedge clk)
7350 For this proof we create the following template (test.tpl).
7352 ; we need QF_UFBV for this proof
7355 ; insert the auto-generated code here
7358 ; declare two state variables s1 and s2
7359 (declare-fun s1 () test_s)
7360 (declare-fun s2 () test_s)
7362 ; state s2 is the successor of state s1
7363 (assert (test_t s1 s2))
7365 ; we are looking for a model with y non-zero in s1
7366 (assert (distinct (|test_n y| s1) #b0000))
7368 ; we are looking for a model with y zero in s2
7369 (assert (= (|test_n y| s2) #b0000))
7371 ; is there such a model?
7374 The following yosys script will create a 'test.smt2' file for our proof:
7377 hierarchy -check; proc; opt; check -assert
7378 write_smt2 -bv -tpl test.tpl test.smt2
7380 Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
7381 from non-zero to zero in the test design.
7384 \section{write
\_smv -- write design to SMV file
}
7385 \label{cmd:write_smv
}
7386 \begin{lstlisting
}[numbers=left,frame=single
]
7387 write_smv
[options
] [filename
]
7389 Write an SMV description of the current design.
7392 this will print the recursive walk used to export the modules.
7394 -tpl <template_file>
7395 use the given template file. the line containing only the token '
%%'
7396 is replaced with the regular output of this command.
7398 THIS COMMAND IS UNDER CONSTRUCTION
7401 \section{write
\_spice -- write design to SPICE netlist file
}
7402 \label{cmd:write_spice
}
7403 \begin{lstlisting
}[numbers=left,frame=single
]
7404 write_spice
[options
] [filename
]
7406 Write the current design to an SPICE netlist file.
7409 generate multi-bit ports in MSB first order
7410 (default is LSB first)
7413 set the net name for constant
0 (default: Vss)
7416 set the net name for constant
1 (default: Vdd)
7419 prefix for not-connected nets (default: _NC)
7422 include names of internal ($-prefixed) nets in outputs
7423 (default is to use net numbers instead)
7426 set the specified module as design top module
7429 \section{write
\_table -- write design as connectivity table
}
7430 \label{cmd:write_table
}
7431 \begin{lstlisting
}[numbers=left,frame=single
]
7432 write_table
[options
] [filename
]
7434 Write the current design as connectivity table. The output is a tab-separated
7435 ASCII table with the following columns:
7444 module inputs and outputs are output using cell type and port '-' and with
7445 'pi' (primary input) or 'po' (primary output) or 'pio' as direction.
7448 \section{write
\_verilog -- write design to Verilog file
}
7449 \label{cmd:write_verilog
}
7450 \begin{lstlisting
}[numbers=left,frame=single
]
7451 write_verilog
[options
] [filename
]
7453 Write the current design to a Verilog file.
7456 without this option all internal object names (the ones with a dollar
7457 instead of a backslash prefix) are changed to short names in the
7458 format '_<number>_'.
7460 -renameprefix <prefix>
7461 insert this prefix in front of auto-generated instance names
7464 with this option no attributes are included in the output
7467 with this option attributes are included as comments in the output
7470 without this option all internal cells are converted to Verilog
7474 add initial statements with hierarchical refs to initialize FFs when
7478 32-bit constant values are by default dumped as decimal numbers,
7479 not bit pattern. This option deactivates this feature and instead
7480 will write out all constants in binary.
7483 dump
32-bit constants in decimal and without size and radix
7486 constant values that are compatible with hex output are usually
7487 dumped as hex values. This option deactivates this feature and
7488 instead will write out all constants in binary.
7491 Parameters and attributes that are specified as strings in the
7492 original input will be output as strings by this back-end. This
7493 deactivates this feature and instead will write string constants
7497 instead of initializing memories using assignments to individual
7498 elements, use the '$readmemh' function to read initialization data
7499 from a file. This data is written to a file named by appending
7500 a sequential index to the Verilog filename and replacing the extension
7501 with '.mem', e.g. 'write_verilog -extmem foo.v' writes 'foo-
1.mem',
7502 'foo-
2.mem' and so on.
7505 use 'defparam' statements instead of the Verilog-
2001 syntax for
7509 usually modules with the 'blackbox' attribute are ignored. with
7510 this option set only the modules with the 'blackbox' attribute
7511 are written to the output file.
7514 only write selected modules. modules must be selected entirely or
7518 verbose output (print new names of all renamed wires and cells)
7520 Note that RTLIL processes can't always be mapped directly to Verilog
7521 always blocks. This frontend should only be used to export an RTLIL
7522 netlist, i.e. after the "proc" pass has been used to convert all
7523 processes to logic networks and registers. A warning is generated when
7524 this command is called on a design with RTLIL processes.
7527 \section{write
\_xaiger -- write design to XAIGER file
}
7528 \label{cmd:write_xaiger
}
7529 \begin{lstlisting
}[numbers=left,frame=single
]
7530 write_xaiger
[options
] [filename
]
7532 Write the top module (according to the
(* top *) attribute or if only one module
7533 is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, ornon
(* abc9_box_id *) cells will be converted into psuedo-inputs and
7534 pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'
7535 module, if it exists.
7538 write ASCII version of AIGER format
7541 write an extra file with port and box symbols
7544 \section{xilinx
\_dffopt -- Xilinx: optimize FF control signal usage
}
7545 \label{cmd:xilinx_dffopt
}
7546 \begin{lstlisting
}[numbers=left,frame=single
]
7547 xilinx_dffopt
[options
] [selection
]
7549 Converts hardware clock enable and set/reset signals on FFs to emulation
7550 using LUTs, if doing so would improve area. Operates on post-techmap Xilinx
7554 Assume a LUT4-based device (instead of a LUT6-based device).
7557 \section{xilinx
\_dsp -- Xilinx: pack resources into DSPs
}
7558 \label{cmd:xilinx_dsp
}
7559 \begin{lstlisting
}[numbers=left,frame=single
]
7560 xilinx_dsp
[options
] [selection
]
7562 Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),
7563 pipeline registers (M; with optional enable/reset), output registers (P; with
7564 optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.
7566 Multiply-accumulate operations using the post-adder with feedback on the 'C'
7567 input will be folded into the DSP. In this scenario only, the 'C' input can be
7568 used to override the current accumulation result with a new value, which will
7569 be added to the multiplier result to form the next accumulation result.
7571 Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'
7572 connections (optionally, where 'P' is right-shifted by
17-bits and used as an
7573 input to the post-adder -- a pattern common for summing partial products to
7574 implement wide multipliers). Limited support also exists for similar cascading
7575 for A and B using '
[AB
]COUT' -> '
[AB
]CIN'. Currently, cascade chains are limited
7576 to a maximum length of
20 cells, corresponding to the smallest Xilinx
7 Series
7579 This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set
7583 Experimental feature: addition/subtractions less than
12 or
24 bits with the
7584 '
(* use_dsp="simd" *)' attribute attached to the output wire or attached to
7585 the add/subtract operator will cause those operations to be implemented using
7586 the 'SIMD' feature of DSPs.
7588 Experimental feature: the presence of a `$ge' cell attached to the registered
7589 P output implementing the operation "(P >= <power-of-
2>)" will be transformed
7590 into using the DSP48E1's pattern detector feature for overflow detection.
7592 -family
{xcup|xcu|xc7|xc6v|xc5v|xc4v|xc6s|xc3sda
}
7593 select the family to target
7597 \section{xilinx
\_srl -- Xilinx shift register extraction
}
7598 \label{cmd:xilinx_srl
}
7599 \begin{lstlisting
}[numbers=left,frame=single
]
7600 xilinx_srl
[options
] [selection
]
7602 This pass converts chains of built-in flops (bit-level: $_DFF_
[NP
]_, $_DFFE_*
7603 and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a
7604 $__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,
7605 enable, and enable polarity (where relevant).
7606 Flops with resets cannot be mapped to Xilinx devices and will not be inferred.
7608 min length of shift register (default =
3)
7611 infer fixed-length shift registers.
7614 infer variable-length shift registers (i.e. fixed-length shifts where
7615 each element also fans-out to a $shiftx cell).
7618 \section{zinit -- add inverters so all FF are zero-initialized
}
7620 \begin{lstlisting
}[numbers=left,frame=single
]
7621 zinit
[options
] [selection
]
7623 Add inverters as needed to make all FFs zero-initialized.
7626 also add zero initialization to uninitialized FFs
projects / yosys.git / blob