1 % Generated using the yosys 'help -write-tex-command-reference-manual' command.
3 \section{abc -- use ABC for technology mapping
}
5 \begin{lstlisting
}[numbers=left,frame=single
]
6 abc
[options
] [selection
]
8 This pass uses the ABC tool
[1] for technology mapping of yosys's internal gate
9 library to a target architecture.
12 use the specified command name instead of "yosys-abc" to execute ABC.
13 This can e.g. be used to call a specific version of ABC or a wrapper.
16 use the specified ABC script file instead of the default script.
18 if <file> starts with a plus sign (+), then the rest of the filename
19 string is interprated as the command string to be passed to ABC. the
20 leading plus sign is removed and all commas (,) in the string are
21 replaced with blanks before the string is passed to ABC.
23 if no -script parameter is given, the following scripts are used:
25 for -liberty without -constr:
26 strash; scorr -v; ifraig -v; retime -v
{D
}; strash; dch -vf;
29 for -liberty with -constr:
30 strash; scorr -v; ifraig -v; retime -v
{D
}; strash; dch -vf;
31 map -v
{D
}; buffer -v; upsize -v
{D
}; dnsize -v
{D
};
35 strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v
38 strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v
41 use different default scripts that are slightly faster (at the cost
44 for -liberty without -constr:
45 retime -v
{D
}; map -v
{D
}
47 for -liberty with -constr:
48 retime -v
{D
}; map -v
{D
}; buffer -v; upsize -v
{D
};
49 dnsize -v
{D
}; stime -p
58 generate netlists for the specified cell library (using the liberty
62 pass this file with timing constraints to ABC. use with -liberty.
64 a constr file contains two lines:
65 set_driving_cell <cell_name>
66 set_load <floating_point_number>
68 the set_driving_cell statement defines which cell type is assumed to
69 drive the primary inputs and the set_load statement sets the load in
70 femtofarads for each primary output.
73 set delay target. the string
{D
} in the default scripts above is
74 replaced by this option when used, and an empty string otherwise.
77 generate netlist using luts of (max) the specified width.
80 also pass $_DFF_?_ cells through ABC (only one clock domain, if many
81 clock domains are present in a module, the one with the largest number
82 of $_DFF_?_ cells in it is used)
85 use the specified clock domain. (when this option is used in combination
86 with -dff, then it falls back to the automatic dection of clock domain
87 if the specified clock is not found in a module.)
90 set the "keep" attribute on flip-flop output wires. (and thus preserve
91 them, for example for equivialence checking.)
94 when this option is used, the temporary files created by this pass
95 are not removed. this is useful for debugging.
97 When neither -liberty nor -lut is used, the Yosys standard cell library is
98 loaded into ABC before the ABC script is executed.
100 This pass does not operate on modules with unprocessed processes in it.
101 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
103 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
106 \section{add -- add objects to the design
}
108 \begin{lstlisting
}[numbers=left,frame=single
]
109 add <command>
[selection
]
111 This command adds objects to the design. It operates on all fully selected
112 modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.
115 add
{-wire|-input|-inout|-output
} <name> <width>
[selection
]
117 Add a wire (input, inout, output port) with the given name and width. The
118 command will fail if the object exists already and has different properties
119 than the object to be created.
122 add -global_input <name> <width>
[selection
]
124 Like 'add -input', but also connect the signal between instances of the
128 \section{alumacc -- extract ALU and MACC cells
}
130 \begin{lstlisting
}[numbers=left,frame=single
]
133 This pass translates arithmetic operations $add, $mul, $lt, etc. to $alu and
137 \section{cd -- a shortcut for 'select -module <name>'
}
139 \begin{lstlisting
}[numbers=left,frame=single
]
142 This is just a shortcut for 'select -module <modname>'.
147 When no module with the specified name is found, but there is a cell
148 with the specified name in the current module, then this is equivialent
153 This is just a shortcut for 'select -clear'.
156 \section{clean -- remove unused cells and wires
}
158 \begin{lstlisting
}[numbers=left,frame=single
]
159 clean
[options
] [selection
]
161 This is identical to 'opt_clean', but less verbose.
163 When commands are separated using the ';;' token, this command will be executed
164 between the commands.
166 When commands are separated using the ';;;' token, this command will be executed
167 in -purge mode between the commands.
170 \section{connect -- create or remove connections
}
172 \begin{lstlisting
}[numbers=left,frame=single
]
173 connect
[-nomap
] [-nounset
] -set <lhs-expr> <rhs-expr>
175 Create a connection. This is equivialent to adding the statement 'assign
176 <lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing
177 drivers for <lhs-expr> are unconnected. This can be overwritten by using
181 connect
[-nomap
] -unset <expr>
183 Unconnect all existing drivers for the specified expression.
186 connect
[-nomap
] -port <cell> <port> <expr>
188 Connect the specified cell port to the specified cell port.
191 Per default signal alias names are resolved and all signal names are mapped
192 the the signal name of the primary driver. Using the -nomap option deactivates
195 The connect command operates in one module only. Either only one module must
196 be selected or an active module must be set using the 'cd' command.
198 This command does not operate on module with processes.
201 \section{connwrappers -- replace undef values with defined constants
}
202 \label{cmd:connwrappers
}
203 \begin{lstlisting
}[numbers=left,frame=single
]
204 connwrappers
[options
] [selection
]
206 Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
207 in wrapper cells with a (larger) constant port size. I.e. the upper bits
208 of the wrapper outut are signed/unsigned bit extended. This command uses this
209 knowlege to rewire the inputs of the driven cells to match the output of
212 -signed <cell_type> <port_name> <width_param>
213 -unsigned <cell_type> <port_name> <width_param>
214 consider the specified signed/unsigned wrapper output
216 -port <cell_type> <port_name> <width_param> <sign_param>
217 use the specified parameter to decide if signed or unsigned
219 The options -signed, -unsigned, and -port can be specified multiple times.
222 \section{copy -- copy modules in the design
}
224 \begin{lstlisting
}[numbers=left,frame=single
]
225 copy old_name new_name
227 Copy the specified module. Note that selection patterns are not supported
231 \section{cover -- print code coverage counters
}
233 \begin{lstlisting
}[numbers=left,frame=single
]
234 cover
[options
] [pattern
]
236 Print the code coverage counters collected using the cover() macro in the Yosys
237 C++ code. This is useful to figure out what parts of Yosys are utilized by a
241 Do not print output to the normal destination (console and/or log file)
244 Write output to this file, truncate if exists.
247 Write output to this file, append if exists.
250 Write output to a newly created file in the specified directory.
252 When one or more pattern (shell wildcards) are specified, then only counters
253 matching at least one pattern are printed.
256 It is also possible to instruct Yosys to print the coverage counters on program
257 exit to a file using environment variables:
259 YOSYS_COVER_DIR="
{dir-name
}" yosys
{args
}
261 This will create a file (with an auto-generated name) in this
262 directory and write the coverage counters to it.
264 YOSYS_COVER_FILE="
{file-name
}" yosys
{args
}
266 This will append the coverage counters to the specified file.
269 Hint: Use the following AWK command to consolidate Yosys coverage files:
271 gawk '
{ p
[$
3] = $
1; c
[$
3] += $
2;
} END
{ for (i in p)
272 printf "
%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3
275 Coverage counters are only available in debug builds of Yosys for Linux.
278 \section{delete -- delete objects in the design
}
280 \begin{lstlisting
}[numbers=left,frame=single
]
283 Deletes the selected objects. This will also remove entire modules, if the
284 whole module is selected.
287 delete
{-input|-output|-port
} [selection
]
289 Does not delete any object but removes the input and/or output flag on the
290 selected wires, thus 'deleting' module ports.
293 \section{design -- save, restore and reset current design
}
295 \begin{lstlisting
}[numbers=left,frame=single
]
298 Clear the current design.
303 Save the current design under the given name.
308 Save the current design under the given name and then clear the current design.
313 Push the current design to the stack and then clear the current design.
318 Reset the current design and pop the last design from the stack.
323 Reset the current design and load the design previously saved under the given
327 design -copy-from <name>
[-as <new_mod_name>
] <selection>
329 Copy modules from the specified design into the current one. The selection is
330 evaluated in the other design.
333 design -copy-to <name>
[-as <new_mod_name>
] [selection
]
335 Copy modules from the current design into the soecified one.
338 \section{dfflibmap -- technology mapping of flip-flops
}
339 \label{cmd:dfflibmap
}
340 \begin{lstlisting
}[numbers=left,frame=single
]
341 dfflibmap -liberty <file>
[selection
]
343 Map internal flip-flop cells to the flip-flop cells in the technology
344 library specified in the given liberty file.
346 This pass may add inverters as needed. Therefore it is recommended to
347 first run this pass and then map the logic paths to the target technology.
350 \section{dump -- print parts of the design in ilang format
}
352 \begin{lstlisting
}[numbers=left,frame=single
]
353 dump
[options
] [selection
]
355 Write the selected parts of the design to the console or specified file in
359 also dump the module headers, even if only parts of a single
363 only dump the module headers if the entire module is selected
366 write to the specified file.
369 like -outfile but append instead of overwrite
372 \section{echo -- turning echoing back of commands on and off
}
374 \begin{lstlisting
}[numbers=left,frame=single
]
377 Print all commands to log before executing them.
382 Do not print all commands to log before executing them. (default)
385 \section{eval -- evaluate the circuit given an input
}
387 \begin{lstlisting
}[numbers=left,frame=single
]
388 eval
[options
] [selection
]
390 This command evaluates the value of a signal given the value of all required
393 -set <signal> <value>
394 set the specified signal to the specified value.
397 set all unspecified source signals to undef (x)
400 create a truth table using the specified input signals
403 show the value for the specified signal. if no -show option is passed
404 then all output ports of the current module are used.
407 \section{expose -- convert internal signals to module ports
}
409 \begin{lstlisting
}[numbers=left,frame=single
]
410 expose
[options
] [selection
]
412 This command exposes all selected internal signals of a module as additional
416 only consider wires that are directly driven by register cell.
419 when exposing a wire, create an input/output pair and cut the internal
420 signal path at that wire.
423 only expose those signals that are shared ammong the selected modules.
424 this is useful for preparing modules for equivialence checking.
427 also turn connections to instances of other modules to additional
428 inputs and outputs and remove the module instances.
431 turn flip-flops to sets of inputs and outputs.
434 when creating new wire/port names, the original object name is suffixed
435 with this separator (default: '.') and the port name or a type
436 designator for the exposed signal.
439 \section{extract -- find subcircuits and replace them with cells
}
441 \begin{lstlisting
}[numbers=left,frame=single
]
442 extract -map <map_file>
[options
] [selection
]
443 extract -mine <out_file>
[options
] [selection
]
445 This pass looks for subcircuits that are isomorphic to any of the modules
446 in the given map file and replaces them with instances of this modules. The
447 map file can be a verilog source file
(*.v) or an ilang file (*.il).
450 use the modules in this file as reference. This option can be used
454 use the modules in this in-memory design as reference. This option can
455 be used multiple times.
458 print debug output while analyzing
461 also find instances with constant drivers. this may be much
462 slower than the normal operation.
465 normally builtin port swapping rules for internal cells are used per
466 default. This turns that off, so e.g. 'a^b' does not match 'b^a'
467 when this option is used.
469 -compat <needle_type> <haystack_type>
470 Per default, the cells in the map file (needle) must have the
471 type as the cells in the active design (haystack). This option
472 can be used to register additional pairs of types that should
473 match. This option can be used multiple times.
475 -swap <needle_type> <port1>,<port2>[,...]
476 Register a set of swapable ports for a needle cell type.
477 This option can be used multiple times.
479 -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
480 Register a valid permutation of swapable ports for a needle
481 cell type. This option can be used multiple times.
483 -cell_attr <attribute_name>
484 Attributes on cells with the given name must match.
486 -wire_attr <attribute_name>
487 Attributes on wires with the given name must match.
490 Do not use parameters when matching cells.
492 -ignore_param <cell_type> <parameter_name>
493 Do not use this parameter when matching cells.
495 This pass does not operate on modules with uprocessed processes in it.
496 (I.e. the 'proc' pass should be used first to convert processes to netlists.)
498 This pass can also be used for mining for frequent subcircuits. In this mode
499 the following options are to be used instead of the -map option.
502 mine for frequent subcircuits and write them to the given ilang file
504 -mine_cells_span <min> <max>
505 only mine for subcircuits with the specified number of cells
509 only mine for subcircuits with at least the specified number of matches
512 -mine_limit_matches_per_module <num>
513 when calculating the number of matches for a subcircuit, don't count
514 more than the specified number of matches per module
516 -mine_max_fanout <num>
517 don't consider internal signals with more than <num> connections
519 The modules in the map file may have the attribute 'extract_order' set to an
520 integer value. Then this value is used to determine the order in which the pass
521 tries to map the modules to the design (ascending, default value is 0).
523 See 'help techmap' for a pass that does the opposite thing.
526 \section{flatten -- flatten design}
528 \begin{lstlisting}[numbers=left,frame=single]
531 This pass flattens the design by replacing cells by their implementation. This
532 pass is very simmilar to the 'techmap' pass. The only difference is that this
533 pass is using the current design as mapping library.
536 \section{freduce -- perform functional reduction}
538 \begin{lstlisting}[numbers=left,frame=single]
539 freduce [options] [selection]
541 This pass performs functional reduction in the circuit. I.e. if two nodes are
542 equivialent, they are merged to one node and one of the redundant drivers is
543 disconnected. A subsequent call to 'clean' will remove the redundant drivers.
546 enable verbose or very verbose output
549 enable explicit handling of inverted signals
552 stop after <n> reduction operations. this is mostly used for
553 debugging the freduce command itself.
556 dump the design to <prefix>_<module>_<num>.il after each reduction
557 operation. this is mostly used for debugging the freduce command.
559 This pass is undef-aware, i.e. it considers don't-care values for detecting
562 All selected wires are considered for rewiring. The selected cells cover the
563 circuit that is analyzed.
566 \section{fsm -- extract and optimize finite state machines}
568 \begin{lstlisting}[numbers=left,frame=single]
569 fsm [options] [selection]
571 This pass calls all the other fsm_* passes in a useful order. This performs
572 FSM extraction and optimiziation. It also calls opt_clean as needed:
574 fsm_detect unless got option -nodetect
581 fsm_expand if got option -expand
582 opt_clean if got option -expand
583 fsm_opt if got option -expand
585 fsm_recode unless got option -norecode
589 fsm_export if got option -export
590 fsm_map unless got option -nomap
594 -expand, -norecode, -export, -nomap
595 enable or disable passes as indicated above
598 -fm_set_fsm_file file
599 passed through to fsm_recode pass
602 \section{fsm\_detect -- finding FSMs in design}
603 \label{cmd:fsm_detect}
604 \begin{lstlisting}[numbers=left,frame=single]
605 fsm_detect [selection]
607 This pass detects finite state machines by identifying the state signal.
608 The state signal is then marked by setting the attribute 'fsm_encoding'
609 on the state signal to "auto".
611 Existing 'fsm_encoding' attributes are not changed by this pass.
613 Signals can be protected from being detected by this pass by setting the
614 'fsm_encoding' attribute to "none".
617 \section{fsm\_expand -- expand FSM cells by merging logic into it}
618 \label{cmd:fsm_expand}
619 \begin{lstlisting}[numbers=left,frame=single]
620 fsm_expand [selection]
622 The fsm_extract pass is conservative about the cells that belong to a finite
623 state machine. This pass can be used to merge additional auxiliary gates into
624 the finate state machine.
627 \section{fsm\_export -- exporting FSMs to KISS2 files}
628 \label{cmd:fsm_export}
629 \begin{lstlisting}[numbers=left,frame=single]
630 fsm_export [-noauto] [-o filename] [-origenc] [selection]
632 This pass creates a KISS2 file for every selected FSM. For FSMs with the
633 'fsm_export' attribute set, the attribute value is used as filename, otherwise
634 the module and cell name is used as filename. If the parameter '-o' is given,
635 the first exported FSM is written to the specified filename. This overwrites
636 the setting as specified with the 'fsm_export' attribute. All other FSMs are
637 exported to the default name as mentioned above.
640 only export FSMs that have the 'fsm_export' attribute set
643 filename of the first exported FSM
646 use binary state encoding as state names instead of s0, s1, ...
649 \section{fsm\_extract -- extracting FSMs in design}
650 \label{cmd:fsm_extract}
651 \begin{lstlisting}[numbers=left,frame=single]
652 fsm_extract [selection]
654 This pass operates on all signals marked as FSM state signals using the
655 'fsm_encoding' attribute. It consumes the logic that creates the state signal
656 and uses the state signal to generate control signal and replaces it with an
659 The generated FSM cell still generates the original state signal with its
660 original encoding. The 'fsm_opt' pass can be used in combination with the
661 'opt_clean' pass to eliminate this signal.
664 \section{fsm\_info -- print information on finite state machines}
666 \begin{lstlisting}[numbers=left,frame=single]
669 This pass dumps all internal information on FSM cells. It can be useful for
670 analyzing the synthesis process and is called automatically by the 'fsm'
671 pass so that this information is included in the synthesis log file.
674 \section{fsm\_map -- mapping FSMs to basic logic}
676 \begin{lstlisting}[numbers=left,frame=single]
679 This pass translates FSM cells to flip-flops and logic.
682 \section{fsm\_opt -- optimize finite state machines}
684 \begin{lstlisting}[numbers=left,frame=single]
687 This pass optimizes FSM cells. It detects which output signals are actually
688 not used and removes them from the FSM. This pass is usually used in
689 combination with the 'opt_clean' pass (see also 'help fsm').
692 \section{fsm\_recode -- recoding finite state machines}
693 \label{cmd:fsm_recode}
694 \begin{lstlisting}[numbers=left,frame=single]
695 fsm_recode [-encoding type] [-fm_set_fsm_file file] [selection]
697 This pass reassign the state encodings for FSM cells. At the moment only
698 one-hot encoding and binary encoding is supported. The option -encoding
699 can be used to specify the encoding scheme used for FSMs without the
700 `fsm_encoding' attribute (or with the attribute set to `auto'.
702 The option -fm_set_fsm_file can be used to generate a file containing the
703 mapping from old to new FSM encoding in form of Synopsys Formality set_fsm_*
707 \section{help -- display help messages}
709 \begin{lstlisting}[numbers=left,frame=single]
710 help ............. list all commands
711 help <command> ... print help message for given command
712 help -all ........ print complete command reference
715 \section{hierarchy -- check, expand and clean up design hierarchy}
716 \label{cmd:hierarchy}
717 \begin{lstlisting}[numbers=left,frame=single]
718 hierarchy [-check] [-top <module>]
719 hierarchy -generate <cell-types> <port-decls>
721 In parametric designs, a module might exists in several variations with
722 different parameter values. This pass looks at all modules in the current
723 design an re-runs the language frontends for the parametric modules as
727 also check the design hierarchy. this generates an error when
728 an unknown module is used as cell type.
731 by default the hierarchy command will not remove library (blackbox)
732 module. use this options to also remove unused blackbox modules.
735 search for files named <module_name>.v in the specified directory
736 for unknown modules and automatically run read_verilog for each
740 per default this pass also converts positional arguments in cells
741 to arguments using port names. this option disables this behavior.
744 per default this pass sets the "keep" attribute on all modules
745 that directly or indirectly contain one or more $assert cells. this
746 option disables this behavior.
749 use the specified top module to built a design hierarchy. modules
750 outside this tree (unused modules) are removed.
752 when the -top option is used, the 'top' attribute will be set on the
753 specified top module. otherwise a module with the 'top' attribute set
754 will implicitly be used as top module, if such a module exists.
756 In -generate mode this pass generates blackbox modules for the given cell
757 types (wildcards supported). For this the design is searched for cells that
758 match the given types and then the given port declarations are used to
759 determine the direction of the ports. The syntax for a port declaration is:
761 {i|o|io}[@<num>]:<portname>
763 Input ports are specified with the 'i' prefix, output ports with the 'o'
764 prefix and inout ports with the 'io' prefix. The optional <num> specifies
765 the position of the port in the parameter list (needed when instanciated
766 using positional arguments). When <num> is not specified, the <portname> can
767 also contain wildcard characters.
769 This pass ignores the current selection and always operates on all modules
770 in the current design.
773 \section{hilomap -- technology mapping of constant hi- and/or lo-drivers}
775 \begin{lstlisting}[numbers=left,frame=single]
776 hilomap [options] [selection]
778 Map constants to 'tielo' and 'tiehi' driver cells.
780 -hicell <celltype> <portname>
781 Replace constant hi bits with this cell.
783 -locell <celltype> <portname>
784 Replace constant lo bits with this cell.
787 Create only one hi/lo cell and connect all constant bits
788 to that cell. Per default a separate cell is created for
792 \section{history -- show last interactive commands}
794 \begin{lstlisting}[numbers=left,frame=single]
797 This command prints all commands in the shell history buffer. This are
798 all commands executed in an interactive session, but not the commands
799 from executed scripts.
802 \section{iopadmap -- technology mapping of i/o pads (or buffers)}
804 \begin{lstlisting}[numbers=left,frame=single]
805 iopadmap [options] [selection]
807 Map module inputs/outputs to PAD cells from a library. This pass
808 can only map to very simple PAD cells. Use 'techmap' to further map
809 the resulting cells to more sophisticated PAD cells.
811 -inpad <celltype> <portname>[:<portname>]
812 Map module input ports to the given cell type with
813 the given port name. if a 2nd portname is given, the
814 signal is passed through the pad call, using the 2nd
817 -outpad <celltype> <portname>[:<portname>]
818 -inoutpad <celltype> <portname>[:<portname>]
819 Similar to -inpad, but for output and inout ports.
821 -widthparam <param_name>
822 Use the specified parameter name to set the port width.
824 -nameparam <param_name>
825 Use the specified parameter to set the port name.
828 create individual bit-wide buffers even for ports that
829 are wider. (the default behavio is to create word-wide
830 buffers use -widthparam to set the word size on the cell.)
833 \section{log -- print text and log files}
835 \begin{lstlisting}[numbers=left,frame=single]
838 Print the given string to the screen and/or the log file. This is useful for TCL
839 scripts, because the TCL command "puts" only goes to stdout but not to
843 Print the output to stdout too. This is useful when all Yosys is executed
844 with a script and the -q (quiet operation) argument to notify the user.
847 Print the output to stderr too.
850 Don't use the internal log() command. Use either -stdout or -stderr,
851 otherwise no output will be generated at all.
854 do not append a newline
857 \section{ls -- list modules or objects in modules}
859 \begin{lstlisting}[numbers=left,frame=single]
862 When no active module is selected, this prints a list of all modules.
864 When an active module is selected, this prints a list of objects in the module.
866 If a pattern is given, the objects matching the pattern are printed
868 Note that this command does not use the selection mechanism and always operates
869 on the whole design or whole active module. Use 'select -list' to show a list
870 of currently selected objects.
873 \section{maccmap -- mapping macc cells}
875 \begin{lstlisting}[numbers=left,frame=single]
876 maccmap [-unmap] [selection]
878 This pass maps $macc cells to yosys gate primitives. When the -unmap option is
879 used then the $macc cell is mapped to $and, $sub, etc. cells instead.
882 \section{memory -- translate memories to basic cells}
884 \begin{lstlisting}[numbers=left,frame=single]
885 memory [-nomap] [selection]
887 This pass calls all the other memory_* passes in a useful order:
894 memory_map (skipped if called with -nomap)
896 This converts memories to word-wide DFFs and address decoders
897 or multiport memory blocks if called with the -nomap option.
900 \section{memory\_collect -- creating multi-port memory cells}
901 \label{cmd:memory_collect}
902 \begin{lstlisting}[numbers=left,frame=single]
903 memory_collect [selection]
905 This pass collects memories and memory ports and creates generic multiport
909 \section{memory\_dff -- merge input/output DFFs into memories}
910 \label{cmd:memory_dff}
911 \begin{lstlisting}[numbers=left,frame=single]
912 memory_dff [options] [selection]
914 This pass detects DFFs at memory ports and merges them into the memory port.
915 I.e. it consumes an asynchronous memory port and the flip-flops at its
916 interface and yields a synchronous memory port.
919 do not merge registers on read ports
922 \section{memory\_map -- translate multiport memories to basic cells}
923 \label{cmd:memory_map}
924 \begin{lstlisting}[numbers=left,frame=single]
925 memory_map [selection]
927 This pass converts multiport memory cells as generated by the memory_collect
928 pass to word-wide DFFs and address decoders.
931 \section{memory\_share -- consolidate memory ports}
932 \label{cmd:memory_share}
933 \begin{lstlisting}[numbers=left,frame=single]
934 memory_share [selection]
936 This pass merges share-able memory ports into single memory ports.
938 The following methods are used to consolidate the number of memory ports:
940 - When write ports are connected to async read ports accessing the same
941 address, then this feedback path is converted to a write port with
942 byte/part enable signals.
944 - When multiple write ports access the same address then this is converted
945 to a single write port with a more complex data and/or enable logic path.
947 - When multiple write ports are never accessed at the same time (a SAT
948 solver is used to determine this), then the ports are merged into a single
951 Note that in addition to the algorithms implemented in this pass, the $memrd
952 and $memwr cells are also subject to generic resource sharing passes (and other
953 optimizations) such as opt_share.
956 \section{memory\_unpack -- unpack multi-port memory cells}
957 \label{cmd:memory_unpack}
958 \begin{lstlisting}[numbers=left,frame=single]
959 memory_unpack [selection]
961 This pass converts the multi-port $mem memory cells into individual $memrd and
962 $memwr cells. It is the counterpart to the memory_collect pass.
965 \section{miter -- automatically create a miter circuit}
967 \begin{lstlisting}[numbers=left,frame=single]
968 miter -equiv [options] gold_name gate_name miter_name
970 Creates a miter circuit for equivialence checking. The gold- and gate- modules
971 must have the same interfaces. The miter circuit will have all inputs of the
972 two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
973 output that goes high if an output mismatch between the two source modules is
977 a undef (x) bit in the gold module output will match any value in
978 the gate module output.
981 also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
982 on the miter circuit.
985 also create a cmp_* output for each gold/gate output pair.
988 also create an 'assert' cell that checks if trigger is always low.
991 call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.
994 \section{opt -- perform simple optimizations}
996 \begin{lstlisting}[numbers=left,frame=single]
997 opt [options] [selection]
999 This pass calls all the other opt_* passes in a useful order. This performs
1000 a series of trivial optimizations and cleanups. This pass executes the other
1001 passes in the following order:
1003 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1008 opt_reduce [-fine] [-full]
1012 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1013 while <changed design>
1015 When called with -fast the following script is used instead:
1018 opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]
1022 while <changed design in opt_rmdff>
1024 Note: Options in square brackets (such as [-keepdc]) are passed through to
1025 the opt_* commands when given to 'opt'.
1028 \section{opt\_clean -- remove unused cells and wires}
1029 \label{cmd:opt_clean}
1030 \begin{lstlisting}[numbers=left,frame=single]
1031 opt_clean [options] [selection]
1033 This pass identifies wires and cells that are unused and removes them. Other
1034 passes often remove cells but leave the wires in the design or reconnect the
1035 wires but leave the old cells in the design. This pass can be used to clean up
1036 after the passes that do the actual work.
1038 This pass only operates on completely selected modules without processes.
1041 also remove internal nets if they have a public name
1044 \section{opt\_const -- perform const folding}
1045 \label{cmd:opt_const}
1046 \begin{lstlisting}[numbers=left,frame=single]
1047 opt_const [options] [selection]
1049 This pass performs const folding on internal cell types with constant inputs.
1052 remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
1055 replace $mux cells with inverters or buffers when possible
1058 replace undriven nets with undef (x) constants
1061 perform fine-grain optimizations
1064 alias for -mux_undef -mux_bool -undriven -fine
1067 some optimizations change the behavior of the circuit with respect to
1068 don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
1069 all result bits to be set to x. this behavior changes when 'a+0' is
1070 replaced by 'a'. the -keepdc option disables all such optimizations.
1073 \section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
1074 \label{cmd:opt_muxtree}
1075 \begin{lstlisting}[numbers=left,frame=single]
1076 opt_muxtree [selection]
1078 This pass analyzes the control signals for the multiplexer trees in the design
1079 and identifies inputs that can never be active. It then removes this dead
1080 branches from the multiplexer trees.
1082 This pass only operates on completely selected modules without processes.
1085 \section{opt\_reduce -- simplify large MUXes and AND/OR gates}
1086 \label{cmd:opt_reduce}
1087 \begin{lstlisting}[numbers=left,frame=single]
1088 opt_reduce [options] [selection]
1090 This pass performs two interlinked optimizations:
1092 1. it consolidates trees of large AND gates or OR gates and eliminates
1095 2. it identifies duplicated inputs to MUXes and replaces them with a single
1096 input with the original control signals OR'ed together.
1099 perform fine-grain optimizations
1105 \section{opt\_rmdff -- remove DFFs with constant inputs}
1106 \label{cmd:opt_rmdff}
1107 \begin{lstlisting}[numbers=left,frame=single]
1108 opt_rmdff [selection]
1110 This pass identifies flip-flops with constant inputs and replaces them with
1114 \section{opt\_share -- consolidate identical cells}
1115 \label{cmd:opt_share}
1116 \begin{lstlisting}[numbers=left,frame=single]
1117 opt_share [-nomux] [selection]
1119 This pass identifies cells with identical type and input signals. Such cells
1120 are then merged to one cell.
1123 Do not merge MUX cells.
1126 \section{plugin -- load and list loaded plugins}
1128 \begin{lstlisting}[numbers=left,frame=single]
1131 Load and list loaded plugins.
1133 -i <plugin_filename>
1134 Load (install) the specified plugin.
1137 Register the specified alias name for the loaded plugin
1143 \section{proc -- translate processes to netlists}
1145 \begin{lstlisting}[numbers=left,frame=single]
1146 proc [options] [selection]
1148 This pass calls all the other proc_* passes in the most common order.
1158 This replaces the processes in the design with multiplexers and flip-flops.
1160 The following options are supported:
1162 -global_arst [!]<netname>
1163 This option is passed through to proc_arst.
1166 \section{proc\_arst -- detect asynchronous resets}
1167 \label{cmd:proc_arst}
1168 \begin{lstlisting}[numbers=left,frame=single]
1169 proc_arst [-global_arst [!]<netname>] [selection]
1171 This pass identifies asynchronous resets in the processes and converts them
1172 to a different internal representation that is suitable for generating
1173 flip-flop cells with asynchronous resets.
1175 -global_arst [!]<netname>
1176 In modules that have a net with the given name, use this net as async
1177 reset for registers that have been assign initial values in their
1178 declaration ('reg foobar = constant_value;'). Use the '!' modifier for
1179 active low reset signals. Note: the frontend stores the default value
1180 in the 'init' attribute on the net.
1183 \section{proc\_clean -- remove empty parts of processes}
1184 \label{cmd:proc_clean}
1185 \begin{lstlisting}[numbers=left,frame=single]
1186 proc_clean [selection]
1188 This pass removes empty parts of processes and ultimately removes a process
1189 if it contains only empty structures.
1192 \section{proc\_dff -- extract flip-flops from processes}
1193 \label{cmd:proc_dff}
1194 \begin{lstlisting}[numbers=left,frame=single]
1195 proc_dff [selection]
1197 This pass identifies flip-flops in the processes and converts them to
1198 d-type flip-flop cells.
1201 \section{proc\_init -- convert initial block to init attributes}
1202 \label{cmd:proc_init}
1203 \begin{lstlisting}[numbers=left,frame=single]
1204 proc_init [selection]
1206 This pass extracts the 'init' actions from processes (generated from verilog
1207 'initial' blocks) and sets the initial value to the 'init' attribute on the
1211 \section{proc\_mux -- convert decision trees to multiplexers}
1212 \label{cmd:proc_mux}
1213 \begin{lstlisting}[numbers=left,frame=single]
1214 proc_mux [selection]
1216 This pass converts the decision trees in processes (originating from if-else
1217 and case statements) to trees of multiplexer cells.
1220 \section{proc\_rmdead -- eliminate dead trees in decision trees}
1221 \label{cmd:proc_rmdead}
1222 \begin{lstlisting}[numbers=left,frame=single]
1223 proc_rmdead [selection]
1225 This pass identifies unreachable branches in decision trees and removes them.
1228 \section{read\_ilang -- read modules from ilang file}
1229 \label{cmd:read_ilang}
1230 \begin{lstlisting}[numbers=left,frame=single]
1231 read_ilang [filename]
1233 Load modules from an ilang file to the current design. (ilang is a text
1234 representation of a design in yosys's internal format.)
1237 \section{read\_liberty -- read cells from liberty file}
1238 \label{cmd:read_liberty}
1239 \begin{lstlisting}[numbers=left,frame=single]
1240 read_liberty [filename]
1242 Read cells from liberty file as modules into current design.
1245 only create empty blackbox modules
1248 ignore re-definitions of modules. (the default behavior is to
1249 create an error message.)
1252 ignore cells with missing function specification of outputs
1255 ignore cells with a missing or invalid direction
1256 specification on a pin
1258 -setattr <attribute_name>
1259 set the specified attribute (to the value 1) on all loaded modules
1262 \section{read\_verilog -- read modules from verilog file}
1263 \label{cmd:read_verilog}
1264 \begin{lstlisting}[numbers=left,frame=single]
1265 read_verilog [options] [filename]
1267 Load modules from a verilog file to the current design. A large subset of
1268 Verilog-2005 is supported.
1271 enable support for SystemVerilog features. (only a small subset
1272 of SystemVerilog is supported)
1275 dump abstract syntax tree (before simplification)
1278 dump abstract syntax tree (after simplification)
1281 dump ast as verilog code (after simplification)
1284 enable parser debug output
1287 usually latches are synthesized into logic loops
1288 this option prohibits this and sets the output to 'x'
1289 in what would be the latches hold condition
1291 this behavior can also be achieved by setting the
1292 'nolatches' attribute on the respective module or
1296 under certain conditions memories are converted to registers
1297 early during simplification to ensure correct handling of
1298 complex corner cases. this option disables this behavior.
1300 this can also be achieved by setting the 'nomem2reg'
1301 attribute on the respective module or register.
1304 always convert memories to registers. this can also be
1305 achieved by setting the 'mem2reg' attribute on the respective
1309 dump verilog code after pre-processor
1312 do not run the pre-processor
1315 only create empty blackbox modules
1318 don't perform basic optimizations (such as const folding) in the
1319 high-level front-end.
1322 interpret cell types starting with '$' as internal cell types
1325 ignore re-definitions of modules. (the default behavior is to
1326 create an error message.)
1329 only read the abstract syntax tree and defer actual compilation
1330 to a later 'hierarchy' command. Useful in cases where the default
1331 parameters of modules yield invalid or not synthesizable code.
1333 -setattr <attribute_name>
1334 set the specified attribute (to the value 1) on all loaded modules
1337 define the preprocessor symbol 'name' and set its optional value
1341 add 'dir' to the directories which are used when searching include
1344 The command 'verilog_defaults' can be used to register default options for
1345 subsequent calls to 'read_verilog'.
1347 Note that the Verilog frontend does a pretty good job of processing valid
1348 verilog input, but has not very good error reporting. It generally is
1349 recommended to use a simulator (for example icarus verilog) for checking
1350 the syntax of the code, rather than to rely on read_verilog for that.
1353 \section{rename -- rename object in the design}
1355 \begin{lstlisting}[numbers=left,frame=single]
1356 rename old_name new_name
1358 Rename the specified object. Note that selection patterns are not supported
1362 rename -enumerate [-pattern <pattern>] [selection]
1364 Assign short auto-generated names to all selected wires and cells with private
1365 names. The -pattern option can be used to set the pattern for the new names.
1366 The character % in the pattern is replaced with a integer number. The default
1369 rename -hide [selection]
1371 Assign private names (the ones with $-prefix) to all selected wires and cells
1372 with public names. This ignores all selected ports.
1375 \section{sat -- solve a SAT problem in the circuit}
1377 \begin{lstlisting}[numbers=left,frame=single]
1378 sat [options] [selection]
1380 This command solves a SAT problem defined over the currently selected circuit
1381 and additional constraints passed as parameters.
1384 show all solutions to the problem (this can grow exponentially, use
1385 -max <N> instead to get <N> solutions)
1388 like -all, but limit number of solutions to <N>
1391 enable modeling of undef value (aka 'x-bits')
1392 this option is implied by -set-def, -set-undef et. cetera
1395 maximize the number of undef bits in solutions, giving a better
1396 picture of which input bits are actually vital to the solution.
1398 -set <signal> <value>
1399 set the specified signal to the specified value.
1402 add a constraint that all bits of the given signal must be defined
1404 -set-any-undef <signal>
1405 add a constraint that at least one bit of the given signal is undefined
1407 -set-all-undef <signal>
1408 add a constraint that all bits of the given signal are undefined
1411 add -set-def constraints for all module inputs
1414 show the model for the specified signal. if no -show option is
1415 passed then a set of signals to be shown is automatically selected.
1417 -show-inputs, -show-outputs
1418 add all module input (output) ports to the list of shown signals
1421 ignore all solutions that involve a division by zero
1423 -ignore_unknown_cells
1424 ignore all cells that can not be matched to a SAT model
1426 The following options can be used to set up a sequential problem:
1429 set up a sequential problem with <N> time steps. The steps will
1430 be numbered from 1 to N.
1432 -set-at <N> <signal> <value>
1433 -unset-at <N> <signal>
1434 set or unset the specified signal to the specified value in the
1435 given timestep. this has priority over a -set for the same signal.
1437 -set-def-at <N> <signal>
1438 -set-any-undef-at <N> <signal>
1439 -set-all-undef-at <N> <signal>
1440 add undef constraints in the given timestep.
1442 -set-init <signal> <value>
1443 set the initial value for the register driving the signal to the value
1446 set all initial states (not set using -set-init) to undef
1449 do not force a value for the initial state but do not allow undef
1452 set all initial states (not set using -set-init) to zero
1454 -dump_vcd <vcd-file-name>
1455 dump SAT model (counter example in proof) to VCD file
1457 -dump_cnf <cnf-file-name>
1458 dump CNF of SAT problem (in DIMACS format). in temporal induction
1459 proofs this is the CNF of the first induction step.
1461 The following additional options can be used to set up a proof. If also -seq
1462 is passed, a temporal induction proof is performed.
1465 Perform a temporal induction proof. In a temporalinduction proof it is
1466 proven that the condition holds forever after the number of time steps
1467 specified using -seq.
1470 Perform a temporal induction proof. Assume an initial state with all
1471 registers set to defined values for the induction step.
1473 -prove <signal> <value>
1474 Attempt to proof that <signal> is always <value>.
1476 -prove-x <signal> <value>
1477 Like -prove, but an undef (x) bit in the lhs matches any value on
1478 the right hand side. Useful for equivialence checking.
1481 Prove that all asserts in the design hold.
1484 Do not enforce the prove-condition for the first <N> time steps.
1487 Set a maximum length for the induction.
1490 Set initial length for the induction.
1493 Maximum number of seconds a single SAT instance may take.
1496 Return an error and stop the synthesis script if the proof fails.
1499 Like -verify but do not return an error for timeouts.
1502 Return an error and stop the synthesis script if the proof succeeds.
1505 Like -falsify but do not return an error for timeouts.
1508 \section{scatter -- add additional intermediate nets}
1510 \begin{lstlisting}[numbers=left,frame=single]
1513 This command adds additional intermediate nets on all cell ports. This is used
1514 for testing the correct use of the SigMap helper in passes. If you don't know
1515 what this means: don't worry -- you only need this pass when testing your own
1516 extensions to Yosys.
1518 Use the opt_clean command to get rid of the additional nets.
1521 \section{scc -- detect strongly connected components (logic loops)}
1523 \begin{lstlisting}[numbers=left,frame=single]
1524 scc [options] [selection]
1526 This command identifies strongly connected components (aka logic loops) in the
1530 limit to loops not longer than the specified number of cells. This can
1531 e.g. be useful in identifying local loops in a module that turns out
1532 to be one gigantic SCC.
1535 Usually this command only considers internal non-memory cells. With
1536 this option set, all cells are considered. For unknown cells all ports
1537 are assumed to be bidirectional 'inout' ports.
1539 -set_attr <name> <value>
1540 -set_cell_attr <name> <value>
1541 -set_wire_attr <name> <value>
1542 set the specified attribute on all cells and/or wires that are part of
1543 a logic loop. the special token {} in the value is replaced with a
1544 unique identifier for the logic loop.
1547 replace the current selection with a selection of all cells and wires
1548 that are part of a found logic loop
1551 \section{script -- execute commands from script file}
1553 \begin{lstlisting}[numbers=left,frame=single]
1554 script <filename> [<from_label>:<to_label>]
1556 This command executes the yosys commands in the specified file.
1558 The 2nd argument can be used to only execute the section of the
1559 file between the specified labels. An empty from label is synonymous
1560 for the beginning of the file and an empty to label is synonymous
1561 for the end of the file.
1563 If only one label is specified (without ':') then only the block
1564 marked with that label (until the next label) is executed.
1567 \section{select -- modify and view the list of selected objects}
1569 \begin{lstlisting}[numbers=left,frame=single]
1570 select [ -add | -del | -set <name> ] <selection>
1571 select [ -assert-none | -assert-any ] <selection>
1572 select [ -list | -write <filename> | -count | -clear ]
1573 select -module <modname>
1575 Most commands use the list of currently selected objects to determine which part
1576 of the design to operate on. This command can be used to modify and view this
1577 list of selected objects.
1579 Note that many commands support an optional [selection] argument that can be
1580 used to override the global selection for the command. The syntax of this
1581 optional argument is identical to the syntax of the <selection> argument
1585 add or remove the given objects to the current selection.
1586 without this options the current selection is replaced.
1589 do not modify the current selection. instead save the new selection
1590 under the given name (see @<name> below). to save the current selection,
1591 use "select -set <name> %"
1594 do not modify the current selection. instead assert that the given
1595 selection is empty. i.e. produce an error if any object matching the
1599 do not modify the current selection. instead assert that the given
1600 selection is non-empty. i.e. produce an error if no object matching
1601 the selection is found.
1604 do not modify the current selection. instead assert that the given
1605 selection contains exactly N objects.
1608 list all objects in the current selection
1611 like -list but write the output to the specified file
1614 count all objects in the current selection
1617 clear the current selection. this effectively selects the whole
1618 design. it also resets the selected module (see -module). use the
1619 command 'select *' to select everything but stay in the current module.
1622 create an empty selection. the current module is unchanged.
1625 limit the current scope to the specified module.
1626 the difference between this and simply selecting the module
1627 is that all object names are interpreted relative to this
1628 module after this command until the selection is cleared again.
1630 When this command is called without an argument, the current selection
1631 is displayed in a compact form (i.e. only the module name when a whole module
1634 The <selection> argument itself is a series of commands for a simple stack
1635 machine. Each element on the stack represents a set of selected objects.
1636 After this commands have been executed, the union of all remaining sets
1637 on the stack is computed and used as selection for the command.
1639 Pushing (selecting) object when not in -module mode:
1642 select the specified module(s)
1644 <mod_pattern>/<obj_pattern>
1645 select the specified object(s) from the module(s)
1647 Pushing (selecting) object when in -module mode:
1650 select the specified object(s) from the current module
1652 A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
1653 matching module names, or one of the following:
1655 A:<pattern>, A:<pattern>=<pattern>
1656 all modules with an attribute matching the given pattern
1657 in addition to = also <, <=, >=, and > are supported
1659 An <obj_pattern> can be an object name, wildcard expression, or one of
1663 all wires with a name matching the given wildcard pattern
1665 i:<pattern>, o:<pattern>, x:<pattern>
1666 all inputs (i:), outputs (o:) or any ports (x:) with matching names
1668 s:<size>, s:<min>:<max>
1669 all wires with a matching width
1672 all memories with a name matching the given pattern
1675 all cells with a name matching the given pattern
1678 all cells with a type matching the given pattern
1681 all processes with a name matching the given pattern
1684 all objects with an attribute name matching the given pattern
1686 a:<pattern>=<pattern>
1687 all objects with a matching attribute name-value-pair.
1688 in addition to = also <, <=, >=, and > are supported
1690 r:<pattern>, r:<pattern>=<pattern>
1691 cells with matching parameters. also with <, <=, >= and >.
1694 all objects with a name matching the given pattern
1695 (i.e. 'n:' is optional as it is the default matching rule)
1698 push the selection saved prior with 'select -set <name> ...'
1700 The following actions can be performed on the top sets on the stack:
1703 push a copy of the current selection to the stack
1706 replace the stack with a union of all elements on it
1709 replace top set with its invert
1712 replace the two top sets on the stack with their union
1715 replace the two top sets on the stack with their intersection
1718 pop the top set from the stack and subtract it from the new top
1721 like %d but swap the roles of two top sets on the stack
1724 create a copy of the top set rom the stack and push it
1726 %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1727 expand top set <num1> num times according to the specified rules.
1728 (i.e. select all cells connected to selected wires and select all
1729 wires connected to selected cells) The rules specify which cell
1730 ports to use for this. the syntax for a rule is a '-' for exclusion
1731 and a '+' for inclusion, followed by an optional comma separated
1732 list of cell types followed by an optional comma separated list of
1733 cell ports in square brackets. a rule can also be just a cell or wire
1734 name that limits the expansion (is included but does not go beyond).
1735 select at most <num2> objects. a warning message is printed when this
1736 limit is reached. When '*' is used instead of <num1> then the process
1737 is repeated until no further object are selected.
1739 %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1740 %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
1741 simmilar to %x, but only select input (%ci) or output cones (%co)
1744 expand top set by selecting all wires that are (at least in part)
1745 aliases for selected wires.
1748 expand top set by adding all modules of instantiated cells in selected
1752 expand top set by selecting all modules that contain selected objects
1754 Example: the following command selects all wires that are connected to a
1755 'GATE' input of a 'SWITCH' cell:
1757 select */t:SWITCH %x:+[GATE] */t:SWITCH %d
1760 \section{setattr -- set/unset attributes on objects}
1762 \begin{lstlisting}[numbers=left,frame=single]
1763 setattr [ -mod ] [ -set name value | -unset name ]... [selection]
1765 Set/unset the given attributes on the selected objects. String values must be
1766 passed in double quotes (").
1768 When called with -mod, this command will set and unset attributes on modules
1769 instead of objects within modules.
1772 \section{setparam -- set/unset parameters on objects}
1773 \label{cmd:setparam}
1774 \begin{lstlisting}[numbers=left,frame=single]
1775 setparam [ -set name value | -unset name ]... [selection]
1777 Set/unset the given parameters on the selected cells. String values must be
1778 passed in double quotes (").
1781 \section{setundef -- replace undef values with defined constants}
1782 \label{cmd:setundef}
1783 \begin{lstlisting}[numbers=left,frame=single]
1784 setundef [options] [selection]
1786 This command replaced undef (x) constants with defined (0/1) constants.
1789 also set undriven nets to constant values
1792 replace with bits cleared (0)
1795 replace with bits set (1)
1798 replace with random bits using the specified integer als seed
1799 value for the random number generator.
1802 \section{share -- perform sat-based resource sharing}
1804 \begin{lstlisting}[numbers=left,frame=single]
1805 share [options] [selection]
1807 This pass merges shareable resources into a single resource. A SAT solver
1808 is used to determine if two resources are share-able.
1811 Per default the selection of cells that is considered for sharing is
1812 narrowed using a list of cell types. With this option all selected
1813 cells are considered for resource sharing.
1815 IMPORTANT NOTE: If the -all option is used then no cells with internal
1816 state must be selected!
1819 Per default some heuristics are used to reduce the number of cells
1820 considered for resource sharing to only large resources. This options
1821 turns this heuristics off, resulting in much more cells being considered
1822 for resource sharing.
1825 Only consider the simple part of the control logic in SAT solving, resulting
1826 in much easier SAT problems at the cost of maybe missing some oportunities
1827 for resource sharing.
1830 Only perform the first N merges, then stop. This is useful for debugging.
1833 \section{shell -- enter interactive command mode}
1835 \begin{lstlisting}[numbers=left,frame=single]
1838 This command enters the interactive command mode. This can be useful
1839 in a script to interrupt the script at a certain point and allow for
1840 interactive inspection or manual synthesis of the design at this point.
1842 The command prompt of the interactive shell indicates the current
1843 selection (see 'help select'):
1846 the entire design is selected
1849 only part of the design is selected
1852 the entire module 'modname' is selected using 'select -module modname'
1855 only part of current module 'modname' is selected
1857 When in interactive shell, some errors (e.g. invalid command arguments)
1858 do not terminate yosys but return to the command prompt.
1860 This command is the default action if nothing else has been specified
1861 on the command line.
1863 Press Ctrl-D or type 'exit' to leave the interactive shell.
1866 \section{show -- generate schematics using graphviz}
1868 \begin{lstlisting}[numbers=left,frame=single]
1869 show [options] [selection]
1871 Create a graphviz DOT file for the selected part of the design and compile it
1872 to a graphics file (usually SVG or PostScript).
1875 Run the specified command with the graphics file as parameter.
1878 Generate a graphics file in the specified format.
1879 Usually <format> is 'svg' or 'ps'.
1881 -lib <verilog_or_ilang_file>
1882 Use the specified library file for determining whether cell ports are
1883 inputs or outputs. This option can be used multiple times to specify
1884 more than one library.
1887 generate <prefix>.* instead of ~/.yosys_show.*
1889 -color <color> <object>
1890 assign the specified color to the specified object. The object can be
1891 a single selection wildcard expressions or a saved set of objects in
1892 the @<name> syntax (see "help select" for details).
1894 -label <text> <object>
1895 assign the specified label text to the specified object. The object can
1896 be a single selection wildcard expressions or a saved set of objects in
1897 the @<name> syntax (see "help select" for details).
1900 Randomly assign colors to the wires. The integer argument is the seed
1901 for the random number generator. Change the seed value if the colored
1902 graph still is ambigous. A seed of zero deactivates the coloring.
1905 annotate busses with a label indicating the width of the bus.
1908 mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED
1909 cell parameter) with an asterisk next to the port name.
1912 stretch the graph so all inputs are on the left side and all outputs
1913 (including inout ports) are on the right side.
1916 wait for the use to press enter to before returning
1919 enumerate objects with internal ($-prefixed) names
1922 do not abbeviate objects with internal ($-prefixed) names
1925 do not add the module name as graph title to the dot file
1927 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
1928 specified, 'xdot' is used to display the schematic.
1930 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
1931 unless another prefix is specified using -prefix <prefix>.
1934 \section{simplemap -- mapping simple coarse-grain cells}
1935 \label{cmd:simplemap}
1936 \begin{lstlisting}[numbers=left,frame=single]
1937 simplemap [selection]
1939 This pass maps a small selection of simple coarse-grain cells to yosys gate
1940 primitives. The following internal cell types are mapped by this pass:
1942 $not, $pos, $and, $or, $xor, $xnor
1943 $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
1944 $logic_not, $logic_and, $logic_or, $mux
1945 $sr, $dff, $dffsr, $adff, $dlatch
1948 \section{splice -- create explicit splicing cells}
1950 \begin{lstlisting}[numbers=left,frame=single]
1951 splice [options] [selection]
1953 This command adds $slice and $concat cells to the design to make the splicing
1954 of multi-bit signals explicit. This for example is useful for coarse grain
1955 synthesis, where dedidacted hardware is needed to splice signals.
1958 only select the cell ports to rewire by the cell. if the selection
1959 contains a cell, than all cell inputs are rewired, if necessary.
1962 only select the cell ports to rewire by the wire. if the selection
1963 contains a wire, than all cell ports driven by this wire are wired,
1967 it is sufficient if the driver of any bit of a cell port is selected.
1968 by default all bits must be selected.
1971 do not rewire selected module outputs.
1974 only rewire cell ports with the specified name. can be used multiple
1975 times. implies -no_output.
1978 do not rewire cell ports with the specified name. can be used multiple
1979 times. can not be combined with -port <name>.
1981 By default selected output wires and all cell ports of selected cells driven
1982 by selected wires are rewired.
1985 \section{splitnets -- split up multi-bit nets}
1986 \label{cmd:splitnets}
1987 \begin{lstlisting}[numbers=left,frame=single]
1988 splitnets [options] [selection]
1990 This command splits multi-bit nets into single-bit nets.
1992 -format char1[char2[char3]]
1993 the first char is inserted between the net name and the bit index, the
1994 second char is appended to the netname. e.g. -format () creates net
1995 names like 'mysignal(42)'. the 3rd character is the range separation
1996 character when creating multi-bit wires. the default is '[]:'.
1999 also split module ports. per default only internal signals are split.
2002 don't blindly split nets in individual bits. instead look at the driver
2003 and split nets so that no driver drives only part of a net.
2006 \section{stat -- print some statistics}
2008 \begin{lstlisting}[numbers=left,frame=single]
2009 stat [options] [selection]
2011 Print some statistics (number of objects) on the selected portion of the
2015 print design hierarchy with this module as top. if the design is fully
2016 selected and a module has the 'top' attribute set, this module is used
2017 default value for this option.
2020 annotate internal cell types with their word width.
2021 e.g. $add_8 for an 8 bit wide $add cell.
2024 \section{submod -- moving part of a module to a new submodule}
2026 \begin{lstlisting}[numbers=left,frame=single]
2029 This pass identifies all cells with the 'submod' attribute and moves them to
2030 a newly created module. The value of the attribute is used as name for the
2031 cell that replaces the group of cells with the same attribute value.
2033 This pass can be used to create a design hierarchy in flat design. This can
2034 be useful for analyzing or reverse-engineering a design.
2036 This pass only operates on completely selected modules with no processes
2040 submod -name <name> [selection]
2042 As above, but don't use the 'submod' attribute but instead use the selection.
2043 Only objects from one module might be selected. The value of the -name option
2044 is used as the value of the 'submod' attribute above.
2047 \section{synth -- generic synthesis script}
2049 \begin{lstlisting}[numbers=left,frame=single]
2052 This command runs the default synthesis script. This command does not operate
2053 on partly selected designs.
2056 use the specified module as top module (default='top')
2058 -run <from_label>[:<to_label>]
2059 only run the commands between the labels (see below). an empty
2060 from label is synonymous to 'begin', and empty to label is
2061 synonymous to the end of the command list.
2064 The following commands are executed by this synthesis command:
2067 hierarchy -check [-top <top>]
2093 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
2094 \label{cmd:synth_xilinx}
2095 \begin{lstlisting}[numbers=left,frame=single]
2096 synth_xilinx [options]
2098 This command runs synthesis for Xilinx FPGAs. This command does not operate on
2099 partly selected designs.
2102 use the specified module as top module (default='top')
2105 select architecture. the following architectures are supported:
2106 spartan6 (default), artix7, kintex7, virtex7, zynq7000
2107 (this parameter is not used by the command at the moment)
2110 write the design to the specified edif file. writing of an output file
2111 is omitted if this parameter is not specified.
2113 -run <from_label>:<to_label>
2114 only run the commands between the labels (see below). an empty
2115 from label is synonymous to 'begin', and empty to label is
2116 synonymous to the end of the command list.
2119 The following commands are executed by this synthesis command:
2122 hierarchy -check -top <top>
2141 techmap -share_map xilinx/cells.v
2145 select -set xilinx_clocks <top>/t:FDRE %x:+FDRE[C] <top>/t:FDRE %d
2146 iopadmap -inpad BUFGP O:I @xilinx_clocks
2149 select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %x:+BUFGP[I] %d
2150 iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks
2153 write_edif synth.edif
2156 \section{tcl -- execute a TCL script file}
2158 \begin{lstlisting}[numbers=left,frame=single]
2161 This command executes the tcl commands in the specified file.
2162 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
2164 The tcl command 'yosys -import' can be used to import all yosys
2165 commands directly as tcl commands to the tcl shell. The yosys
2166 command 'proc' is wrapped using the tcl command 'procs' in order
2167 to avoid a name collision with the tcl builting command 'proc'.
2170 \section{techmap -- generic technology mapper}
2172 \begin{lstlisting}[numbers=left,frame=single]
2173 techmap [-map filename] [selection]
2175 This pass implements a very simple technology mapper that replaces cells in
2176 the design with implementations given in form of a verilog or ilang source
2180 the library of cell implementations to be used.
2181 without this parameter a builtin library is used that
2182 transforms the internal RTL cells to the internal gate
2186 like -map above, but with an in-memory design instead of a file.
2189 like -map, but look for the file in the share directory (where the
2190 yosys data files are). this is mainly used internally when techmap
2191 is called from other commands.
2194 load the cell implementations as separate modules into the design
2195 instead of inlining them.
2198 only run the specified number of iterations.
2201 instead of the iterative breadth-first algorithm use a recursive
2202 depth-first algorithm. both methods should yield equivialent results,
2203 but may differ in performance.
2206 Automatically call "proc" on implementations that contain processes.
2209 this option will cause techmap to exit with an error if it can't map
2210 a selected cell. only cell types that end on an underscore are accepted
2211 as final cell types by this mode.
2213 -D <define>, -I <incdir>
2214 this options are passed as-is to the verilog frontend for loading the
2215 map file. Note that the verilog frontend is also called with the
2216 '-ignore_redef' option set.
2218 When a module in the map file has the 'techmap_celltype' attribute set, it will
2219 match cells with a type that match the text value of this attribute. Otherwise
2220 the module name will be used to match the cell.
2222 When a module in the map file has the 'techmap_simplemap' attribute set, techmap
2223 will use 'simplemap' (see 'help simplemap') to map cells matching the module.
2225 When a module in the map file has the 'techmap_maccmap' attribute set, techmap
2226 will use 'maccmap' (see 'help maccmap') to map cells matching the module.
2228 When a module in the map file has the 'techmap_wrap' attribute set, techmap
2229 will create a wrapper for the cell and then run the command string that the
2230 attribute is set to on the wrapper module.
2232 All wires in the modules from the map file matching the pattern _TECHMAP_*
2233 or *._TECHMAP_* are special wires that are used to pass instructions from
2234 the mapping module to the techmap command. At the moment the following special
2235 wires are supported:
2238 When this wire is set to a non-zero constant value, techmap will not
2239 use this module and instead try the next module with a matching
2240 'techmap_celltype' attribute.
2242 When such a wire exists but does not have a constant value after all
2243 _TECHMAP_DO_* commands have been executed, an error is generated.
2246 This wires are evaluated in alphabetical order. The constant text value
2247 of this wire is a yosys command (or sequence of commands) that is run
2248 by techmap on the module. A common use case is to run 'proc' on modules
2249 that are written using always-statements.
2251 When such a wire has a non-constant value at the time it is to be
2252 evaluated, an error is produced. That means it is possible for such a
2253 wire to start out as non-constant and evaluate to a constant value
2254 during processing of other _TECHMAP_DO_* commands.
2256 A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
2257 in this case techmap will create a copy for each distinct configuration
2258 of constant inputs and shorted inputs at this point and import the
2259 constant and connected bits into the map module. All further commands
2260 are executed in this copy. This is a very convenient way of creating
2261 optimizied specializations of techmap modules without using the special
2262 parameters described below.
2264 A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
2265 then techmap will recursively replace the cells in the module with their
2266 implementation. This is not affected by the -max_iter option.
2268 It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
2270 In addition to this special wires, techmap also supports special parameters in
2271 modules in the map file:
2274 When a parameter with this name exists, it will be set to the type name
2275 of the cell that matches the module.
2277 _TECHMAP_CONSTMSK_<port-name>_
2278 _TECHMAP_CONSTVAL_<port-name>_
2279 When this pair of parameters is available in a module for a port, then
2280 former has a 1-bit for each constant input bit and the latter has the
2281 value for this bit. The unused bits of the latter are set to undef (x).
2283 _TECHMAP_BITS_CONNMAP_
2284 _TECHMAP_CONNMAP_<port-name>_
2285 For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
2286 exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
2287 N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
2288 bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
2289 This can be used to detect shorted inputs.
2291 When a module in the map file has a parameter where the according cell in the
2292 design has a port, the module from the map file is only used if the port in
2293 the design is connected to a constant value. The parameter is then set to the
2296 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
2297 of the cell that is beeing replaced.
2299 See 'help extract' for a pass that does the opposite thing.
2301 See 'help flatten' for a pass that does flatten the design (which is
2302 esentially techmap but using the design itself as map library).
2305 \section{tee -- redirect command output to file}
2307 \begin{lstlisting}[numbers=left,frame=single]
2308 tee [-q] [-o logfile|-a logfile] cmd
2310 Execute the specified command, optionally writing the commands output to the
2311 specified logfile(s).
2314 Do not print output to the normal destination (console and/or log file)
2317 Write output to this file, truncate if exists.
2320 Write output to this file, append if exists.
2323 \section{test\_abcloop -- automatically test handling of loops in abc command}
2324 \label{cmd:test_abcloop}
2325 \begin{lstlisting}[numbers=left,frame=single]
2326 test_abcloop [options]
2328 Test handling of logic loops in ABC.
2331 create this number of circuits and test them (default = 100).
2333 -s {positive_integer}
2334 use this value as rng seed value (default = unix time).
2337 \section{test\_autotb -- generate simple test benches}
2338 \label{cmd:test_autotb}
2339 \begin{lstlisting}[numbers=left,frame=single]
2340 test_autotb [options] [filename]
2342 Automatically create primitive verilog test benches for all modules in the
2343 design. The generated testbenches toggle the input pins of the module in
2344 a semi-random manner and dumps the resulting output signals.
2346 This can be used to check the synthesis results for simple circuits by
2347 comparing the testbench output for the input files and the synthesis results.
2349 The backend automatically detects clock signals. Additionally a signal can
2350 be forced to be interpreted as clock signal by setting the attribute
2351 'gentb_clock' on the signal.
2353 The attribute 'gentb_constant' can be used to force a signal to a constant
2354 value after initialization. This can e.g. be used to force a reset signal
2355 low in order to explore more inner states in a state machine.
2358 number of iterations the test bench shuld run (default = 1000)
2361 \section{test\_cell -- automatically test the implementation of a cell type}
2362 \label{cmd:test_cell}
2363 \begin{lstlisting}[numbers=left,frame=single]
2364 test_cell [options] {cell-types}
2366 Tests the internal implementation of the given cell type (for example '$add')
2367 by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
2369 Run with 'all' instead of a cell type to run the test on all supported
2373 create this number of cell instances and test them (default = 100).
2375 -s {positive_integer}
2376 use this value as rng seed value (default = unix time).
2379 don't generate circuits. instead load the specified ilang file.
2382 pass this option to techmap.
2385 use "techmap -map +/simlib.v -max_iter 2 -autoproc"
2387 -script {script_file}
2388 instead of calling "techmap", call "script {script_file}".
2391 set some input bits to random constant values
2394 do not check SAT model or run SAT equivalence checking
2397 print additional debug information to the console
2400 create a verilog test bench to test simlib and write_verilog
2403 \section{trace -- redirect command output to file}
2405 \begin{lstlisting}[numbers=left,frame=single]
2408 Execute the specified command, logging all changes the command performs on
2409 the design in real time.
2412 \section{verific -- load Verilog and VHDL designs using Verific}
2414 \begin{lstlisting}[numbers=left,frame=single]
2415 verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
2417 Load the specified Verilog/SystemVerilog files into Verific.
2420 verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
2422 Load the specified VHDL files into Verific.
2425 verific -import [-gates] {-all | <top-module>..}
2427 Elaborate the design for the sepcified top modules, import to Yosys and
2428 reset the internal state of Verific. A gate-level netlist is created
2429 when called with -gates.
2431 Visit http://verific.com/ for more information on Verific.
2434 \section{verilog\_defaults -- set default options for read\_verilog}
2435 \label{cmd:verilog_defaults}
2436 \begin{lstlisting}[numbers=left,frame=single]
2437 verilog_defaults -add [options]
2439 Add the sepcified options to the list of default options to read_verilog.
2442 verilog_defaults -clear
2443 Clear the list of verilog default options.
2446 verilog_defaults -push verilog_defaults -pop
2447 Push or pop the list of default options to a stack. Note that -push does
2451 \section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
2452 \label{cmd:vhdl2verilog}
2453 \begin{lstlisting}[numbers=left,frame=single]
2454 vhdl2verilog [options] <vhdl-file>..
2456 This command reads VHDL source files using the 'vhdl2verilog' tool and the
2457 Yosys Verilog frontend.
2460 do not import the vhdl2verilog output. instead write it to the
2463 -vhdl2verilog_dir <directory>
2464 do use the specified vhdl2verilog installation. this is the directory
2465 that contains the setup_env.sh file. when this option is not present,
2466 it is assumed that vhdl2verilog is in the PATH environment variable.
2468 -top <top-entity-name>
2469 The name of the top entity. This option is mandatory.
2471 The following options are passed as-is to vhdl2verilog:
2473 -arch <architecture_name>
2483 vhdl2verilog can be obtained from:
2484 http://www.edautils.com/vhdl2verilog.html
2487 \section{wreduce -- reduce the word size of operations is possible}
2489 \begin{lstlisting}[numbers=left,frame=single]
2490 wreduce [options] [selection]
2492 This command reduces the word size of operations. For example it will replace
2493 the 32 bit adders in the following code with adders of more appropriate widths:
2495 module test(input [3:0] a, b, c, output [7:0] y);
2496 assign y = a + b + c + 1;
2500 \section{write\_blif -- write design to BLIF file}
2501 \label{cmd:write_blif}
2502 \begin{lstlisting}[numbers=left,frame=single]
2503 write_blif [options] [filename]
2505 Write the current design to an BLIF file.
2508 set the specified module as design top module
2510 -buf <cell-type> <in-port> <out-port>
2511 use cells of type <cell-type> with the specified port names for buffers
2513 -true <cell-type> <out-port>
2514 -false <cell-type> <out-port>
2515 use the specified cell types to drive nets that are constant 1 or 0
2517 The following options can be useful when the generated file is not going to be
2518 read by a BLIF parser but a custom tool. It is recommended to not name the output
2519 file *.blif when any of this options is used.
2522 do not translate Yosys's internal gates to generic BLIF logic
2523 functions. Instead create .subckt or .gate lines for all cells.
2526 print .gate instead of .subckt lines for all cells that are not
2527 instantiations of other modules from this design.
2530 do not generate buffers for connected wires. instead use the
2531 non-standard .conn statement.
2534 use the non-standard .param statement to write module parameters
2537 do not write definitions for the $true and $false wires.
2540 \section{write\_btor -- write design to BTOR file}
2541 \label{cmd:write_btor}
2542 \begin{lstlisting}[numbers=left,frame=single]
2543 write_btor [filename]
2545 Write the current design to an BTOR file.
2548 \section{write\_edif -- write design to EDIF netlist file}
2549 \label{cmd:write_edif}
2550 \begin{lstlisting}[numbers=left,frame=single]
2551 write_edif [options] [filename]
2553 Write the current design to an EDIF netlist file.
2556 set the specified module as design top module
2558 Unfortunately there are different "flavors" of the EDIF file format. This
2559 command generates EDIF files for the Xilinx place&route tools. It might be
2560 necessary to make small modifications to this command when a different tool
2564 \section{write\_file -- write a text to a file}
2565 \label{cmd:write_file}
2566 \begin{lstlisting}[numbers=left,frame=single]
2567 write_file [options] output_file [input_file]
2569 Write the text fron the input file to the output file.
2572 Append to output file (instead of overwriting)
2575 Inside a script the input file can also can a here-document:
2577 write_file hello.txt <<EOT
2582 \section{write\_ilang -- write design to ilang file}
2583 \label{cmd:write_ilang}
2584 \begin{lstlisting}[numbers=left,frame=single]
2585 write_ilang [filename]
2587 Write the current design to an 'ilang' file. (ilang is a text representation
2588 of a design in yosys's internal format.)
2591 only write selected parts of the design.
2594 \section{write\_intersynth -- write design to InterSynth netlist file}
2595 \label{cmd:write_intersynth}
2596 \begin{lstlisting}[numbers=left,frame=single]
2597 write_intersynth [options] [filename]
2599 Write the current design to an 'intersynth' netlist file. InterSynth is
2600 a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
2603 do not generate celltypes and conntypes commands. i.e. just output
2604 the netlists. this is used for postsilicon synthesis.
2606 -lib <verilog_or_ilang_file>
2607 Use the specified library file for determining whether cell ports are
2608 inputs or outputs. This option can be used multiple times to specify
2609 more than one library.
2612 only write selected modules. modules must be selected entirely or
2615 http://www.clifford.at/intersynth/
2618 \section{write\_spice -- write design to SPICE netlist file}
2619 \label{cmd:write_spice}
2620 \begin{lstlisting}[numbers=left,frame=single]
2621 write_spice [options] [filename]
2623 Write the current design to an SPICE netlist file.
2626 generate multi-bit ports in MSB first order
2627 (default is LSB first)
2630 set the net name for constant 0 (default: Vss)
2633 set the net name for constant 1 (default: Vdd)
2636 prefix for not-connected nets (default: _NC)
2639 set the specified module as design top module
2642 \section{write\_verilog -- write design to verilog file}
2643 \label{cmd:write_verilog}
2644 \begin{lstlisting}[numbers=left,frame=single]
2645 write_verilog [options] [filename]
2647 Write the current design to a verilog file.
2650 without this option all internal object names (the ones with a dollar
2651 instead of a backslash prefix) are changed to short names in the
2652 format '_<number>_'.
2655 with this option no attributes are included in the output
2658 with this option attributes are included as comments in the output
2661 without this option all internal cells are converted to verilog
2665 usually modules with the 'blackbox' attribute are ignored. with
2666 this option set only the modules with the 'blackbox' attribute
2667 are written to the output file.
2670 only write selected modules. modules must be selected entirely or