2 @inproceedings
{intersynth
,
3 title={Example
-driven interconnect synthesis for heterogeneous coarse
-grain reconfigurable logic
},
4 author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm
},
5 booktitle={FDL Proceeding of the
2012 Forum on Specification and Design Languages
},
10 @incollection
{intersynthFdlBookChapter
,
11 title={Methodology and Example
-Driven Interconnect Synthesis for Designing Heterogeneous Coarse
-Grain Reconfigurable Architectures
},
12 author={Johann Glaser and Clifford Wolf
},
13 booktitle={Advances in Models
, Methods
, and Tools for Complex Chip Design
--- Selected contributions from FDL'
12},
21 author = {Clifford Wolf
},
22 title = {Design and Implementation of the Yosys Open SYnthesis Suite
},
23 note = {Bachelor Thesis
, Vienna University of Technology
},
27 @unpublished
{VerilogFossEval
,
28 author = {Clifford Wolf
},
29 title = {Evaluation of Open Source Verilog Synthesis Tools for Feature
-Completeness and Extensibility
},
30 note = {Unpublished Student Research Paper
, Vienna University of Technology
},
35 title={A High
-Level Design Language for Programmable Logic Devices
},
36 author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright
},
37 journal={VLSI Design
(Manhasset NY
: CPM Publications
)},
43 author = {S
-T Cheng and G York and R K Brayton
},
44 title = {VL2MV
: A Compiler from Verilog to BLIF
-MV
},
49 author = {Peter Jamieson and Jonathan Rose
},
50 title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS
},
54 @inproceedings
{vtr2012
,
55 title={The VTR Project
: Architecture and CAD for FPGAs from Verilog to Routing
},
56 author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson
},
57 booktitle={Proceedings of the
20th ACM
/SIGDA International Symposium on Field
-Programmable Gate Arrays
},
64 author = {G D Hachtel and F Somenzi
},
65 title = {Logic Synthesis and Verification Algorithms
},
70 journal={IEEE Std
1364-2005 (Revision of IEEE Std
1364-2001)},
71 title={IEEE Standard for Verilog Hardware Description Language
},
73 doi
={10.1109/IEEESTD
.2006.99495}
76 @ARTICLE
{VerilogSynth
,
77 journal={IEEE Std
1364.1-2002},
78 title={IEEE Standard for Verilog Register Transfer Level Synthesis
},
80 doi
={10.1109/IEEESTD
.2002.94220}
84 journal={IEEE Std
1076-2008 (Revision of IEEE Std
1076-2002)}, title={IEEE Standard VHDL Language Reference Manual
},
87 doi
={10.1109/IEEESTD
.2009.4772740}
91 journal={IEEE Std
1076.6-2004 (Revision of IEEE Std
1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level
(RTL
) Synthesis
},
93 doi
={10.1109/IEEESTD
.2004.94802}
97 journal={IEEE Std
1685-2009}, title={IEEE Standard for IP
-XACT
, Standard Structure for Packaging
, Integrating
, and Reusing IP within Tools Flows
},
100 keywords={abstraction definitions
, address space specification
, bus definitions
, design environment
, EDA
, electronic design automation
, electronic system level
, ESL
, implementation constraints
, IP
-XACT
, register transfer level
, RTL
, SCRs
, semantic consistency rules
, TGI
, tight generator interface
, tool and data interoperability
, use models
, XML design meta
-data
, XML schema
},
101 doi
={10.1109/IEEESTD
.2010.5417309},}
104 author = {Aho
, Alfred V. and Sethi
, Ravi and Ullman
, Jeffrey D.
},
105 title = {Compilers
: principles
, techniques
, and tools
},
107 isbn
= {0-201-10088-6},
108 publisher = {Addison
-Wesley Longman Publishing Co.
, Inc.
},
109 address = {Boston
, MA
, USA
},
112 @INPROCEEDINGS
{Cummings00
,
113 author = {Clifford E. Cummings and Sunburst Design Inc
},
114 title = {Nonblocking Assignments in Verilog Synthesis
, Coding Styles That Kill
},
115 booktitle = {SNUG
(Synopsys Users Group
) 2000 User Papers
, section
-MC1
(1 st paper
},
120 author={D. L. Klipstein
},
121 journal={Cahners Publishing Co.
, EEE Magazine
, Vol.
15, No.
8},
122 title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects
},
126 @INPROCEEDINGS
{fsmextract
,
127 author={Yiqiong Shi and Chan Wai Ting and Bah
-Hwee Gwee and Ye Ren
},
128 booktitle={Circuits and Systems
(ISCAS
), Proceedings of
2010 IEEE International Symposium on
},
129 title={A highly efficient method for extracting FSMs from flattened gate
-level netlist
},
132 keywords={circuit CAD
;finite state machines
;microcontrollers
;FSM
;control
-intensive circuits
;finite state machines
;flattened gate
-level netlist
;state register elimination technique
;Automata
;Circuit synthesis
;Continuous wavelet transforms
;Design automation
;Digital circuits
;Hardware design languages
;Logic
;Microcontrollers
;Registers
;Signal processing
},
133 doi
={10.1109/ISCAS
.2010.5537093},}
135 @ARTICLE
{MultiLevelLogicSynth
,
136 author={Brayton
, R.K. and Hachtel
, G.D. and Sangiovanni
-Vincentelli
, A.L.
},
137 journal={Proceedings of the IEEE
},
138 title={Multilevel logic synthesis
},
143 keywords={circuit layout CAD
;integrated logic circuits
;logic CAD
;capsule summaries
;definitions
;detailed analysis
;in
-depth background
;logic decomposition
;logic minimisation
;logic synthesis
;logic synthesis techniques
;multilevel combinational logic
;multilevel logic synthesis
;notation
;perspective
;survey
;synthesis methods
;technology mapping
;testing
;Application specific integrated circuits
;Design automation
;Integrated circuit synthesis
;Logic design
;Logic devices
;Logic testing
;Network synthesis
;Programmable logic arrays
;Signal synthesis
;Silicon
},
144 doi
={10.1109/5.52213},
147 @article
{UllmannSubgraphIsomorphism
,
148 author = {Ullmann
, J. R.
},
149 title = {An Algorithm for Subgraph Isomorphism
},
151 issue_date
= {Jan.
1976},
159 doi
= {10.1145/321921.321925},
162 address = {New York
, NY
, USA
},