manual/manual.tex

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  53 pdftitle={Yosys Manual},%
  54 pdfauthor={Clifford Wolf},%
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 120 \begin{document}
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 133 \begin{center}
 134 \bf\Huge Yosys Manual
 135
 136 \bigskip
 137 \large Clifford Wolf
 138 \end{center}
 139
 140 \vfil\null
 141 \eject
 142
 143 \chapter*{Abstract}
 144 Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
 145 with the help of HDL synthesis tools.
 146
 147 In special cases such as synthesis for coarse-grain cell libraries or when
 148 testing new synthesis algorithms it might be necessary to write a custom HDL
 149 synthesis tool or add new features to an existing one. In these cases the
 150 availability of a Free and Open Source (FOSS) synthesis tool that can be used
 151 as basis for custom tools would be helpful.
 152
 153 In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was
 154 developed. This document covers the design and implementation of this tool.
 155 At the moment the main focus of Yosys lies on the high-level aspects of
 156 digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used
 157 by Yosys to perform advanced gate-level optimizations.
 158
 159 An evaluation of Yosys based on real-world designs is included. It is shown
 160 that Yosys can be used as-is to synthesize such designs. The results produced
 161 by Yosys in this tests where successfully verified using formal verification
 162 and are comparable in quality to the results produced by a commercial
 163 synthesis tool.
 164
 165 \bigskip
 166
 167 This document was originally published as bachelor thesis at the Vienna
 168 University of Technology \cite{BACC}.
 169
 170 \chapter*{Abbreviations}
 171 \begin{tabular}{ll}
 172 AIG         & And-Inverter-Graph \\
 173 ASIC        & Application-Specific Integrated Circuit \\
 174 AST         & Abstract Syntax Tree \\
 175 BDD         & Binary Decision Diagram \\
 176 BLIF        & Berkeley Logic Interchange Format \\
 177 EDA         & Electronic Design Automation \\
 178 EDIF        & Electronic Design Interchange Format \\
 179 ER Diagram  & Entity-Relationship Diagram \\
 180 FOSS        & Free and Open-Source Software \\
 181 FPGA        & Field-Programmable Gate Array \\
 182 FSM         & Finite-state machine \\
 183 HDL         & Hardware Description Language \\
 184 LPM         & Library of Parameterized Modules \\
 185 RTLIL       & RTL Intermediate Language \\
 186 RTL         & Register Transfer Level \\
 187 SAT         & Satisfiability Problem \\
 188 % SSA       & Static Single Assignment Form \\
 189 VHDL        & VHSIC Hardware Description Language \\
 190 VHSIC       & Very-High-Speed Integrated Circuit \\
 191 YOSYS       & Yosys Open SYnthesis Suite \\
 192 \end{tabular}
 193
 194 \tableofcontents
 195
 196 \include{CHAPTER_Intro}
 197 \include{CHAPTER_Basics}
 198 \include{CHAPTER_Approach}
 199 \include{CHAPTER_Overview}
 200 \include{CHAPTER_CellLib}
 201 \include{CHAPTER_Prog}
 202
 203 \include{CHAPTER_Verilog}
 204 \include{CHAPTER_Optimize}
 205 \include{CHAPTER_Techmap}
 206 % \include{CHAPTER_Eval}
 207
 208 \appendix
 209
 210 \include{CHAPTER_Auxlibs}
 211 \include{CHAPTER_Auxprogs}
 212
 213 \chapter{Command Reference Manual}
 214 \label{commandref}
 215 \input{command-reference-manual}
 216
 217 \include{CHAPTER_Appnotes}
 218 % \include{CHAPTER_StateOfTheArt}
 219
 220 \bibliography{literature}
 221 \bibliographystyle{alphadin}
 222
 223 \bibliographyweblink{weblinks}
 224 \bibliographystyleweblink{abbrv}
 225
 226 \end{document}