manual/presentation.tex

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  72
  73 \title{Yosys Open SYnthesis Suite}
  74 \author{Clifford Wolf}
  75 \institute{http://www.clifford.at/}
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  90 \begin{document}
  91
  92 \begin{frame}
  93 \titlepage
  94 \end{frame}
  95
  96 \setcounter{section}{-2}
  97
  98 \section{Abstract}
  99 \begin{frame}{Abstract}
 100 Yosys is the first full-featured open source software for Verilog HDL
 101 synthesis. It supports most of Verilog-2005 and is well tested with
 102 real-world designs from the ASIC and FPGA world.
 103
 104 \bigskip
 105 Learn how to use Yosys to create your own custom synthesis flows and
 106 discover why open source HDL synthesis is important for researchers,
 107 hobbyists, educators and engineers alike.
 108
 109 \bigskip
 110 This presentation covers basic concepts of Yosys, writing synthesis scripts
 111 for a wide range of applications, creating Yosys scripts for various
 112 non-synthesis applications (such as formal equivialence checking) and
 113 writing extensions to Yosys using the C++ API.
 114 \end{frame}
 115
 116 \section{Outline}
 117 \begin{frame}{Outline}
 118 Yosys is an Open Source Verilog synthesis tool, and more.
 119
 120 \bigskip
 121 Outline of this presentation:
 122 \begin{itemize}
 123 \item Introduction to the field and Yosys
 124 \item Yosys by example: synthesis
 125 \item Yosys by example: advanced synthesis
 126 \item Yosys by example: beyond synthesis
 127 \item Programming Yosys extensions
 128 \end{itemize}
 129 \end{frame}
 130
 131 \include{PRESENTATION_Intro}
 132 \include{PRESENTATION_ExSyn}
 133 \include{PRESENTATION_ExAdv}
 134 \include{PRESENTATION_ExOth}
 135 \include{PRESENTATION_Prog}
 136
 137 \end{document}