manual/presentation.tex

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  81
  82 \title{Yosys Open SYnthesis Suite}
  83 \author{Clifford Wolf}
  84 \institute{http://www.clifford.at/yosys/}
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  98
  99 \begin{document}
 100
 101 \begin{frame}
 102 \titlepage
 103 \end{frame}
 104
 105 \setcounter{section}{-2}
 106
 107 \section{Abstract}
 108 \begin{frame}{Abstract}
 109 Yosys is the first full-featured open source software for Verilog HDL
 110 synthesis. It supports most of Verilog-2005 and is well tested with
 111 real-world designs from the ASIC and FPGA world.
 112
 113 \bigskip
 114 Learn how to use Yosys to create your own custom synthesis flows and
 115 discover why open source HDL synthesis is important for researchers,
 116 hobbyists, educators and engineers alike.
 117
 118 \bigskip
 119 This presentation covers basic concepts of Yosys, writing synthesis scripts
 120 for a wide range of applications, creating Yosys scripts for various
 121 non-synthesis applications (such as formal equivialence checking) and
 122 writing extensions to Yosys using the C++ API.
 123 \end{frame}
 124
 125 \section{Outline}
 126 \begin{frame}{Outline}
 127 Yosys is an Open Source Verilog synthesis tool, and more.
 128
 129 \bigskip
 130 Outline of this presentation:
 131 \begin{itemize}
 132 \item Introduction to the field and Yosys
 133 \item Yosys by example: synthesis
 134 \item Yosys by example: advanced synthesis
 135 \item Yosys by example: beyond synthesis
 136 \item Writing Yosys extensions in C++
 137 \end{itemize}
 138 \end{frame}
 139
 140 \include{PRESENTATION_Intro}
 141 \include{PRESENTATION_ExSyn}
 142 \include{PRESENTATION_ExAdv}
 143 \include{PRESENTATION_ExOth}
 144 \include{PRESENTATION_Prog}
 145
 146 \end{document}