manual/presentation.tex

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  62
  63 \title{Yosys Open SYnthesis Suite}
  64 \author{Clifford Wolf}
  65 \institute{http://www.clifford.at/}
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  79
  80 \begin{document}
  81
  82 \begin{frame}
  83 \titlepage
  84 \end{frame}
  85
  86 \setcounter{section}{-2}
  87
  88 \section{Abstract}
  89 \begin{frame}{Abstract}
  90 Yosys is the first full-featured open source software for Verilog HDL
  91 synthesis. It supports most of Verilog-2005 and is well tested with
  92 real-world designs from the ASIC and FPGA world.
  93
  94 \bigskip
  95 Learn how to use Yosys to create your own custom synthesis flows and discover
  96 why open source HDL synthesis is important for researchers, hobbyists,
  97 educators and engineers alike.
  98
  99 \bigskip
 100 This presentation covers basic concepts of Yosys, creating simple synthesis
 101 scripts, creating synthesis scripts for advanced applications, creating Yosys
 102 scripts for non-synthesis applications (such as formal equivialence checking)
 103 and writing extensions to Yosys using the C++ API.
 104 \end{frame}
 105
 106 \section{Outline}
 107 \begin{frame}{Outline}
 108 Yosys is an Open Source Verilog synthesis tool, and more.
 109
 110 \bigskip
 111 Outline of this presentation:
 112 \begin{itemize}
 113 \item Introduction to the field and Yosys
 114 \item Yosys by example: synthesis
 115 \item Yosys by example: advanced synthesis
 116 \item Yosys by example: beyond synthesis
 117 \item Programming Yosys extensions
 118 \end{itemize}
 119 \end{frame}
 120
 121 \include{PRESENTATION_Intro}
 122 \include{PRESENTATION_ExSyn}
 123 \include{PRESENTATION_ExAdv}
 124 \include{PRESENTATION_ExOth}
 125 \include{PRESENTATION_Prog}
 126
 127 \end{document}