manual/weblinks.bib

   1
   2 @misc{YosysGit,
   3         author =        {Clifford Wolf},
   4         title =         {{Yosys Open SYnthesis Suite (YOSYS)}},
   5         note =          {\url{http://github.com/cliffordwolf/yosys}}
   6 }
   7
   8 @misc{YosysTestsGit,
   9         author =        {Clifford Wolf},
  10         title =         {{Yosys Test Bench}},
  11         note =          {\url{http://github.com/cliffordwolf/yosys-tests}}
  12 }
  13
  14 @misc{VlogHammer,
  15         author =        {Clifford Wolf},
  16         title =         {{VlogHammer Verilog Synthesis Regression Tests}},
  17         note =          {\url{http://github.com/cliffordwolf/VlogHammer}}
  18 }
  19
  20 @misc{Icarus,
  21         author =        {Stephen Williams},
  22         title =         {{Icarus Verilog}},
  23         note =          {Version 0.8.7, \url{http://iverilog.icarus.com/}}
  24 }
  25
  26 @misc{VTR,
  27         author=         {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
  28         title =         {{The Verilog-to-Routing (VTR) Project for FPGAs}},
  29         note =          {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
  30 }
  31
  32 @misc{HANA,
  33         author =        {Parvez Ahmad},
  34         title =         {{HDL Analyzer and Netlist Architect (HANA)}},
  35         note =          {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
  36 }
  37
  38 @misc{MVSIS,
  39         author =        {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
  40         title =         {{MVSIS: Logic Synthesis and Verification}},
  41         note =          {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
  42 }
  43
  44 @misc{VIS,
  45         author =        {{The VIS group}},
  46         title =         {{VIS: A system for Verification and Synthesis}},
  47         note =          {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
  48 }
  49
  50 @misc{ABC,
  51         author =        {{Berkeley Logic Synthesis and Verification Group}},
  52         title =         {{ABC: A System for Sequential Synthesis and Verification}},
  53         note =          {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
  54 }
  55
  56 @misc{AIGER,
  57         author =        {{Armin Biere, Johannes Kepler University Linz, Austria}},
  58         title =         {{AIGER}},
  59         note =          {\url{http://fmv.jku.at/aiger/}}
  60 }
  61
  62 @misc{XilinxWebPACK,
  63         author =        {{Xilinx, Inc.}},
  64         title =         {{ISE WebPACK Design Software}},
  65         note =          {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
  66 }
  67
  68 @misc{QuartusWeb,
  69         author =        {{Altera, Inc.}},
  70         title =         {{Quartus II Web Edition Software}},
  71         note =          {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
  72 }
  73
  74 @misc{OR1200,
  75         title =         {{OpenRISC 1200 CPU}},
  76         note =          {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
  77 }
  78
  79 @misc{openMSP430,
  80         title =         {{openMSP430 CPU}},
  81         note =          {\url{http://opencores.org/project,openmsp430}}
  82 }
  83
  84 @misc{i2cmaster,
  85         title =         {{OpenCores I$^2$C Core}},
  86         note =          {\url{http://opencores.org/project,i2c}}
  87 }
  88
  89 @misc{k68,
  90         title =         {{OpenCores k68 Core}},
  91         note =          {\url{http://opencores.org/project,k68}}
  92 }
  93
  94 @misc{bison,
  95         title = {{GNU Bison}},
  96         note = {\url{http://www.gnu.org/software/bison/}}
  97 }
  98
  99 @misc{flex,
 100         title = {{Flex}},
 101         note = {\url{http://flex.sourceforge.net/}}
 102 }
 103
 104 @misc{C_to_Verilog,
 105         title = {{C-to-Verilog}},
 106         note = {\url{http://www.c-to-verilog.com/}}
 107 }
 108
 109 @misc{LegUp,
 110         title = {{LegUp}},
 111         note = {\url{http://legup.eecg.utoronto.ca/}}
 112 }
 113
 114 @misc{LibertyFormat,
 115         title = {{The Liberty Library Modeling Standard}},
 116         note = {\url{http://www.opensourceliberty.org/}}
 117 }
 118
 119 @misc{ASIC-WORLD,
 120         title = {{World of ASIC}},
 121         note = {\url{http://www.asic-world.com/}}
 122 }
 123
 124 @misc{Formality,
 125         title = {{Synopsys Formality Equivalence Checking}},
 126         note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
 127 }
 128
 129 @misc{bigint,
 130         author = {Matt McCutchen},
 131         title = {{C++ Big Integer Library}},
 132         note = {\url{http://mattmccutchen.net/bigint/}}
 133 }
 134