meetings/dmitry_2023-11-24.mdwn

   1 # Friday 24th November 17:00 UTC
   2
   3 - A meeting with Dmitry, David, James, Luke, and Andrey to explain the
   4 new grants for extending SV for RISC-V.
   5
   6 Main points to take away:
   7
   8 - There will be two new grants (links below).
   9 - Meeting on Tuesday will be used for planning the binutils grant.
  10 Link to next week's meeting: [[meetings/sync_up/sync_up_2023-11-28]]
  11
  12 ## New SV Expansion Grant
  13
  14 - [[nlnet_2023_simplev_riscv]]
  15
  16 The expansion grant. Primary focus on:
  17
  18 - Add RISC-V ISA support to ISACAller.
  19 - Extend `svanalysis.py` for characterising RISC-V instructions
  20 (number of reg ports, insn type, etc.). Link to existing
  21 [svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD)
  22 - Extending existing sv for of the RISC-V Spike sim to support
  23 full feature set of SimpleV. Link to LibreSOC'
  24 [sv spike repo](https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv)
  25
  26 ## New Binutils Grant
  27
  28 - [[nlnet_2023_simplev_riscv_binutils]]
  29
  30 - Primarily Dmitry doing most of the work.
  31
  32 ## Primary Tasks
  33
  34   1. Finish writing libopid, some of the work started 4 months ago
  35 (no RfPs can be submitted for that work). Link to
  36 [repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
  37   2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid
  38    (without losing CSV files which are machine-readable by other projects)
  39   3. Create RISC-V instruction database using libopid.
  40   4. Implement SVP64 PowerISA in libopid.
  41   5. Implement SimpleV for RISC-V in libopid.
  42      - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
  43      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
  44      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.
  45
  46 The 16-bit prefix saves instruction space in memory
  47 (but with limited feature set).
  48
  49 The 32-bit prefix gives full access to SimpleV feature set
  50 (128 reg's, all SV modes such as data dependent fail-first, etc.)
  51
  52 # Defining SVPxxSingle
  53
  54 Another point mentioned after Dmitry left is the need to define SVPxxSingle.
  55
  56 For both RISC-V and PowerISA need to define:
  57
  58 - SVP16Single
  59 - SVP32Single
  60 - SVP64Single
  61
  62 *(Andrey: Why do these need to be defined for PowerISA?
  63 To also save on instruction memory?)*
  64
  65 Doing this work for both ISAs at the same time isn't too difficult,
  66 as the SVPxxSingle format will be the same for both ISAs.
  67 By defining SV format to be the same across ISAs saves effort
  68 and helps future programmers to switch from one ISA to another
  69 with minimal adjustment...*perhaps except for x86*...)
  70
  71 [[!tag meeting2023]]
  72