meetings/dmitry_2023-11-24.mdwn

   1 # Friday 24th November
   2
   3 - A meeting with Dmitry, David, James, Luke, and Andrey to explain the
   4 new grants for extending SV for RISC-V.
   5
   6 Main points to take away:
   7 - There will be two new grants.
   8 - Meeting on Tuesday will be used for planning the binutils grant.
   9 Link to next week's meeting: [[meetings/sync_up/sync_up_2023-11-28]]
  10
  11 ## New SV Expansion Grant
  12
  13 - [[nlnet_2023_simplev_riscv]]
  14
  15 The expansion grant. Primary focus on:
  16
  17 - Add RISC-V ISA support to ISACAller.
  18 - Extend `svanalysis.py` for characterising RISC-V instructions
  19 (number of reg ports, insn type, etc.). Link to existing
  20 [svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD)
  21 - Extending existing sv for of the RISC-V Spike sim to support
  22 full feature set of SimpleV. Link to LibreSOC'
  23 [sv spike repo](https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv)
  24
  25 ## New Binutils Grant
  26
  27 - [[nlnet_2023_svp64_riscv_binutils]]
  28
  29 - Primarily Dmitry doing most of the work.
  30
  31 ## Primary Tasks
  32
  33   1. Finish writing libopid, some of the work started 4 months ago
  34 (no RfPs will be submitted for that work). Link to
  35 [repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
  36   2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid.
  37   3. Create RISC-V instruction database using libopid.
  38   4. Implement SVP64 PowerISA in libopid.
  39   5. Implement SV for RISC-V in libopid.
  40      - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
  41      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
  42      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.
  43
  44 The 16-bit prefix saves instruction space in memory
  45 (but with limited feature set).
  46
  47 The 32-bit prefix gives full access to SimpleV feature set
  48 (128 reg's, all SV modes such as data dependent fail-first, etc.)
  49
  50 # Defining SVPxxSingle
  51
  52 Another point mentioned after Dmitry left is the need to define SVPxxSingle.
  53
  54 For both RISC-V and PowerISA need to define:
  55
  56 - SVP16Single
  57 - SVP32Single
  58 - SVP64Single
  59
  60 *(Andrey: Why do these need to be defined for PowerISA?
  61 To also save on instruction memory?)*
  62
  63 Doing this work for both ISAs at the same time isn't too difficult,
  64 as the SVPxxSingle format will be the same for both ISAs.
  65 By defining SV format to be the same across ISAs saves effort
  66 and helps future programmers to switch from one ISA to another
  67 with minimal adjustment...*perhaps except for x86*...)
  68
  69 [[!tag meeting2023]]
  70