meetings/sync_up/sync_up_2023-11-07.mdwn

   1 # Tuesday 7th Nov
   2
   3 TODO: Finish filling up from notes
   4
   5 * Previous weeks' notes: NA
   6 * Next weeks' notes: [[meetings/sync_up/2023-11-14_15]]
   7
   8 ## Sadoon
   9
  10 -
  11
  12 ## Jacob
  13
  14 - Made necessary fixes to pseudo-code to get a whole bunch of simulator
  15 tests working. [bug #1177](https://bugs.libre-soc.org/show_bug.cgi?id=1177)
  16 - Quoting Jacob:
  17   - "yeah, i made the changes since coping all insn inputs made TRAP
  18     not quite work since it modifies the SRR0/1 in self.spr instead of
  19     the locals in the compiled pseudo-code
  20     otherwise i'd have to change the parser to feed all locals into TRAP"
  21
  22 ## Andrey
  23
  24 # Wednesday 8th November
  25
  26 ## Cesar
  27
  28 - nextpnr-xilinx has issues with 2.5V I/O.
  29   - FPGA split I/O split into banks, each bank has its own voltage.
  30   - For now ignore switches/LEDs, test UART as it's at 3.3V
  31 (and that's enough for Libre-SOC).
  32   - Need to make a bug report in upstream nextpnr-xilinx.
  33
  34 - LD/ST CompUnit (CU) formal verification:
  35   - During test, CompUnit communicates with scoreboard and registerfiles.
  36   - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
  37 store result to regfile.
  38   - Put counters for those tests. Counter values must match
  39 (fetch reg's only once, read ALU only *after* operands have been written).
  40
  41 - FOSDEM:
  42   - Suggested people to invite:
  43     - [Matt Venn](https://www.mattvenn.net/)
  44 ([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
  45     - Mohamed Kassem ([e-fabless](https://efabless.com/))
  46   - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
  47 should also make the space available to other projects in the same area).
  48
  49 [[!tag meeting2023]]
  50 [[!tag meeting_sync_up]]