meetings/sync_up/sync_up_2023-11-07.mdwn

   1 # Tuesday 7th November 17:00 UTC
   2
   3 TODO: Finish filling up from notes
   4
   5 * Previous week's notes: NA
   6 * Next day's notes: [[meetings/sync_up/sync_up_2023-11-08]]
   7 * Next week's notes: [[meetings/sync_up/sync_up_2023-11-14]]
   8
   9 ## Sadoon
  10
  11 -
  12
  13 ## Jacob
  14
  15 - Made necessary fixes to pseudo-code to get a whole bunch of simulator
  16 tests working. [bug #1177](https://bugs.libre-soc.org/show_bug.cgi?id=1177)
  17 - Quoting Jacob:
  18   - "yeah, i made the changes since coping all insn inputs made TRAP
  19     not quite work since it modifies the SRR0/1 in self.spr instead of
  20     the locals in the compiled pseudo-code
  21     otherwise i'd have to change the parser to feed all locals into TRAP"
  22
  23 ## Andrey
  24
  25 # Wednesday 8th November
  26
  27 ## Cesar
  28
  29 - nextpnr-xilinx has issues with 2.5V I/O.
  30   - FPGA split I/O split into banks, each bank has its own voltage.
  31   - For now ignore switches/LEDs, test UART as it's at 3.3V
  32 (and that's enough for Libre-SOC).
  33   - Need to make a bug report in upstream nextpnr-xilinx.
  34
  35 - LD/ST CompUnit (CU) formal verification:
  36   - During test, CompUnit communicates with scoreboard and registerfiles.
  37   - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
  38 store result to regfile.
  39   - Put counters for those tests. Counter values must match
  40 (fetch reg's only once, read ALU only *after* operands have been written).
  41
  42 - FOSDEM:
  43   - Suggested people to invite:
  44     - [Matt Venn](https://www.mattvenn.net/)
  45 ([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
  46     - Mohamed Kassem ([e-fabless](https://efabless.com/))
  47   - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
  48 should also make the space available to other projects in the same area).
  49
  50 [[!tag meeting2023]]
  51 [[!tag meeting_sync_up]]