meetings/sync_up/sync_up_2023-11-08.mdwn

   1 # Wednesday 8th November 09:00 UTC
   2
   3 * Previous week's notes: NA
   4 * Yesterday's notes: [[meetings/sync_up/sync_up_2023-11-07]]
   5 * Next week's notes: [[meetings/sync_up/sync_up_2023-11-14]]
   6
   7 ## Cesar
   8
   9 - nextpnr-xilinx has issues with 2.5V I/O.
  10   - FPGA split I/O split into banks, each bank has its own voltage.
  11   - For now ignore switches/LEDs, test UART as it's at 3.3V
  12 (and that's enough for Libre-SOC).
  13   - Need to make a bug report in upstream nextpnr-xilinx.
  14
  15 - LD/ST CompUnit (CU) formal verification:
  16   - During test, CompUnit communicates with scoreboard and registerfiles.
  17   - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
  18 store result to regfile.
  19   - Put counters for those tests. Counter values must match
  20 (fetch reg's only once, read ALU only *after* operands have been written).
  21
  22 - FOSDEM:
  23   - Suggested people to invite:
  24     - [Matt Venn](https://www.mattvenn.net/)
  25 ([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
  26     - Mohamed Kassem ([e-fabless](https://efabless.com/))
  27   - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
  28 should also make the space available to other projects in the same area).
  29
  30 [[!tag meeting2023]]
  31 [[!tag meeting_sync_up]]