sync_up: Jacob's section
[libreriscv.git] / meetings / sync_up / sync_up_2023-11-22.mdwn
1 # Wednesday 22nd November 09:00 UTC
2
3 * Previous weeks' notes: [[meetings/sync_up/sync_up_2023-11-14]]
4 * Yesterday's notes: [[meetings/sync_up/sync_up_2023-11-21]]
5 * Next week's notes: [[meetings/sync_up/sync_up_2023-11-28]]
6
7 ## Cesar
8
9 - Been visiting family, so not much progress.
10
11 - Plan to:
12 - update FOSDEM travel costs
13 - submit talk proposal
14 - continue formal verif.
15
16 - When considering RISC-V ISA:
17 - Binutils support - covered by new potential grant application
18 - Compiler support - gcc, although initially assembly is primary
19
20 - FOSDEM:
21 - Didn't get stand, could still bring FPGA and possibly do a live demo.
22 - A new demo where hex file format could be uploaded to FPGA via UART?
23 - Might be easier to just program the SPI flash separately
24 - hex file commonly format (monitor program):
25 column, address, num of bytes, data, checksum
26
27 [[!tag meeting2023]]
28 [[!tag meeting_sync_up]]