mibuild/mibuild/crg.py

   1 from migen.fhdl.std import *
   2
   3 class SimpleCRG(Module):
   4         def __init__(self, platform, clk_name, rst_name, rst_invert=False):
   5                         reset_less = rst_name is None
   6                         self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
   7                         self._clk = platform.request(clk_name)
   8                         self.comb += self.cd_sys.clk.eq(self._clk)
   9
  10                         if not reset_less:
  11                                 if rst_invert:
  12                                         self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
  13                                 else:
  14                                         self.comb += self.cd_sys.rst.eq(platform.request(rst_name))